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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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| 1 | 2 | /* |
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| 2 | 3 | * Copyright (c) 2012, Intel Corporation |
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| 3 | 4 | * Copyright (c) 2015, Red Hat, Inc. |
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| 4 | 5 | * Copyright (c) 2015, 2016 Linaro Ltd. |
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| 5 | | - * |
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| 6 | | - * This program is free software; you can redistribute it and/or modify |
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| 7 | | - * it under the terms of the GNU General Public License version 2 as |
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| 8 | | - * published by the Free Software Foundation. |
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| 9 | | - * |
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| 10 | 6 | */ |
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| 11 | 7 | |
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| 12 | 8 | #define pr_fmt(fmt) "ACPI: SPCR: " fmt |
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| .. | .. |
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| 28 | 24 | |
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| 29 | 25 | /* |
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| 30 | 26 | * Some Qualcomm Datacenter Technologies SoCs have a defective UART BUSY bit. |
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| 31 | | - * Detect them by examining the OEM fields in the SPCR header, similiar to PCI |
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| 27 | + * Detect them by examining the OEM fields in the SPCR header, similar to PCI |
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| 32 | 28 | * quirk detection in pci_mcfg.c. |
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| 33 | 29 | */ |
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| 34 | 30 | static bool qdf2400_erratum_44_present(struct acpi_table_header *h) |
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| .. | .. |
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| 115 | 111 | table->serial_port.access_width))) { |
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| 116 | 112 | default: |
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| 117 | 113 | pr_err("Unexpected SPCR Access Width. Defaulting to byte size\n"); |
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| 118 | | - /* fall through */ |
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| 114 | + fallthrough; |
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| 119 | 115 | case 8: |
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| 120 | 116 | iotype = "mmio"; |
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| 121 | 117 | break; |
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| .. | .. |
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| 132 | 128 | switch (table->interface_type) { |
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| 133 | 129 | case ACPI_DBG2_ARM_SBSA_32BIT: |
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| 134 | 130 | iotype = "mmio32"; |
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| 135 | | - /* fall through */ |
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| 131 | + fallthrough; |
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| 136 | 132 | case ACPI_DBG2_ARM_PL011: |
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| 137 | 133 | case ACPI_DBG2_ARM_SBSA_GENERIC: |
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| 138 | 134 | case ACPI_DBG2_BCM2835: |
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