| .. | .. |
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| 1 | +// SPDX-License-Identifier: GPL-2.0-or-later |
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| 1 | 2 | /* |
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| 2 | 3 | * Performance counter support for POWER7 processors. |
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| 3 | 4 | * |
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| 4 | 5 | * Copyright 2009 Paul Mackerras, IBM Corporation. |
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| 5 | | - * |
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| 6 | | - * This program is free software; you can redistribute it and/or |
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| 7 | | - * modify it under the terms of the GNU General Public License |
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| 8 | | - * as published by the Free Software Foundation; either version |
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| 9 | | - * 2 of the License, or (at your option) any later version. |
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| 10 | 6 | */ |
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| 11 | 7 | #include <linux/kernel.h> |
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| 12 | 8 | #include <linux/perf_event.h> |
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| 13 | 9 | #include <linux/string.h> |
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| 14 | 10 | #include <asm/reg.h> |
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| 15 | 11 | #include <asm/cputable.h> |
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| 12 | + |
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| 13 | +#include "internal.h" |
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| 16 | 14 | |
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| 17 | 15 | /* |
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| 18 | 16 | * Bits in event code for POWER7 |
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| .. | .. |
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| 238 | 236 | case 6: |
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| 239 | 237 | if (psel == 0x64) |
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| 240 | 238 | return pmc >= 3; |
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| 239 | + break; |
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| 241 | 240 | case 8: |
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| 242 | 241 | return unit == 0xd; |
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| 243 | 242 | } |
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| .. | .. |
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| 245 | 244 | } |
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| 246 | 245 | |
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| 247 | 246 | static int power7_compute_mmcr(u64 event[], int n_ev, |
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| 248 | | - unsigned int hwc[], unsigned long mmcr[], struct perf_event *pevents[]) |
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| 247 | + unsigned int hwc[], struct mmcr_regs *mmcr, |
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| 248 | + struct perf_event *pevents[]) |
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| 249 | 249 | { |
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| 250 | 250 | unsigned long mmcr1 = 0; |
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| 251 | 251 | unsigned long mmcra = MMCRA_SDAR_DCACHE_MISS | MMCRA_SDAR_ERAT_MISS; |
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| .. | .. |
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| 301 | 301 | } |
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| 302 | 302 | |
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| 303 | 303 | /* Return MMCRx values */ |
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| 304 | | - mmcr[0] = 0; |
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| 304 | + mmcr->mmcr0 = 0; |
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| 305 | 305 | if (pmc_inuse & 1) |
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| 306 | | - mmcr[0] = MMCR0_PMC1CE; |
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| 306 | + mmcr->mmcr0 = MMCR0_PMC1CE; |
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| 307 | 307 | if (pmc_inuse & 0x3e) |
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| 308 | | - mmcr[0] |= MMCR0_PMCjCE; |
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| 309 | | - mmcr[1] = mmcr1; |
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| 310 | | - mmcr[2] = mmcra; |
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| 308 | + mmcr->mmcr0 |= MMCR0_PMCjCE; |
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| 309 | + mmcr->mmcr1 = mmcr1; |
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| 310 | + mmcr->mmcra = mmcra; |
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| 311 | 311 | return 0; |
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| 312 | 312 | } |
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| 313 | 313 | |
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| 314 | | -static void power7_disable_pmc(unsigned int pmc, unsigned long mmcr[]) |
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| 314 | +static void power7_disable_pmc(unsigned int pmc, struct mmcr_regs *mmcr) |
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| 315 | 315 | { |
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| 316 | 316 | if (pmc <= 3) |
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| 317 | | - mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SH(pmc)); |
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| 317 | + mmcr->mmcr1 &= ~(0xffUL << MMCR1_PMCSEL_SH(pmc)); |
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| 318 | 318 | } |
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| 319 | 319 | |
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| 320 | 320 | static int power7_generic_events[] = { |
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| .. | .. |
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| 335 | 335 | * 0 means not supported, -1 means nonsensical, other values |
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| 336 | 336 | * are event codes. |
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| 337 | 337 | */ |
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| 338 | | -static int power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { |
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| 338 | +static u64 power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { |
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| 339 | 339 | [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */ |
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| 340 | 340 | [C(OP_READ)] = { 0xc880, 0x400f0 }, |
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| 341 | 341 | [C(OP_WRITE)] = { 0, 0x300f0 }, |
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| .. | .. |
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| 444 | 444 | .cache_events = &power7_cache_events, |
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| 445 | 445 | }; |
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| 446 | 446 | |
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| 447 | | -static int __init init_power7_pmu(void) |
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| 447 | +int init_power7_pmu(void) |
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| 448 | 448 | { |
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| 449 | 449 | if (!cur_cpu_spec->oprofile_cpu_type || |
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| 450 | 450 | strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power7")) |
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| .. | .. |
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| 455 | 455 | |
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| 456 | 456 | return register_power_pmu(&power7_pmu); |
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| 457 | 457 | } |
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| 458 | | - |
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| 459 | | -early_initcall(init_power7_pmu); |
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