mk-rootfs.sh

hc

2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376

 kernel/arch/powerpc/perf/8xx-pmu.c
..
..
@@ -1,12 +1,8 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later
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 /*
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  * Performance event support - PPC 8xx
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  *
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  * Copyright 2016 Christophe Leroy, CS Systemes d'Information
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- *
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- * This program is free software; you can redistribute it and/or
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- * modify it under the terms of the GNU General Public License
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- * as published by the Free Software Foundation; either version
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- * 2 of the License, or (at your option) any later version.
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  */
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 #include <linux/kernel.h>
..
..
@@ -19,6 +15,7 @@
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 #include <asm/firmware.h>
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 #include <asm/ptrace.h>
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 #include <asm/code-patching.h>
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+#include <asm/inst.h>
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19
 
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 #define PERF_8xx_ID_CPU_CYCLES		1
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 #define PERF_8xx_ID_HW_INSTRUCTIONS	2
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..
@@ -31,9 +28,6 @@
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 extern unsigned long itlb_miss_counter, dtlb_miss_counter;
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 extern atomic_t instruction_counter;
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-extern unsigned int itlb_miss_perf, dtlb_miss_perf;
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-extern unsigned int itlb_miss_exit_1, itlb_miss_exit_2;
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-extern unsigned int dtlb_miss_exit_1, dtlb_miss_exit_2, dtlb_miss_exit_3;
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 static atomic_t insn_ctr_ref;
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 static atomic_t itlb_miss_ref;
..
..
@@ -103,22 +97,17 @@
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 		break;
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 	case PERF_8xx_ID_ITLB_LOAD_MISS:
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 		if (atomic_inc_return(&itlb_miss_ref) == 1) {
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-			unsigned long target = (unsigned long)&itlb_miss_perf;
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+			unsigned long target = patch_site_addr(&patch__itlbmiss_perf);
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-			patch_branch(&itlb_miss_exit_1, target, 0);
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-#ifndef CONFIG_PIN_TLB_TEXT
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-			patch_branch(&itlb_miss_exit_2, target, 0);
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-#endif
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+			patch_branch_site(&patch__itlbmiss_exit_1, target, 0);
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 		}
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 		val = itlb_miss_counter;
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 		break;
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 	case PERF_8xx_ID_DTLB_LOAD_MISS:
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 		if (atomic_inc_return(&dtlb_miss_ref) == 1) {
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-			unsigned long target = (unsigned long)&dtlb_miss_perf;
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+			unsigned long target = patch_site_addr(&patch__dtlbmiss_perf);
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-			patch_branch(&dtlb_miss_exit_1, target, 0);
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-			patch_branch(&dtlb_miss_exit_2, target, 0);
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-			patch_branch(&dtlb_miss_exit_3, target, 0);
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+			patch_branch_site(&patch__dtlbmiss_exit_1, target, 0);
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 		}
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 		val = dtlb_miss_counter;
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 		break;
..
..
@@ -164,10 +153,6 @@
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153
 
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 static void mpc8xx_pmu_del(struct perf_event *event, int flags)
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 {
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-	/* mfspr r10, SPRN_SPRG_SCRATCH0 */
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-	unsigned int insn = PPC_INST_MFSPR | __PPC_RS(R10) |
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-			    __PPC_SPR(SPRN_SPRG_SCRATCH0);
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-
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 	mpc8xx_pmu_read(event);
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 	/* If it was the last user, stop counting to avoid useles overhead */
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@@ -180,17 +165,20 @@
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 		break;
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 	case PERF_8xx_ID_ITLB_LOAD_MISS:
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 		if (atomic_dec_return(&itlb_miss_ref) == 0) {
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-			patch_instruction(&itlb_miss_exit_1, insn);
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-#ifndef CONFIG_PIN_TLB_TEXT
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-			patch_instruction(&itlb_miss_exit_2, insn);
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-#endif
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+			/* mfspr r10, SPRN_SPRG_SCRATCH0 */
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+			struct ppc_inst insn = ppc_inst(PPC_INST_MFSPR | __PPC_RS(R10) |
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+					    __PPC_SPR(SPRN_SPRG_SCRATCH0));
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+
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+			patch_instruction_site(&patch__itlbmiss_exit_1, insn);
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 		}
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 		break;
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 	case PERF_8xx_ID_DTLB_LOAD_MISS:
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 		if (atomic_dec_return(&dtlb_miss_ref) == 0) {
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-			patch_instruction(&dtlb_miss_exit_1, insn);
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-			patch_instruction(&dtlb_miss_exit_2, insn);
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-			patch_instruction(&dtlb_miss_exit_3, insn);
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+			/* mfspr r10, SPRN_DAR */
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+			struct ppc_inst insn = ppc_inst(PPC_INST_MFSPR | __PPC_RS(R10) |
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+					    __PPC_SPR(SPRN_DAR));
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+
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+			patch_instruction_site(&patch__dtlbmiss_exit_1, insn);
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 		}
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 		break;
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 	}