mk-rootfs.sh

hc

2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376

 kernel/arch/mips/mm/c-r3k.c
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@@ -16,7 +16,6 @@
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 #include <linux/mm.h>
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 #include <asm/page.h>
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-#include <asm/pgtable.h>
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 #include <asm/mmu_context.h>
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 #include <asm/isadep.h>
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 #include <asm/io.h>
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@@ -240,8 +239,6 @@
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 	unsigned long kaddr = KSEG0ADDR(pfn << PAGE_SHIFT);
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 	int exec = vma->vm_flags & VM_EXEC;
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 	struct mm_struct *mm = vma->vm_mm;
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-	pgd_t *pgdp;
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-	pud_t *pudp;
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 	pmd_t *pmdp;
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 	pte_t *ptep;
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@@ -252,10 +249,8 @@
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 	if (cpu_context(smp_processor_id(), mm) == 0)
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 		return;
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-	pgdp = pgd_offset(mm, addr);
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-	pudp = pud_offset(pgdp, addr);
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-	pmdp = pmd_offset(pudp, addr);
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-	ptep = pte_offset(pmdp, addr);
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+	pmdp = pmd_off(mm, addr);
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+	ptep = pte_offset_kernel(pmdp, addr);
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 	/* Invalid => no such page in the cache.  */
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 	if (!(pte_val(*ptep) & _PAGE_PRESENT))
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@@ -272,30 +267,6 @@
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 static void r3k_flush_data_cache_page(unsigned long addr)
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 {
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-}
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-
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-static void r3k_flush_cache_sigtramp(unsigned long addr)
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-{
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-	unsigned long flags;
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-
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-	pr_debug("csigtramp[%08lx]\n", addr);
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-
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-	flags = read_c0_status();
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-
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-	write_c0_status(flags&~ST0_IEC);
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-
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-	/* Fill the TLB to avoid an exception with caches isolated. */
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-	asm(	"lw\t$0, 0x000(%0)\n\t"
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-		"lw\t$0, 0x004(%0)\n\t"
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-		: : "r" (addr) );
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-
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-	write_c0_status((ST0_ISC|ST0_SWC|flags)&~ST0_IEC);
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-
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-	asm(	"sb\t$0, 0x000(%0)\n\t"
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-		"sb\t$0, 0x004(%0)\n\t"
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-		: : "r" (addr) );
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-
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-	write_c0_status(flags);
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 }
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 static void r3k_flush_kernel_vmap_range(unsigned long vaddr, int size)
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@@ -331,7 +302,6 @@
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 	__flush_kernel_vmap_range = r3k_flush_kernel_vmap_range;
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-	flush_cache_sigtramp = r3k_flush_cache_sigtramp;
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 	local_flush_data_cache_page = local_r3k_flush_data_cache_page;
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 	flush_data_cache_page = r3k_flush_data_cache_page;
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@@ -339,9 +309,9 @@
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 	_dma_cache_wback = r3k_dma_cache_wback_inv;
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 	_dma_cache_inv = r3k_dma_cache_wback_inv;
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-	printk("Primary instruction cache %ldkB, linesize %ld bytes.\n",
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+	pr_info("Primary instruction cache %ldkB, linesize %ld bytes.\n",
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 		icache_size >> 10, icache_lsize);
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-	printk("Primary data cache %ldkB, linesize %ld bytes.\n",
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+	pr_info("Primary data cache %ldkB, linesize %ld bytes.\n",
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 		dcache_size >> 10, dcache_lsize);
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 	build_clear_page();