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hc

2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376

 kernel/arch/mips/include/asm/llsc.h
..
..
@@ -9,20 +9,31 @@
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 #ifndef __ASM_LLSC_H
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 #define __ASM_LLSC_H
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+#include <asm/isa-rev.h>
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+
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 #if _MIPS_SZLONG == 32
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-#define SZLONG_LOG 5
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-#define SZLONG_MASK 31UL
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 #define __LL		"ll	"
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 #define __SC		"sc	"
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 #define __INS		"ins	"
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 #define __EXT		"ext	"
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 #elif _MIPS_SZLONG == 64
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-#define SZLONG_LOG 6
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-#define SZLONG_MASK 63UL
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 #define __LL		"lld	"
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 #define __SC		"scd	"
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 #define __INS		"dins	"
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 #define __EXT		"dext	"
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 #endif
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+/*
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+ * Using a branch-likely instruction to check the result of an sc instruction
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+ * works around a bug present in R10000 CPUs prior to revision 3.0 that could
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+ * cause ll-sc sequences to execute non-atomically.
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+ */
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+#ifdef CONFIG_WAR_R10000_LLSC
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+# define __SC_BEQZ "beqzl	"
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+#elif MIPS_ISA_REV >= 6
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+# define __SC_BEQZ "beqzc	"
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+#else
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+# define __SC_BEQZ "beqz	"
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+#endif
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+
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 #endif /* __ASM_LLSC_H  */