mk-rootfs.sh

hc

2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376

 kernel/arch/mips/include/asm/futex.h
..
..
@@ -16,26 +16,27 @@
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 #include <asm/barrier.h>
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 #include <asm/compiler.h>
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 #include <asm/errno.h>
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+#include <asm/sync.h>
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 #include <asm/war.h>
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 #define __futex_atomic_op(insn, ret, oldval, uaddr, oparg)		\
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 {									\
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-	if (cpu_has_llsc && R10000_LLSC_WAR) {				\
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+	if (cpu_has_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) {	\
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 		__asm__ __volatile__(					\
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 		"	.set	push				\n"	\
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 		"	.set	noat				\n"	\
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+		"	.set	push				\n"	\
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 		"	.set	arch=r4000			\n"	\
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 		"1:	ll	%1, %4	# __futex_atomic_op	\n"	\
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-		"	.set	mips0				\n"	\
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+		"	.set	pop				\n"	\
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 		"	" insn	"				\n"	\
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 		"	.set	arch=r4000			\n"	\
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 		"2:	sc	$1, %2				\n"	\
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 		"	beqzl	$1, 1b				\n"	\
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-		__WEAK_LLSC_MB						\
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+		__stringify(__WEAK_LLSC_MB) "			\n"	\
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 		"3:						\n"	\
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 		"	.insn					\n"	\
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 		"	.set	pop				\n"	\
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-		"	.set	mips0				\n"	\
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 		"	.section .fixup,\"ax\"			\n"	\
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 		"4:	li	%0, %6				\n"	\
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 		"	j	3b				\n"	\
..
..
@@ -53,18 +54,19 @@
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 		__asm__ __volatile__(					\
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 		"	.set	push				\n"	\
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 		"	.set	noat				\n"	\
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+		"	.set	push				\n"	\
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 		"	.set	"MIPS_ISA_ARCH_LEVEL"		\n"	\
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+		"	" __SYNC(full, loongson3_war) "		\n"	\
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 		"1:	"user_ll("%1", "%4")" # __futex_atomic_op\n"	\
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-		"	.set	mips0				\n"	\
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+		"	.set	pop				\n"	\
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 		"	" insn	"				\n"	\
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 		"	.set	"MIPS_ISA_ARCH_LEVEL"		\n"	\
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 		"2:	"user_sc("$1", "%2")"			\n"	\
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 		"	beqz	$1, 1b				\n"	\
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-		__WEAK_LLSC_MB						\
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+		__stringify(__WEAK_LLSC_MB) "			\n"	\
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 		"3:						\n"	\
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 		"	.insn					\n"	\
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 		"	.set	pop				\n"	\
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-		"	.set	mips0				\n"	\
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 		"	.section .fixup,\"ax\"			\n"	\
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 		"4:	li	%0, %6				\n"	\
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 		"	j	3b				\n"	\
..
..
@@ -87,7 +89,8 @@
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 {
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 	int oldval = 0, ret;
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-	pagefault_disable();
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+	if (!access_ok(uaddr, sizeof(u32)))
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+		return -EFAULT;
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 	switch (op) {
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 	case FUTEX_OP_SET:
..
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@@ -114,8 +117,6 @@
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 		ret = -ENOSYS;
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 	}
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-	pagefault_enable();
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-
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 	if (!ret)
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 		*oval = oldval;
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..
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@@ -129,23 +130,24 @@
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 	int ret = 0;
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 	u32 val;
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-	if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
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+	if (!access_ok(uaddr, sizeof(u32)))
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 		return -EFAULT;
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-	if (cpu_has_llsc && R10000_LLSC_WAR) {
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+	if (cpu_has_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) {
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 		__asm__ __volatile__(
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 		"# futex_atomic_cmpxchg_inatomic			\n"
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 		"	.set	push					\n"
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 		"	.set	noat					\n"
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+		"	.set	push					\n"
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 		"	.set	arch=r4000				\n"
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 		"1:	ll	%1, %3					\n"
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 		"	bne	%1, %z4, 3f				\n"
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-		"	.set	mips0					\n"
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+		"	.set	pop					\n"
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 		"	move	$1, %z5					\n"
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 		"	.set	arch=r4000				\n"
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 		"2:	sc	$1, %2					\n"
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 		"	beqzl	$1, 1b					\n"
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-		__WEAK_LLSC_MB
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+		__stringify(__WEAK_LLSC_MB) "				\n"
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 		"3:							\n"
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 		"	.insn						\n"
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 		"	.set	pop					\n"
..
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@@ -166,16 +168,17 @@
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 		"# futex_atomic_cmpxchg_inatomic			\n"
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 		"	.set	push					\n"
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 		"	.set	noat					\n"
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+		"	.set	push					\n"
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 		"	.set	"MIPS_ISA_ARCH_LEVEL"			\n"
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+		"	" __SYNC(full, loongson3_war) "			\n"
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 		"1:	"user_ll("%1", "%3")"				\n"
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 		"	bne	%1, %z4, 3f				\n"
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-		"	.set	mips0					\n"
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+		"	.set	pop					\n"
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 		"	move	$1, %z5					\n"
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 		"	.set	"MIPS_ISA_ARCH_LEVEL"			\n"
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 		"2:	"user_sc("$1", "%2")"				\n"
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 		"	beqz	$1, 1b					\n"
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-		__WEAK_LLSC_MB
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-		"3:							\n"
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+		"3:	" __SYNC_ELSE(full, loongson3_war, __WEAK_LLSC_MB) "\n"
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 		"	.insn						\n"
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 		"	.set	pop					\n"
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 		"	.section .fixup,\"ax\"				\n"