| .. | .. | 
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|  | 1 | +/* SPDX-License-Identifier: GPL-2.0-or-later */ | 
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| 1 | 2 | /* | 
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| 2 | 3 | * Copyright (C) 2002 MontaVista Software Inc. | 
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| 3 | 4 | * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net | 
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| 4 |  | - * | 
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| 5 |  | - * This program is free software; you can redistribute it and/or modify it | 
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| 6 |  | - * under the terms of the GNU General Public License as published by the | 
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| 7 |  | - * Free Software Foundation;  either version 2 of the  License, or (at your | 
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| 8 |  | - * option) any later version. | 
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| 9 | 5 | */ | 
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| 10 | 6 | #ifndef _ASM_FPU_H | 
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| 11 | 7 | #define _ASM_FPU_H | 
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| .. | .. | 
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| 30 | 26 | #include <asm/mips_mt.h> | 
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| 31 | 27 | #endif | 
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| 32 | 28 |  | 
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| 33 |  | -struct sigcontext; | 
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| 34 |  | -struct sigcontext32; | 
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| 35 |  | - | 
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| 36 |  | -extern void _init_fpu(unsigned int); | 
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| 37 |  | -extern void _save_fp(struct task_struct *); | 
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| 38 |  | -extern void _restore_fp(struct task_struct *); | 
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| 39 |  | - | 
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| 40 | 29 | /* | 
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| 41 | 30 | * This enum specifies a mode in which we want the FPU to operate, for cores | 
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| 42 | 31 | * which implement the Status.FR bit. Note that the bottom bit of the value | 
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| .. | .. | 
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| 50 | 39 |  | 
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| 51 | 40 | #define FPU_FR_MASK		0x1 | 
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| 52 | 41 | }; | 
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|  | 42 | + | 
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|  | 43 | +#ifdef CONFIG_MIPS_FP_SUPPORT | 
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|  | 44 | + | 
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|  | 45 | +extern void _save_fp(struct task_struct *); | 
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|  | 46 | +extern void _restore_fp(struct task_struct *); | 
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| 53 | 47 |  | 
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| 54 | 48 | #define __disable_fpu()							\ | 
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| 55 | 49 | do {									\ | 
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| .. | .. | 
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| 77 | 71 | goto fr_common; | 
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| 78 | 72 |  | 
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| 79 | 73 | case FPU_64BIT: | 
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| 80 |  | -#if !(defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) \ | 
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| 81 |  | -      || defined(CONFIG_64BIT)) | 
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|  | 74 | +#if !(defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \ | 
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|  | 75 | +      defined(CONFIG_CPU_MIPSR6) || defined(CONFIG_64BIT)) | 
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| 82 | 76 | /* we only have a 32-bit FPU */ | 
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| 83 | 77 | return SIGFPE; | 
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| 84 | 78 | #endif | 
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| 85 |  | -		/* fall through */ | 
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|  | 79 | +		fallthrough; | 
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| 86 | 80 | case FPU_32BIT: | 
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| 87 | 81 | if (cpu_has_fre) { | 
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| 88 | 82 | /* clear FRE */ | 
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| .. | .. | 
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| 198 | 192 | preempt_enable(); | 
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| 199 | 193 | } | 
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| 200 | 194 |  | 
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| 201 |  | -static inline int init_fpu(void) | 
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|  | 195 | +/** | 
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|  | 196 | + * init_fp_ctx() - Initialize task FP context | 
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|  | 197 | + * @target: The task whose FP context should be initialized. | 
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|  | 198 | + * | 
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|  | 199 | + * Initializes the FP context of the target task to sane default values if that | 
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|  | 200 | + * target task does not already have valid FP context. Once the context has | 
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|  | 201 | + * been initialized, the task will be marked as having used FP & thus having | 
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|  | 202 | + * valid FP context. | 
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|  | 203 | + * | 
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|  | 204 | + * Returns: true if context is initialized, else false. | 
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|  | 205 | + */ | 
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|  | 206 | +static inline bool init_fp_ctx(struct task_struct *target) | 
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| 202 | 207 | { | 
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| 203 |  | -	unsigned int fcr31 = current->thread.fpu.fcr31; | 
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| 204 |  | -	int ret = 0; | 
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|  | 208 | +	/* If FP has been used then the target already has context */ | 
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|  | 209 | +	if (tsk_used_math(target)) | 
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|  | 210 | +		return false; | 
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| 205 | 211 |  | 
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| 206 |  | -	if (cpu_has_fpu) { | 
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| 207 |  | -		unsigned int config5; | 
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|  | 212 | +	/* Begin with data registers set to all 1s... */ | 
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|  | 213 | +	memset(&target->thread.fpu.fpr, ~0, sizeof(target->thread.fpu.fpr)); | 
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| 208 | 214 |  | 
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| 209 |  | -		ret = __own_fpu(); | 
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| 210 |  | -		if (ret) | 
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| 211 |  | -			return ret; | 
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|  | 215 | +	/* FCSR has been preset by `mips_set_personality_nan'.  */ | 
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| 212 | 216 |  | 
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| 213 |  | -		if (!cpu_has_fre) { | 
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| 214 |  | -			_init_fpu(fcr31); | 
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|  | 217 | +	/* | 
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|  | 218 | +	 * Record that the target has "used" math, such that the context | 
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|  | 219 | +	 * just initialised, and any modifications made by the caller, | 
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|  | 220 | +	 * aren't discarded. | 
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|  | 221 | +	 */ | 
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|  | 222 | +	set_stopped_child_used_math(target); | 
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| 215 | 223 |  | 
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| 216 |  | -			return 0; | 
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| 217 |  | -		} | 
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| 218 |  | - | 
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| 219 |  | -		/* | 
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| 220 |  | -		 * Ensure FRE is clear whilst running _init_fpu, since | 
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| 221 |  | -		 * single precision FP instructions are used. If FRE | 
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| 222 |  | -		 * was set then we'll just end up initialising all 32 | 
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| 223 |  | -		 * 64b registers. | 
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| 224 |  | -		 */ | 
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| 225 |  | -		config5 = clear_c0_config5(MIPS_CONF5_FRE); | 
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| 226 |  | -		enable_fpu_hazard(); | 
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| 227 |  | - | 
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| 228 |  | -		_init_fpu(fcr31); | 
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| 229 |  | - | 
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| 230 |  | -		/* Restore FRE */ | 
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| 231 |  | -		write_c0_config5(config5); | 
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| 232 |  | -		enable_fpu_hazard(); | 
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| 233 |  | -	} else | 
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| 234 |  | -		fpu_emulator_init_fpu(); | 
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| 235 |  | - | 
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| 236 |  | -	return ret; | 
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|  | 224 | +	return true; | 
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| 237 | 225 | } | 
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| 238 | 226 |  | 
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| 239 | 227 | static inline void save_fp(struct task_struct *tsk) | 
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| .. | .. | 
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| 260 | 248 | return tsk->thread.fpu.fpr; | 
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| 261 | 249 | } | 
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| 262 | 250 |  | 
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|  | 251 | +#else /* !CONFIG_MIPS_FP_SUPPORT */ | 
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|  | 252 | + | 
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|  | 253 | +/* | 
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|  | 254 | + * When FP support is disabled we provide only a minimal set of stub functions | 
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|  | 255 | + * to avoid callers needing to care too much about CONFIG_MIPS_FP_SUPPORT. | 
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|  | 256 | + */ | 
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|  | 257 | + | 
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|  | 258 | +static inline int __enable_fpu(enum fpu_mode mode) | 
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|  | 259 | +{ | 
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|  | 260 | +	return SIGILL; | 
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|  | 261 | +} | 
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|  | 262 | + | 
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|  | 263 | +static inline void __disable_fpu(void) | 
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|  | 264 | +{ | 
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|  | 265 | +	/* no-op */ | 
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|  | 266 | +} | 
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|  | 267 | + | 
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|  | 268 | + | 
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|  | 269 | +static inline int is_fpu_owner(void) | 
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|  | 270 | +{ | 
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|  | 271 | +	return 0; | 
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|  | 272 | +} | 
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|  | 273 | + | 
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|  | 274 | +static inline void clear_fpu_owner(void) | 
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|  | 275 | +{ | 
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|  | 276 | +	/* no-op */ | 
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|  | 277 | +} | 
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|  | 278 | + | 
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|  | 279 | +static inline int own_fpu_inatomic(int restore) | 
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|  | 280 | +{ | 
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|  | 281 | +	return SIGILL; | 
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|  | 282 | +} | 
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|  | 283 | + | 
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|  | 284 | +static inline int own_fpu(int restore) | 
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|  | 285 | +{ | 
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|  | 286 | +	return SIGILL; | 
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|  | 287 | +} | 
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|  | 288 | + | 
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|  | 289 | +static inline void lose_fpu_inatomic(int save, struct task_struct *tsk) | 
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|  | 290 | +{ | 
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|  | 291 | +	/* no-op */ | 
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|  | 292 | +} | 
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|  | 293 | + | 
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|  | 294 | +static inline void lose_fpu(int save) | 
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|  | 295 | +{ | 
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|  | 296 | +	/* no-op */ | 
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|  | 297 | +} | 
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|  | 298 | + | 
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|  | 299 | +static inline bool init_fp_ctx(struct task_struct *target) | 
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|  | 300 | +{ | 
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|  | 301 | +	return false; | 
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|  | 302 | +} | 
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|  | 303 | + | 
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|  | 304 | +/* | 
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|  | 305 | + * The following functions should only be called in paths where we know that FP | 
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|  | 306 | + * support is enabled, typically a path where own_fpu() or __enable_fpu() have | 
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|  | 307 | + * returned successfully. When CONFIG_MIPS_FP_SUPPORT=n it is known at compile | 
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|  | 308 | + * time that this should never happen, so calls to these functions should be | 
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|  | 309 | + * optimized away & never actually be emitted. | 
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|  | 310 | + */ | 
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|  | 311 | + | 
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|  | 312 | +extern void save_fp(struct task_struct *tsk) | 
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|  | 313 | +	__compiletime_error("save_fp() should not be called when CONFIG_MIPS_FP_SUPPORT=n"); | 
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|  | 314 | + | 
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|  | 315 | +extern void _save_fp(struct task_struct *) | 
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|  | 316 | +	__compiletime_error("_save_fp() should not be called when CONFIG_MIPS_FP_SUPPORT=n"); | 
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|  | 317 | + | 
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|  | 318 | +extern void restore_fp(struct task_struct *tsk) | 
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|  | 319 | +	__compiletime_error("restore_fp() should not be called when CONFIG_MIPS_FP_SUPPORT=n"); | 
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|  | 320 | + | 
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|  | 321 | +extern void _restore_fp(struct task_struct *) | 
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|  | 322 | +	__compiletime_error("_restore_fp() should not be called when CONFIG_MIPS_FP_SUPPORT=n"); | 
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|  | 323 | + | 
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|  | 324 | +extern union fpureg *get_fpu_regs(struct task_struct *tsk) | 
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|  | 325 | +	__compiletime_error("get_fpu_regs() should not be called when CONFIG_MIPS_FP_SUPPORT=n"); | 
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|  | 326 | + | 
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|  | 327 | +#endif /* !CONFIG_MIPS_FP_SUPPORT */ | 
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| 263 | 328 | #endif /* _ASM_FPU_H */ | 
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