mk-rootfs.sh

hc

2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376

 kernel/arch/arm64/lib/Makefile
..
..
@@ -1,32 +1,20 @@
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 # SPDX-License-Identifier: GPL-2.0
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 lib-y		:= clear_user.o delay.o copy_from_user.o		\
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 		   copy_to_user.o copy_in_user.o copy_page.o		\
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-		   clear_page.o memchr.o memcpy.o memmove.o memset.o	\
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-		   memcmp.o strcmp.o strncmp.o strlen.o strnlen.o	\
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-		   strchr.o strrchr.o tishift.o
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+		   clear_page.o csum.o memchr.o memcpy.o memmove.o	\
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+		   memset.o memcmp.o strcmp.o strncmp.o strlen.o	\
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+		   strnlen.o strchr.o strrchr.o tishift.o
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-# Tell the compiler to treat all general purpose registers (with the
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-# exception of the IP registers, which are already handled by the caller
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-# in case of a PLT) as callee-saved, which allows for efficient runtime
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-# patching of the bl instruction in the caller with an atomic instruction
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-# when supported by the CPU. Result and argument registers are handled
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-# correctly, based on the function prototype.
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-ifeq ($(CONFIG_LD_IS_LLD), y)
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-# https://bugs.llvm.org/show_bug.cgi?id=35841
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-obj-$(CONFIG_ARM64_LSE_ATOMICS) += atomic_ll_sc.o
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-else
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-lib-$(CONFIG_ARM64_LSE_ATOMICS) += atomic_ll_sc.o
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+ifeq ($(CONFIG_KERNEL_MODE_NEON), y)
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+obj-$(CONFIG_XOR_BLOCKS)	+= xor-neon.o
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+CFLAGS_REMOVE_xor-neon.o	+= -mgeneral-regs-only
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+CFLAGS_xor-neon.o		+= -ffreestanding
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 endif
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-CFLAGS_atomic_ll_sc.o	:= -ffixed-x1 -ffixed-x2        		\
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-		   -ffixed-x3 -ffixed-x4 -ffixed-x5 -ffixed-x6		\
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-		   -ffixed-x7 -fcall-saved-x8 -fcall-saved-x9		\
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-		   -fcall-saved-x10 -fcall-saved-x11 -fcall-saved-x12	\
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-		   -fcall-saved-x13 -fcall-saved-x14 -fcall-saved-x15	\
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-		   -fcall-saved-x18 -fomit-frame-pointer
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-CFLAGS_REMOVE_atomic_ll_sc.o := -pg
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-GCOV_PROFILE_atomic_ll_sc.o	:= n
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-KASAN_SANITIZE_atomic_ll_sc.o	:= n
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-KCOV_INSTRUMENT_atomic_ll_sc.o	:= n
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-UBSAN_SANITIZE_atomic_ll_sc.o	:= n
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 lib-$(CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE) += uaccess_flushcache.o
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+
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+obj-$(CONFIG_CRC32) += crc32.o
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+
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+obj-$(CONFIG_FUNCTION_ERROR_INJECTION) += error-inject.o
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+
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+obj-$(CONFIG_ARM64_MTE) += mte.o