~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,3 +1,4 @@
	1	+# SPDX-License-Identifier: GPL-2.0-only
1	2	config ARM64
2	3	def_bool y
3	4	select ACPI_CCA_REQUIRED if ACPI
..	..	@@ -5,66 +6,84 @@
5	6	select ACPI_GTDT if ACPI
6	7	select ACPI_IORT if ACPI
7	8	select ACPI_REDUCED_HARDWARE_ONLY if ACPI
8		- select ACPI_MCFG if ACPI
	9	+ select ACPI_MCFG if (ACPI && PCI)
9	10	select ACPI_SPCR_TABLE if ACPI
10	11	select ACPI_PPTT if ACPI
11		- select ARCH_CLOCKSOURCE_DATA
	12	+ select ARCH_HAS_DEBUG_WX
	13	+ select ARCH_BINFMT_ELF_STATE
12	14	select ARCH_HAS_DEBUG_VIRTUAL
	15	+ select ARCH_HAS_DEBUG_VM_PGTABLE
13	16	select ARCH_HAS_DEVMEM_IS_ALLOWED
	17	+ select ARCH_HAS_DMA_PREP_COHERENT
14	18	select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
15		- select ARCH_HAS_ELF_RANDOMIZE
16	19	select ARCH_HAS_FAST_MULTIPLIER
17	20	select ARCH_HAS_FORTIFY_SOURCE
18	21	select ARCH_HAS_GCOV_PROFILE_ALL
19		- select ARCH_HAS_GIGANTIC_PAGE if (MEMORY_ISOLATION && COMPACTION) \|\| CMA
	22	+ select ARCH_HAS_GIGANTIC_PAGE
20	23	select ARCH_HAS_KCOV
	24	+ select ARCH_HAS_KEEPINITRD
21	25	select ARCH_HAS_MEMBARRIER_SYNC_CORE
	26	+ select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
	27	+ select ARCH_HAS_PTE_DEVMAP
22	28	select ARCH_HAS_PTE_SPECIAL
	29	+ select ARCH_HAS_SETUP_DMA_OPS
	30	+ select ARCH_HAS_SET_DIRECT_MAP
23	31	select ARCH_HAS_SET_MEMORY
24		- select ARCH_HAS_SG_CHAIN
	32	+ select ARCH_STACKWALK
25	33	select ARCH_HAS_STRICT_KERNEL_RWX
26	34	select ARCH_HAS_STRICT_MODULE_RWX
	35	+ select ARCH_HAS_SYNC_DMA_FOR_DEVICE
	36	+ select ARCH_HAS_SYNC_DMA_FOR_CPU
27	37	select ARCH_HAS_SYSCALL_WRAPPER
	38	+ select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
28	39	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
	40	+ select ARCH_HAVE_ELF_PROT
29	41	select ARCH_HAVE_NMI_SAFE_CMPXCHG
30		- select ARCH_INLINE_READ_LOCK if !PREEMPT
31		- select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
32		- select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
33		- select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
34		- select ARCH_INLINE_READ_UNLOCK if !PREEMPT
35		- select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
36		- select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
37		- select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
38		- select ARCH_INLINE_WRITE_LOCK if !PREEMPT
39		- select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
40		- select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
41		- select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
42		- select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
43		- select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
44		- select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
45		- select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
46		- select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPT
47		- select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPT
48		- select ARCH_INLINE_SPIN_LOCK if !PREEMPT
49		- select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPT
50		- select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPT
51		- select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPT
52		- select ARCH_INLINE_SPIN_UNLOCK if !PREEMPT
53		- select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPT
54		- select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPT
55		- select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPT
	42	+ select ARCH_INLINE_READ_LOCK if !PREEMPTION
	43	+ select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
	44	+ select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
	45	+ select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
	46	+ select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
	47	+ select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
	48	+ select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
	49	+ select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
	50	+ select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
	51	+ select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
	52	+ select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
	53	+ select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
	54	+ select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
	55	+ select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
	56	+ select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
	57	+ select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
	58	+ select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
	59	+ select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
	60	+ select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
	61	+ select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
	62	+ select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
	63	+ select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
	64	+ select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
	65	+ select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
	66	+ select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
	67	+ select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
	68	+ select ARCH_KEEP_MEMBLOCK
56	69	select ARCH_USE_CMPXCHG_LOCKREF
	70	+ select ARCH_USE_GNU_PROPERTY
57	71	select ARCH_USE_QUEUED_RWLOCKS
58	72	select ARCH_USE_QUEUED_SPINLOCKS
	73	+ select ARCH_USE_SYM_ANNOTATIONS
59	74	select ARCH_SUPPORTS_MEMORY_FAILURE
60		- select ARCH_SUPPORTS_LTO_CLANG
61		- select ARCH_SUPPORTS_THINLTO
62	75	select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
	76	+ select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
	77	+ select ARCH_SUPPORTS_LTO_CLANG_THIN
63	78	select ARCH_SUPPORTS_ATOMIC_RMW
64		- select ARCH_SUPPORTS_INT128 if GCC_VERSION >= 50000 \|\| CC_IS_CLANG
	79	+ select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 && (GCC_VERSION >= 50000 \|\| CC_IS_CLANG)
65	80	select ARCH_SUPPORTS_NUMA_BALANCING
66		- select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
	81	+ select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
	82	+ select ARCH_WANT_DEFAULT_BPF_JIT
	83	+ select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
67	84	select ARCH_WANT_FRAME_POINTERS
	85	+ select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES \|\| (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
	86	+ select ARCH_WANT_LD_ORPHAN_WARN
68	87	select ARCH_HAS_UBSAN_SANITIZE_ALL
69	88	select ARM_AMBA
70	89	select ARM_ARCH_TIMER
..	..	@@ -74,12 +93,13 @@
74	93	select ARM_GIC_V3
75	94	select ARM_GIC_V3_ITS if PCI
76	95	select ARM_PSCI_FW
77		- select BUILDTIME_EXTABLE_SORT
	96	+ select BUILDTIME_TABLE_SORT
78	97	select CLONE_BACKWARDS
79	98	select COMMON_CLK
80	99	select CPU_PM if (SUSPEND \|\| CPU_IDLE)
	100	+ select CRC32
81	101	select DCACHE_WORD_ACCESS
82		- select DMA_DIRECT_OPS
	102	+ select DMA_DIRECT_REMAP
83	103	select EDAC_SUPPORT
84	104	select FRAME_POINTER
85	105	select GENERIC_ALLOCATOR
..	..	@@ -90,31 +110,43 @@
90	110	select GENERIC_CPU_VULNERABILITIES
91	111	select GENERIC_EARLY_IOREMAP
92	112	select GENERIC_IDLE_POLL_SETUP
	113	+ select GENERIC_IRQ_IPI
	114	+ select ARCH_WANTS_IRQ_RAW
93	115	select GENERIC_IRQ_MULTI_HANDLER
94	116	select GENERIC_IRQ_PROBE
95	117	select GENERIC_IRQ_SHOW
96	118	select GENERIC_IRQ_SHOW_LEVEL
97	119	select GENERIC_PCI_IOMAP
	120	+ select GENERIC_PTDUMP
98	121	select GENERIC_SCHED_CLOCK
99	122	select GENERIC_SMP_IDLE_THREAD
100	123	select GENERIC_STRNCPY_FROM_USER
101	124	select GENERIC_STRNLEN_USER
102	125	select GENERIC_TIME_VSYSCALL
103	126	select GENERIC_GETTIMEOFDAY
	127	+ select GENERIC_VDSO_TIME_NS
104	128	select HANDLE_DOMAIN_IRQ
105	129	select HARDIRQS_SW_RESEND
	130	+ select HAVE_MOVE_PMD
	131	+ select HAVE_MOVE_PUD
	132	+ select HAVE_PCI
106	133	select HAVE_ACPI_APEI if (ACPI && EFI)
107	134	select HAVE_ALIGNED_STRUCT_PAGE if SLUB
108	135	select HAVE_ARCH_AUDITSYSCALL
109	136	select HAVE_ARCH_BITREVERSE
	137	+ select HAVE_ARCH_COMPILER_H
110	138	select HAVE_ARCH_HUGE_VMAP
111	139	select HAVE_ARCH_JUMP_LABEL
	140	+ select HAVE_ARCH_JUMP_LABEL_RELATIVE
112	141	select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
	142	+ select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
113	143	select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
	144	+ select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
	145	+ select HAVE_ARCH_KFENCE
114	146	select HAVE_ARCH_KGDB
115	147	select HAVE_ARCH_MMAP_RND_BITS
116	148	select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
117		- select HAVE_ARCH_PREL32_RELOCATIONS if !LTO_CLANG
	149	+ select HAVE_ARCH_PREL32_RELOCATIONS
118	150	select HAVE_ARCH_SECCOMP_FILTER
119	151	select HAVE_ARCH_STACKLEAK
120	152	select HAVE_ARCH_THREAD_STRUCT_WHITELIST
..	..	@@ -122,6 +154,7 @@
122	154	select HAVE_ARCH_TRANSPARENT_HUGEPAGE
123	155	select HAVE_ARCH_VMAP_STACK
124	156	select HAVE_ARM_SMCCC
	157	+ select HAVE_ASM_MODVERSIONS
125	158	select HAVE_EBPF_JIT
126	159	select HAVE_C_RECORDMCOUNT
127	160	select HAVE_CMPXCHG_DOUBLE
..	..	@@ -131,25 +164,28 @@
131	164	select HAVE_DEBUG_KMEMLEAK
132	165	select HAVE_DMA_CONTIGUOUS
133	166	select HAVE_DYNAMIC_FTRACE
	167	+ select HAVE_DYNAMIC_FTRACE_WITH_REGS \
	168	+ if $(cc-option,-fpatchable-function-entry=2)
	169	+ select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
	170	+ if DYNAMIC_FTRACE_WITH_REGS
134	171	select HAVE_EFFICIENT_UNALIGNED_ACCESS
	172	+ select HAVE_FAST_GUP
135	173	select HAVE_FTRACE_MCOUNT_RECORD
136	174	select HAVE_FUNCTION_TRACER
137		- select HAVE_FUNCTION_GRAPH_TRACER if !SHADOW_CALL_STACK
	175	+ select HAVE_FUNCTION_ERROR_INJECTION
	176	+ select HAVE_FUNCTION_GRAPH_TRACER
138	177	select HAVE_GCC_PLUGINS
139		- select HAVE_GENERIC_DMA_COHERENT
140	178	select HAVE_HW_BREAKPOINT if PERF_EVENTS
141	179	select HAVE_IRQ_TIME_ACCOUNTING
142		- select HAVE_KERNEL_GZIP
143		- select HAVE_KERNEL_LZ4
144		- select HAVE_MEMBLOCK
145		- select HAVE_MEMBLOCK_NODE_MAP if NUMA
146	180	select HAVE_NMI
147	181	select HAVE_PATA_PLATFORM
148	182	select HAVE_PERF_EVENTS
149	183	select HAVE_PERF_REGS
150	184	select HAVE_PERF_USER_STACK_DUMP
151	185	select HAVE_REGS_AND_STACK_ACCESS_API
152		- select HAVE_RCU_TABLE_FREE
	186	+ select HAVE_FUNCTION_ARG_ACCESS_API
	187	+ select HAVE_FUTEX_CMPXCHG if FUTEX
	188	+ select MMU_GATHER_RCU_TABLE_FREE
153	189	select HAVE_RSEQ
154	190	select HAVE_STACKPROTECTOR
155	191	select HAVE_SYSCALL_TRACEPOINTS
..	..	@@ -159,22 +195,24 @@
159	195	select IOMMU_DMA if IOMMU_SUPPORT
160	196	select IRQ_DOMAIN
161	197	select IRQ_FORCED_THREADING
	198	+ select KASAN_VMALLOC if KASAN_GENERIC
162	199	select MODULES_USE_ELF_RELA
163		- select MULTI_IRQ_HANDLER
164	200	select NEED_DMA_MAP_STATE
165	201	select NEED_SG_DMA_LENGTH
166		- select NO_BOOTMEM
167	202	select OF
168	203	select OF_EARLY_FLATTREE
169		- select OF_RESERVED_MEM
170		- select PCI_ECAM if ACPI
	204	+ select PCI_DOMAINS_GENERIC if PCI
	205	+ select PCI_ECAM if (ACPI && PCI)
	206	+ select PCI_SYSCALL if PCI
171	207	select POWER_RESET
172	208	select POWER_SUPPLY
173		- select REFCOUNT_FULL
	209	+ select SET_FS
174	210	select SPARSE_IRQ
175	211	select SWIOTLB
176	212	select SYSCTL_EXCEPTION_TRACE
177	213	select THREAD_INFO_IN_TASK
	214	+ select ARCH_SUPPORTS_SPECULATIVE_PAGE_FAULT
	215	+ select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
178	216	help
179	217	ARM 64-bit (AArch64) Linux support.
180	218
..	..	@@ -190,10 +228,16 @@
190	228	default 14 if ARM64_16K_PAGES
191	229	default 12
192	230
193		-config ARM64_CONT_SHIFT
	231	+config ARM64_CONT_PTE_SHIFT
194	232	int
195	233	default 5 if ARM64_64K_PAGES
196	234	default 7 if ARM64_16K_PAGES
	235	+ default 4
	236	+
	237	+config ARM64_CONT_PMD_SHIFT
	238	+ int
	239	+ default 5 if ARM64_64K_PAGES
	240	+ default 5 if ARM64_16K_PAGES
197	241	default 4
198	242
199	243	config ARCH_MMAP_RND_BITS_MIN
..	..	@@ -239,9 +283,6 @@
239	283	config TRACE_IRQFLAGS_SUPPORT
240	284	def_bool y
241	285
242		-config RWSEM_XCHGADD_ALGORITHM
243		- def_bool y
244		-
245	286	config GENERIC_BUG
246	287	def_bool y
247	288	depends on BUG
..	..	@@ -259,11 +300,18 @@
259	300	config GENERIC_CALIBRATE_DELAY
260	301	def_bool y
261	302
	303	+config ZONE_DMA
	304	+ bool "Support DMA zone" if EXPERT
	305	+ default y
	306	+
262	307	config ZONE_DMA32
263	308	bool "Support DMA32 zone" if EXPERT
264	309	default y
265	310
266		-config HAVE_GENERIC_GUP
	311	+config ARCH_ENABLE_MEMORY_HOTPLUG
	312	+ def_bool y
	313	+
	314	+config ARCH_ENABLE_MEMORY_HOTREMOVE
267	315	def_bool y
268	316
269	317	config SMP
..	..	@@ -279,7 +327,7 @@
279	327	int
280	328	default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
281	329	default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
282		- default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
	330	+ default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 \|\| ARM64_VA_BITS_52)
283	331	default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
284	332	default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
285	333	default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
..	..	@@ -290,37 +338,37 @@
290	338	config ARCH_PROC_KCORE_TEXT
291	339	def_bool y
292	340
	341	+config BROKEN_GAS_INST
	342	+ def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
	343	+
	344	+config KASAN_SHADOW_OFFSET
	345	+ hex
	346	+ depends on KASAN_GENERIC \|\| KASAN_SW_TAGS
	347	+ default 0xdfffa00000000000 if (ARM64_VA_BITS_48 \|\| ARM64_VA_BITS_52) && !KASAN_SW_TAGS
	348	+ default 0xdfffd00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
	349	+ default 0xdffffe8000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
	350	+ default 0xdfffffd000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
	351	+ default 0xdffffffa00000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
	352	+ default 0xefff900000000000 if (ARM64_VA_BITS_48 \|\| ARM64_VA_BITS_52) && KASAN_SW_TAGS
	353	+ default 0xefffc80000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
	354	+ default 0xeffffe4000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
	355	+ default 0xefffffc800000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
	356	+ default 0xeffffff900000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
	357	+ default 0xffffffffffffffff
	358	+
293	359	source "arch/arm64/Kconfig.platforms"
294		-
295		-menu "Bus support"
296		-
297		-config PCI
298		- bool "PCI support"
299		- help
300		- This feature enables support for PCI bus system. If you say Y
301		- here, the kernel will include drivers and infrastructure code
302		- to support PCI bus devices.
303		-
304		-config PCI_DOMAINS
305		- def_bool PCI
306		-
307		-config PCI_DOMAINS_GENERIC
308		- def_bool PCI
309		-
310		-config PCI_SYSCALL
311		- def_bool PCI
312		-
313		-source "drivers/pci/Kconfig"
314		-
315		-endmenu
316	360
317	361	menu "Kernel Features"
318	362
319	363	menu "ARM errata workarounds via the alternatives framework"
320	364
	365	+config ARM64_WORKAROUND_CLEAN_CACHE
	366	+ bool
	367	+
321	368	config ARM64_ERRATUM_826319
322	369	bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
323	370	default y
	371	+ select ARM64_WORKAROUND_CLEAN_CACHE
324	372	help
325	373	This option adds an alternative code sequence to work around ARM
326	374	erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
..	..	@@ -342,6 +390,7 @@
342	390	config ARM64_ERRATUM_827319
343	391	bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
344	392	default y
	393	+ select ARM64_WORKAROUND_CLEAN_CACHE
345	394	help
346	395	This option adds an alternative code sequence to work around ARM
347	396	erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
..	..	@@ -363,6 +412,7 @@
363	412	config ARM64_ERRATUM_824069
364	413	bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
365	414	default y
	415	+ select ARM64_WORKAROUND_CLEAN_CACHE
366	416	help
367	417	This option adds an alternative code sequence to work around ARM
368	418	erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
..	..	@@ -385,6 +435,7 @@
385	435	config ARM64_ERRATUM_819472
386	436	bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
387	437	default y
	438	+ select ARM64_WORKAROUND_CLEAN_CACHE
388	439	help
389	440	This option adds an alternative code sequence to work around ARM
390	441	erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
..	..	@@ -442,6 +493,22 @@
442	493
443	494	If unsure, say Y.
444	495
	496	+config ARM64_ERRATUM_1742098
	497	+ bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence"
	498	+ depends on COMPAT
	499	+ default y
	500	+ help
	501	+ This option removes the AES hwcap for aarch32 user-space to
	502	+ workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
	503	+
	504	+ Affected parts may corrupt the AES state if an interrupt is
	505	+ taken between a pair of AES instructions. These instructions
	506	+ are only present if the cryptography extensions are present.
	507	+ All software should have a fallback implementation for CPUs
	508	+ that don't implement the cryptography extensions.
	509	+
	510	+ If unsure, say Y.
	511	+
445	512	config ARM64_ERRATUM_845719
446	513	bool "Cortex-A53: 845719: a load might read incorrect data"
447	514	depends on COMPAT
..	..	@@ -479,15 +546,90 @@
479	546	bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
480	547	default y
481	548	help
482		- This option adds work around for Arm Cortex-A55 Erratum 1024718.
	549	+ This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
483	550
484	551	Affected Cortex-A55 cores (all revisions) could cause incorrect
485	552	update of the hardware dirty bit when the DBM/AP bits are updated
486		- without a break-before-make. The work around is to disable the usage
	553	+ without a break-before-make. The workaround is to disable the usage
487	554	of hardware DBM locally on the affected cores. CPUs not affected by
488		- erratum will continue to use the feature.
	555	+ this erratum will continue to use the feature.
489	556
490	557	If unsure, say Y.
	558	+
	559	+config ARM64_ERRATUM_1418040
	560	+ bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
	561	+ default y
	562	+ depends on COMPAT
	563	+ help
	564	+ This option adds a workaround for ARM Cortex-A76/Neoverse-N1
	565	+ errata 1188873 and 1418040.
	566	+
	567	+ Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
	568	+ cause register corruption when accessing the timer registers
	569	+ from AArch32 userspace.
	570	+
	571	+ If unsure, say Y.
	572	+
	573	+config ARM64_WORKAROUND_SPECULATIVE_AT
	574	+ bool
	575	+
	576	+config ARM64_ERRATUM_1165522
	577	+ bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
	578	+ default y
	579	+ select ARM64_WORKAROUND_SPECULATIVE_AT
	580	+ help
	581	+ This option adds a workaround for ARM Cortex-A76 erratum 1165522.
	582	+
	583	+ Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
	584	+ corrupted TLBs by speculating an AT instruction during a guest
	585	+ context switch.
	586	+
	587	+ If unsure, say Y.
	588	+
	589	+config ARM64_ERRATUM_1319367
	590	+ bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
	591	+ default y
	592	+ select ARM64_WORKAROUND_SPECULATIVE_AT
	593	+ help
	594	+ This option adds work arounds for ARM Cortex-A57 erratum 1319537
	595	+ and A72 erratum 1319367
	596	+
	597	+ Cortex-A57 and A72 cores could end-up with corrupted TLBs by
	598	+ speculating an AT instruction during a guest context switch.
	599	+
	600	+ If unsure, say Y.
	601	+
	602	+config ARM64_ERRATUM_1530923
	603	+ bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
	604	+ default y
	605	+ select ARM64_WORKAROUND_SPECULATIVE_AT
	606	+ help
	607	+ This option adds a workaround for ARM Cortex-A55 erratum 1530923.
	608	+
	609	+ Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
	610	+ corrupted TLBs by speculating an AT instruction during a guest
	611	+ context switch.
	612	+
	613	+ If unsure, say Y.
	614	+
	615	+config ARM64_WORKAROUND_REPEAT_TLBI
	616	+ bool
	617	+
	618	+config ARM64_ERRATUM_1286807
	619	+ bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
	620	+ default y
	621	+ select ARM64_WORKAROUND_REPEAT_TLBI
	622	+ help
	623	+ This option adds a workaround for ARM Cortex-A76 erratum 1286807.
	624	+
	625	+ On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
	626	+ address for a cacheable mapping of a location is being
	627	+ accessed by a core while another core is remapping the virtual
	628	+ address to a new physical page using the recommended
	629	+ break-before-make sequence, then under very rare circumstances
	630	+ TLBI+DSB completes before a read using the translation being
	631	+ invalidated has been observed by other observers. The
	632	+ workaround repeats the TLBI+DSB operation.
491	633
492	634	config ARM64_ERRATUM_1463225
493	635	bool "Cortex-A76: Software Step might prevent interrupt recognition"
..	..	@@ -523,14 +665,119 @@
523	665
524	666	If unsure, say Y.
525	667
	668	+config ARM64_ERRATUM_1508412
	669	+ bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
	670	+ default y
	671	+ help
	672	+ This option adds a workaround for Arm Cortex-A77 erratum 1508412.
	673	+
	674	+ Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
	675	+ of a store-exclusive or read of PAR_EL1 and a load with device or
	676	+ non-cacheable memory attributes. The workaround depends on a firmware
	677	+ counterpart.
	678	+
	679	+ KVM guests must also have the workaround implemented or they can
	680	+ deadlock the system.
	681	+
	682	+ Work around the issue by inserting DMB SY barriers around PAR_EL1
	683	+ register reads and warning KVM users. The DMB barrier is sufficient
	684	+ to prevent a speculative PAR_EL1 read.
	685	+
	686	+ If unsure, say Y.
	687	+
	688	+config ARM64_ERRATUM_2051678
	689	+ bool "Cortex-A510: 2051678: disable Hardware Update of the page table's dirty bit"
	690	+ default y
	691	+ help
	692	+ This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
	693	+ Affected Coretex-A510 might not respect the ordering rules for
	694	+ hardware update of the page table's dirty bit. The workaround
	695	+ is to not enable the feature on affected CPUs.
	696	+
	697	+ If unsure, say Y.
	698	+
	699	+config ARM64_WORKAROUND_TSB_FLUSH_FAILURE
	700	+ bool
	701	+
	702	+config ARM64_ERRATUM_2054223
	703	+ bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
	704	+ default y
	705	+ select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
	706	+ help
	707	+ Enable workaround for ARM Cortex-A710 erratum 2054223
	708	+
	709	+ Affected cores may fail to flush the trace data on a TSB instruction, when
	710	+ the PE is in trace prohibited state. This will cause losing a few bytes
	711	+ of the trace cached.
	712	+
	713	+ Workaround is to issue two TSB consecutively on affected cores.
	714	+
	715	+ If unsure, say Y.
	716	+
	717	+config ARM64_ERRATUM_2067961
	718	+ bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
	719	+ default y
	720	+ select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
	721	+ help
	722	+ Enable workaround for ARM Neoverse-N2 erratum 2067961
	723	+
	724	+ Affected cores may fail to flush the trace data on a TSB instruction, when
	725	+ the PE is in trace prohibited state. This will cause losing a few bytes
	726	+ of the trace cached.
	727	+
	728	+ Workaround is to issue two TSB consecutively on affected cores.
	729	+
	730	+ If unsure, say Y.
	731	+
	732	+config ARM64_ERRATUM_2454944
	733	+ bool "Cortex-A510: 2454944: Unmodified cache line might be written back to memory"
	734	+ select ARCH_HAS_TEARDOWN_DMA_OPS
	735	+ select RODATA_FULL_DEFAULT_ENABLED
	736	+ help
	737	+ This option adds the workaround for ARM Cortex-A510 erratum 2454944.
	738	+
	739	+ Affected Cortex-A510 core might write unmodified cache lines back to
	740	+ memory, which breaks the assumptions upon which software coherency
	741	+ management for non-coherent DMA relies. If a cache line is
	742	+ speculatively fetched while a non-coherent device is writing directly
	743	+ to DRAM, and subsequently written back by natural eviction, data
	744	+ written by the device in the intervening period can be lost.
	745	+
	746	+ The workaround is to enforce as far as reasonably possible that all
	747	+ non-coherent DMA transfers are bounced and/or remapped to minimise
	748	+ the chance that any Cacheable alias exists through which speculative
	749	+ cache fills could occur. To further improve effectiveness of
	750	+ the workaround, lazy TLB flushing should be disabled.
	751	+
	752	+ This is quite involved and has unavoidable performance impact on
	753	+ affected systems.
	754	+
	755	+config ARM64_ERRATUM_2457168
	756	+ bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
	757	+ depends on ARM64_AMU_EXTN
	758	+ default y
	759	+ help
	760	+ This option adds the workaround for ARM Cortex-A510 erratum 2457168.
	761	+
	762	+ The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate
	763	+ as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
	764	+ incorrectly giving a significantly higher output value.
	765	+
	766	+ Work around this problem by keeping the reference values of affected counters
	767	+ to 0 thus signaling an error case. This effect is the same to firmware disabling
	768	+ affected counters, in which case 0 will be returned when reading the disabled
	769	+ counters.
	770	+
	771	+ If unsure, say Y.
	772	+
526	773	config CAVIUM_ERRATUM_22375
527	774	bool "Cavium erratum 22375, 24313"
528	775	default y
529	776	help
530		- Enable workaround for erratum 22375, 24313.
	777	+ Enable workaround for errata 22375 and 24313.
531	778
532	779	This implements two gicv3-its errata workarounds for ThunderX. Both
533		- with small impact affecting only ITS table allocation.
	780	+ with a small impact affecting only ITS table allocation.
534	781
535	782	erratum 22375: only alloc 8MB table size
536	783	erratum 24313: ignore memory access type
..	..	@@ -581,6 +828,52 @@
581	828
582	829	If unsure, say Y.
583	830
	831	+config CAVIUM_TX2_ERRATUM_219
	832	+ bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
	833	+ default y
	834	+ help
	835	+ On Cavium ThunderX2, a load, store or prefetch instruction between a
	836	+ TTBR update and the corresponding context synchronizing operation can
	837	+ cause a spurious Data Abort to be delivered to any hardware thread in
	838	+ the CPU core.
	839	+
	840	+ Work around the issue by avoiding the problematic code sequence and
	841	+ trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
	842	+ trap handler performs the corresponding register access, skips the
	843	+ instruction and ensures context synchronization by virtue of the
	844	+ exception return.
	845	+
	846	+ If unsure, say Y.
	847	+
	848	+config FUJITSU_ERRATUM_010001
	849	+ bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
	850	+ default y
	851	+ help
	852	+ This option adds a workaround for Fujitsu-A64FX erratum E#010001.
	853	+ On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
	854	+ accesses may cause undefined fault (Data abort, DFSC=0b111111).
	855	+ This fault occurs under a specific hardware condition when a
	856	+ load/store instruction performs an address translation using:
	857	+ case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
	858	+ case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
	859	+ case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
	860	+ case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
	861	+
	862	+ The workaround is to ensure these bits are clear in TCR_ELx.
	863	+ The workaround only affects the Fujitsu-A64FX.
	864	+
	865	+ If unsure, say Y.
	866	+
	867	+config HISILICON_ERRATUM_161600802
	868	+ bool "Hip07 161600802: Erroneous redistributor VLPI base"
	869	+ default y
	870	+ help
	871	+ The HiSilicon Hip07 SoC uses the wrong redistributor base
	872	+ when issued ITS commands such as VMOVP and VMAPP, and requires
	873	+ a 128kB offset to be applied to the target address in this commands.
	874	+
	875	+ If unsure, say Y.
	876	+
584	877	config QCOM_FALKOR_ERRATUM_1003
585	878	bool "Falkor E1003: Incorrect translation due to ASID change"
586	879	default y
..	..	@@ -595,6 +888,7 @@
595	888	config QCOM_FALKOR_ERRATUM_1009
596	889	bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
597	890	default y
	891	+ select ARM64_WORKAROUND_REPEAT_TLBI
598	892	help
599	893	On Falkor v1, the CPU may prematurely complete a DSB following a
600	894	TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
..	..	@@ -612,25 +906,6 @@
612	906
613	907	If unsure, say Y.
614	908
615		-config SOCIONEXT_SYNQUACER_PREITS
616		- bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
617		- default y
618		- help
619		- Socionext Synquacer SoCs implement a separate h/w block to generate
620		- MSI doorbell writes with non-zero values for the device ID.
621		-
622		- If unsure, say Y.
623		-
624		-config HISILICON_ERRATUM_161600802
625		- bool "Hip07 161600802: Erroneous redistributor VLPI base"
626		- default y
627		- help
628		- The HiSilicon Hip07 SoC usees the wrong redistributor base
629		- when issued ITS commands such as VMOVP and VMAPP, and requires
630		- a 128kB offset to be applied to the target address in this commands.
631		-
632		- If unsure, say Y.
633		-
634	909	config QCOM_FALKOR_ERRATUM_E1041
635	910	bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
636	911	default y
..	..	@@ -638,6 +913,15 @@
638	913	Falkor CPU may speculatively fetch instructions from an improper
639	914	memory location when MMU translation is changed from SCTLR_ELn[M]=1
640	915	to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
	916	+
	917	+ If unsure, say Y.
	918	+
	919	+config SOCIONEXT_SYNQUACER_PREITS
	920	+ bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
	921	+ default y
	922	+ help
	923	+ Socionext Synquacer SoCs implement a separate h/w block to generate
	924	+ MSI doorbell writes with non-zero values for the device ID.
641	925
642	926	If unsure, say Y.
643	927
..	..	@@ -701,7 +985,36 @@
701	985	config ARM64_VA_BITS_48
702	986	bool "48-bit"
703	987
	988	+config ARM64_VA_BITS_52
	989	+ bool "52-bit"
	990	+ depends on ARM64_64K_PAGES && (ARM64_PAN \|\| !ARM64_SW_TTBR0_PAN)
	991	+ help
	992	+ Enable 52-bit virtual addressing for userspace when explicitly
	993	+ requested via a hint to mmap(). The kernel will also use 52-bit
	994	+ virtual addresses for its own mappings (provided HW support for
	995	+ this feature is available, otherwise it reverts to 48-bit).
	996	+
	997	+ NOTE: Enabling 52-bit virtual addressing in conjunction with
	998	+ ARMv8.3 Pointer Authentication will result in the PAC being
	999	+ reduced from 7 bits to 3 bits, which may have a significant
	1000	+ impact on its susceptibility to brute-force attacks.
	1001	+
	1002	+ If unsure, select 48-bit virtual addressing instead.
	1003	+
704	1004	endchoice
	1005	+
	1006	+config ARM64_FORCE_52BIT
	1007	+ bool "Force 52-bit virtual addresses for userspace"
	1008	+ depends on ARM64_VA_BITS_52 && EXPERT
	1009	+ help
	1010	+ For systems with 52-bit userspace VAs enabled, the kernel will attempt
	1011	+ to maintain compatibility with older software by providing 48-bit VAs
	1012	+ unless a hint is supplied to mmap.
	1013	+
	1014	+ This configuration option disables the 48-bit compatibility logic, and
	1015	+ forces all userspace addresses to be 52-bit on HW that supports it. One
	1016	+ should only enable this configuration option for stress testing userspace
	1017	+ memory management code. If unsure say N here.
705	1018
706	1019	config ARM64_VA_BITS
707	1020	int
..	..	@@ -710,6 +1023,7 @@
710	1023	default 42 if ARM64_VA_BITS_42
711	1024	default 47 if ARM64_VA_BITS_47
712	1025	default 48 if ARM64_VA_BITS_48
	1026	+ default 52 if ARM64_VA_BITS_52
713	1027
714	1028	choice
715	1029	prompt "Physical address space size"
..	..	@@ -740,10 +1054,27 @@
740	1054	default 48 if ARM64_PA_BITS_48
741	1055	default 52 if ARM64_PA_BITS_52
742	1056
	1057	+choice
	1058	+ prompt "Endianness"
	1059	+ default CPU_LITTLE_ENDIAN
	1060	+ help
	1061	+ Select the endianness of data accesses performed by the CPU. Userspace
	1062	+ applications will need to be compiled and linked for the endianness
	1063	+ that is selected here.
	1064	+
743	1065	config CPU_BIG_ENDIAN
744		- bool "Build big-endian kernel"
745		- help
746		- Say Y if you plan on running a kernel in big-endian mode.
	1066	+ bool "Build big-endian kernel"
	1067	+ depends on !LD_IS_LLD \|\| LLD_VERSION >= 130000
	1068	+ help
	1069	+ Say Y if you plan on running a kernel with a big-endian userspace.
	1070	+
	1071	+config CPU_LITTLE_ENDIAN
	1072	+ bool "Build little-endian kernel"
	1073	+ help
	1074	+ Say Y if you plan on running a kernel with a little-endian userspace.
	1075	+ This is usually the case for distributions targeting arm64.
	1076	+
	1077	+endchoice
747	1078
748	1079	config SCHED_MC
749	1080	bool "Multi-core scheduler support"
..	..	@@ -762,8 +1093,7 @@
762	1093	config NR_CPUS
763	1094	int "Maximum number of CPUs (2-4096)"
764	1095	range 2 4096
765		- # These have to remain sorted largest to smallest
766		- default "64"
	1096	+ default "256"
767	1097
768	1098	config HOTPLUG_CPU
769	1099	bool "Support for hot-pluggable CPUs"
..	..	@@ -774,11 +1104,11 @@
774	1104
775	1105	# Common NUMA Features
776	1106	config NUMA
777		- bool "Numa Memory Allocation and Scheduler Support"
	1107	+ bool "NUMA Memory Allocation and Scheduler Support"
778	1108	select ACPI_NUMA if ACPI
779	1109	select OF_NUMA
780	1110	help
781		- Enable NUMA (Non Uniform Memory Access) support.
	1111	+ Enable NUMA (Non-Uniform Memory Access) support.
782	1112
783	1113	The kernel will try to allocate memory used by a CPU on the
784	1114	local memory of the CPU and add some more
..	..	@@ -787,7 +1117,7 @@
787	1117	config NODES_SHIFT
788	1118	int "Maximum NUMA Nodes (as a power of 2)"
789	1119	range 1 10
790		- default "2"
	1120	+ default "4"
791	1121	depends on NEED_MULTIPLE_NODES
792	1122	help
793	1123	Specify the maximum number of NUMA Nodes available on the target
..	..	@@ -808,13 +1138,10 @@
808	1138	config HOLES_IN_ZONE
809	1139	def_bool y
810	1140
811		-source kernel/Kconfig.hz
	1141	+source "kernel/Kconfig.hz"
812	1142
813	1143	config ARCH_SUPPORTS_DEBUG_PAGEALLOC
814	1144	def_bool y
815		-
816		-config ARCH_HAS_HOLES_MEMORYMODEL
817		- def_bool y if SPARSEMEM
818	1145
819	1146	config ARCH_SPARSEMEM_ENABLE
820	1147	def_bool y
..	..	@@ -830,7 +1157,7 @@
830	1157	def_bool !NUMA
831	1158
832	1159	config HAVE_ARCH_PFN_VALID
833		- def_bool ARCH_HAS_HOLES_MEMORYMODEL \|\| !SPARSEMEM
	1160	+ def_bool y
834	1161
835	1162	config HW_PERF_EVENTS
836	1163	def_bool y
..	..	@@ -840,59 +1167,16 @@
840	1167	def_bool y
841	1168
842	1169	config ARCH_WANT_HUGE_PMD_SHARE
843		- def_bool y if ARM64_4K_PAGES \|\| (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
844	1170
845	1171	config ARCH_HAS_CACHE_LINE_SIZE
846	1172	def_bool y
847	1173
	1174	+config ARCH_ENABLE_SPLIT_PMD_PTLOCK
	1175	+ def_bool y if PGTABLE_LEVELS > 2
848	1176
849	1177	# Supported by clang >= 7.0
850	1178	config CC_HAVE_SHADOW_CALL_STACK
851	1179	def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
852		-
853		-config ARM64_DMA_USE_IOMMU
854		- bool "ARM64 DMA iommu integration"
855		- select ARM_HAS_SG_CHAIN
856		- select NEED_SG_DMA_LENGTH
857		- help
858		- Enable using iommu through the standard dma apis.
859		- dma_alloc_coherent() will allocate scatter-gather memory
860		- which is made virtually contiguous via iommu.
861		- Enable if system contains IOMMU hardware.
862		-
863		-if ARM64_DMA_USE_IOMMU
864		-
865		-config ARM64_DMA_IOMMU_ALIGNMENT
866		- int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
867		- range 4 9
868		- default 9
869		- help
870		- DMA mapping framework by default aligns all buffers to the smallest
871		- PAGE_SIZE order which is greater than or equal to the requested buffer
872		- size. This works well for buffers up to a few hundreds kilobytes, but
873		- for larger buffers it just a waste of address space. Drivers which has
874		- relatively small addressing window (like 64Mib) might run out of
875		- virtual space with just a few allocations.
876		-
877		- With this parameter you can specify the maximum PAGE_SIZE order for
878		- DMA IOMMU buffers. Larger buffers will be aligned only to this
879		- specified order. The order is expressed as a power of two multiplied
880		- by the PAGE_SIZE.
881		-
882		-endif
883		-
884		-config SECCOMP
885		- bool "Enable seccomp to safely compute untrusted bytecode"
886		- ---help---
887		- This kernel feature is useful for number crunching applications
888		- that may need to compute untrusted bytecode during their
889		- execution. By using pipes or other transports made available to
890		- the process as file descriptors supporting the read/write
891		- syscalls, it's possible to isolate those applications in
892		- their own address space using seccomp. Once seccomp is
893		- enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
894		- and the task is only allowed to execute a few safe syscalls
895		- defined by each seccomp mode.
896	1180
897	1181	config PARAVIRT
898	1182	bool "Enable paravirtualization code"
..	..	@@ -904,7 +1188,6 @@
904	1188	config PARAVIRT_TIME_ACCOUNTING
905	1189	bool "Paravirtual steal time accounting"
906	1190	select PARAVIRT
907		- default n
908	1191	help
909	1192	Select this option to enable fine granularity task steal time
910	1193	accounting. Time spent executing other tasks in parallel with
..	..	@@ -917,11 +1200,44 @@
917	1200	depends on PM_SLEEP_SMP
918	1201	select KEXEC_CORE
919	1202	bool "kexec system call"
920		- ---help---
	1203	+ help
921	1204	kexec is a system call that implements the ability to shutdown your
922	1205	current kernel, and to start another kernel. It is like a reboot
923	1206	but it is independent of the system firmware. And like a reboot
924	1207	you can start any kernel with it, not just Linux.
	1208	+
	1209	+config KEXEC_FILE
	1210	+ bool "kexec file based system call"
	1211	+ select KEXEC_CORE
	1212	+ help
	1213	+ This is new version of kexec system call. This system call is
	1214	+ file based and takes file descriptors as system call argument
	1215	+ for kernel and initramfs as opposed to list of segments as
	1216	+ accepted by previous system call.
	1217	+
	1218	+config KEXEC_SIG
	1219	+ bool "Verify kernel signature during kexec_file_load() syscall"
	1220	+ depends on KEXEC_FILE
	1221	+ help
	1222	+ Select this option to verify a signature with loaded kernel
	1223	+ image. If configured, any attempt of loading a image without
	1224	+ valid signature will fail.
	1225	+
	1226	+ In addition to that option, you need to enable signature
	1227	+ verification for the corresponding kernel image type being
	1228	+ loaded in order for this to work.
	1229	+
	1230	+config KEXEC_IMAGE_VERIFY_SIG
	1231	+ bool "Enable Image signature verification support"
	1232	+ default y
	1233	+ depends on KEXEC_SIG
	1234	+ depends on EFI && SIGNED_PE_FILE_VERIFICATION
	1235	+ help
	1236	+ Enable Image signature verification support.
	1237	+
	1238	+comment "Support for PE file signature verification disabled"
	1239	+ depends on KEXEC_SIG
	1240	+ depends on !EFI \|\| !SIGNED_PE_FILE_VERIFICATION
925	1241
926	1242	config CRASH_DUMP
927	1243	bool "Build kdump crash kernel"
..	..	@@ -932,7 +1248,7 @@
932	1248	reserved region and then later executed after a crash by
933	1249	kdump/kexec.
934	1250
935		- For more details see Documentation/kdump/kdump.txt
	1251	+ For more details see Documentation/admin-guide/kdump/kdump.rst
936	1252
937	1253	config XEN_DOM0
938	1254	def_bool y
..	..	@@ -981,47 +1297,36 @@
981	1297
982	1298	If unsure, say Y.
983	1299
984		-config HARDEN_BRANCH_PREDICTOR
985		- bool "Harden the branch predictor against aliasing attacks" if EXPERT
986		- default y
987		- help
988		- Speculation attacks against some high-performance processors rely on
989		- being able to manipulate the branch predictor for a victim context by
990		- executing aliasing branches in the attacker context. Such attacks
991		- can be partially mitigated against by clearing internal branch
992		- predictor state and limiting the prediction logic in some situations.
993		-
994		- This config option will take CPU-specific actions to harden the
995		- branch predictor against aliasing attacks and may rely on specific
996		- instruction sequences or control bits being set by the system
997		- firmware.
998		-
999		- If unsure, say Y.
1000		-
1001		-config HARDEN_EL2_VECTORS
1002		- bool "Harden EL2 vector mapping against system register leak" if EXPERT
	1300	+config MITIGATE_SPECTRE_BRANCH_HISTORY
	1301	+ bool "Mitigate Spectre style attacks against branch history" if EXPERT
1003	1302	default y
1004	1303	help
1005	1304	Speculation attacks against some high-performance processors can
1006		- be used to leak privileged information such as the vector base
1007		- register, resulting in a potential defeat of the EL2 layout
1008		- randomization.
	1305	+ make use of branch history to influence future speculation.
	1306	+ When taking an exception from user-space, a sequence of branches
	1307	+ or a firmware call overwrites the branch history.
1009	1308
1010		- This config option will map the vectors to a fixed location,
1011		- independent of the EL2 code mapping, so that revealing VBAR_EL2
1012		- to an attacker does not give away any extra information. This
1013		- only gets enabled on affected CPUs.
1014		-
1015		- If unsure, say Y.
1016		-
1017		-config ARM64_SSBD
1018		- bool "Speculative Store Bypass Disable" if EXPERT
	1309	+config RODATA_FULL_DEFAULT_ENABLED
	1310	+ bool "Apply r/o permissions of VM areas also to their linear aliases"
1019	1311	default y
1020	1312	help
1021		- This enables mitigation of the bypassing of previous stores
1022		- by speculative loads.
	1313	+ Apply read-only attributes of VM areas to the linear alias of
	1314	+ the backing pages as well. This prevents code or read-only data
	1315	+ from being modified (inadvertently or intentionally) via another
	1316	+ mapping of the same memory page. This additional enhancement can
	1317	+ be turned off at runtime by passing rodata=[off\|on] (and turned on
	1318	+ with rodata=full if this option is set to 'n')
1023	1319
1024		- If unsure, say Y.
	1320	+ This requires the linear region to be mapped down to pages,
	1321	+ which may adversely affect performance in some cases.
	1322	+
	1323	+config ARM64_SW_TTBR0_PAN
	1324	+ bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
	1325	+ help
	1326	+ Enabling this option prevents the kernel from accessing
	1327	+ user-space memory directly by pointing TTBR0_EL1 to a reserved
	1328	+ zeroed area and reserved ASID. The user access routines
	1329	+ restore the valid TTBR0_EL1 temporarily.
1025	1330
1026	1331	config ARM64_TAGGED_ADDR_ABI
1027	1332	bool "Enable the tagged user addresses syscall ABI"
..	..	@@ -1032,9 +1337,58 @@
1032	1337	to system calls as pointer arguments. For details, see
1033	1338	Documentation/arm64/tagged-address-abi.rst.
1034	1339
	1340	+menuconfig COMPAT
	1341	+ bool "Kernel support for 32-bit EL0"
	1342	+ depends on ARM64_4K_PAGES \|\| EXPERT
	1343	+ select COMPAT_BINFMT_ELF if BINFMT_ELF
	1344	+ select HAVE_UID16
	1345	+ select OLD_SIGSUSPEND3
	1346	+ select COMPAT_OLD_SIGACTION
	1347	+ help
	1348	+ This option enables support for a 32-bit EL0 running under a 64-bit
	1349	+ kernel at EL1. AArch32-specific components such as system calls,
	1350	+ the user helper functions, VFP support and the ptrace interface are
	1351	+ handled appropriately by the kernel.
	1352	+
	1353	+ If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
	1354	+ that you will only be able to execute AArch32 binaries that were compiled
	1355	+ with page size aligned segments.
	1356	+
	1357	+ If you want to execute 32-bit userspace applications, say Y.
	1358	+
	1359	+if COMPAT
	1360	+
	1361	+config KUSER_HELPERS
	1362	+ bool "Enable kuser helpers page for 32-bit applications"
	1363	+ default y
	1364	+ help
	1365	+ Warning: disabling this option may break 32-bit user programs.
	1366	+
	1367	+ Provide kuser helpers to compat tasks. The kernel provides
	1368	+ helper code to userspace in read only form at a fixed location
	1369	+ to allow userspace to be independent of the CPU type fitted to
	1370	+ the system. This permits binaries to be run on ARMv4 through
	1371	+ to ARMv8 without modification.
	1372	+
	1373	+ See Documentation/arm/kernel_user_helpers.rst for details.
	1374	+
	1375	+ However, the fixed address nature of these helpers can be used
	1376	+ by ROP (return orientated programming) authors when creating
	1377	+ exploits.
	1378	+
	1379	+ If all of the binaries and libraries which run on your platform
	1380	+ are built specifically for your platform, and make no use of
	1381	+ these helpers, then you can turn this option off to hinder
	1382	+ such exploits. However, in that case, if a binary or library
	1383	+ relying on those helpers is run, it will not function correctly.
	1384	+
	1385	+ Say N here only if you are absolutely certain that you do not
	1386	+ need these helpers; otherwise, the safe option is to say Y.
	1387	+
1035	1388	config COMPAT_VDSO
1036	1389	bool "Enable vDSO for 32-bit applications"
1037		- depends on !CPU_BIG_ENDIAN && "$(CROSS_COMPILE_COMPAT)" != ""
	1390	+ depends on !CPU_BIG_ENDIAN
	1391	+ depends on (CC_IS_CLANG && LD_IS_LLD) \|\| "$(CROSS_COMPILE_COMPAT)" != ""
1038	1392	select GENERIC_COMPAT_VDSO
1039	1393	default y
1040	1394	help
..	..	@@ -1045,9 +1399,16 @@
1045	1399	You must have a 32-bit build of glibc 2.22 or later for programs
1046	1400	to seamlessly take advantage of this.
1047	1401
	1402	+config THUMB2_COMPAT_VDSO
	1403	+ bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
	1404	+ depends on COMPAT_VDSO
	1405	+ default y
	1406	+ help
	1407	+ Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
	1408	+ otherwise with '-marm'.
	1409	+
1048	1410	menuconfig ARMV8_DEPRECATED
1049	1411	bool "Emulate deprecated/obsolete ARMv8 instructions"
1050		- depends on COMPAT
1051	1412	depends on SYSCTL
1052	1413	help
1053	1414	Legacy software support may require certain instructions
..	..	@@ -1066,6 +1427,8 @@
1066	1427	ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1067	1428	they are always undefined. Say Y here to enable software
1068	1429	emulation of these instructions for userspace using LDXR/STXR.
	1430	+ This feature can be controlled at runtime with the abi.swp
	1431	+ sysctl which is disabled by default.
1069	1432
1070	1433	In some older versions of glibc [<=2.8] SWP is used during futex
1071	1434	trylock() operations with the assumption that the code will not
..	..	@@ -1092,7 +1455,8 @@
1092	1455	Say Y here to enable software emulation of these
1093	1456	instructions for AArch32 userspace code. When this option is
1094	1457	enabled, CP15 barrier usage is traced which can help
1095		- identify software that needs updating.
	1458	+ identify software that needs updating. This feature can be
	1459	+ controlled at runtime with the abi.cp15_barrier sysctl.
1096	1460
1097	1461	If unsure, say Y
1098	1462
..	..	@@ -1103,7 +1467,8 @@
1103	1467	AArch32 EL0, and is deprecated in ARMv8.
1104	1468
1105	1469	Say Y here to enable software emulation of the instruction
1106		- for AArch32 userspace code.
	1470	+ for AArch32 userspace code. This feature can be controlled
	1471	+ at runtime with the abi.setend sysctl.
1107	1472
1108	1473	Note: All the cpus on the system must have mixed endian support at EL0
1109	1474	for this feature to be enabled. If a new CPU - which doesn't support mixed
..	..	@@ -1113,13 +1478,7 @@
1113	1478	If unsure, say Y
1114	1479	endif
1115	1480
1116		-config ARM64_SW_TTBR0_PAN
1117		- bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1118		- help
1119		- Enabling this option prevents the kernel from accessing
1120		- user-space memory directly by pointing TTBR0_EL1 to a reserved
1121		- zeroed area and reserved ASID. The user access routines
1122		- restore the valid TTBR0_EL1 temporarily.
	1481	+endif
1123	1482
1124	1483	menu "ARMv8.1 architectural features"
1125	1484
..	..	@@ -1154,8 +1513,20 @@
1154	1513	The feature is detected at runtime, and will remain as a 'nop'
1155	1514	instruction if the cpu does not implement the feature.
1156	1515
	1516	+config AS_HAS_LDAPR
	1517	+ def_bool $(as-instr,.arch_extension rcpc)
	1518	+
	1519	+config AS_HAS_LSE_ATOMICS
	1520	+ def_bool $(as-instr,.arch_extension lse)
	1521	+
1157	1522	config ARM64_LSE_ATOMICS
	1523	+ bool
	1524	+ default ARM64_USE_LSE_ATOMICS
	1525	+ depends on AS_HAS_LSE_ATOMICS
	1526	+
	1527	+config ARM64_USE_LSE_ATOMICS
1158	1528	bool "Atomic instructions"
	1529	+ depends on JUMP_LABEL
1159	1530	default y
1160	1531	help
1161	1532	As part of the Large System Extensions, ARMv8.1 introduces new
..	..	@@ -1234,12 +1605,233 @@
1234	1605	and access the new registers if the system supports the extension.
1235	1606	Platform RAS features may additionally depend on firmware support.
1236	1607
	1608	+config ARM64_CNP
	1609	+ bool "Enable support for Common Not Private (CNP) translations"
	1610	+ default y
	1611	+ depends on ARM64_PAN \|\| !ARM64_SW_TTBR0_PAN
	1612	+ help
	1613	+ Common Not Private (CNP) allows translation table entries to
	1614	+ be shared between different PEs in the same inner shareable
	1615	+ domain, so the hardware can use this fact to optimise the
	1616	+ caching of such entries in the TLB.
	1617	+
	1618	+ Selecting this option allows the CNP feature to be detected
	1619	+ at runtime, and does not affect PEs that do not implement
	1620	+ this feature.
	1621	+
	1622	+endmenu
	1623	+
	1624	+menu "ARMv8.3 architectural features"
	1625	+
	1626	+config ARM64_PTR_AUTH
	1627	+ bool "Enable support for pointer authentication"
	1628	+ default y
	1629	+ depends on (CC_HAS_SIGN_RETURN_ADDRESS \|\| CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
	1630	+ # Modern compilers insert a .note.gnu.property section note for PAC
	1631	+ # which is only understood by binutils starting with version 2.33.1.
	1632	+ depends on LD_IS_LLD \|\| LD_VERSION >= 233010000 \|\| (CC_IS_GCC && GCC_VERSION < 90100)
	1633	+ depends on !CC_IS_CLANG \|\| AS_HAS_CFI_NEGATE_RA_STATE
	1634	+ depends on (!FUNCTION_GRAPH_TRACER \|\| DYNAMIC_FTRACE_WITH_REGS)
	1635	+ help
	1636	+ Pointer authentication (part of the ARMv8.3 Extensions) provides
	1637	+ instructions for signing and authenticating pointers against secret
	1638	+ keys, which can be used to mitigate Return Oriented Programming (ROP)
	1639	+ and other attacks.
	1640	+
	1641	+ This option enables these instructions at EL0 (i.e. for userspace).
	1642	+ Choosing this option will cause the kernel to initialise secret keys
	1643	+ for each process at exec() time, with these keys being
	1644	+ context-switched along with the process.
	1645	+
	1646	+ If the compiler supports the -mbranch-protection or
	1647	+ -msign-return-address flag (e.g. GCC 7 or later), then this option
	1648	+ will also cause the kernel itself to be compiled with return address
	1649	+ protection. In this case, and if the target hardware is known to
	1650	+ support pointer authentication, then CONFIG_STACKPROTECTOR can be
	1651	+ disabled with minimal loss of protection.
	1652	+
	1653	+ The feature is detected at runtime. If the feature is not present in
	1654	+ hardware it will not be advertised to userspace/KVM guest nor will it
	1655	+ be enabled.
	1656	+
	1657	+ If the feature is present on the boot CPU but not on a late CPU, then
	1658	+ the late CPU will be parked. Also, if the boot CPU does not have
	1659	+ address auth and the late CPU has then the late CPU will still boot
	1660	+ but with the feature disabled. On such a system, this option should
	1661	+ not be selected.
	1662	+
	1663	+ This feature works with FUNCTION_GRAPH_TRACER option only if
	1664	+ DYNAMIC_FTRACE_WITH_REGS is enabled.
	1665	+
	1666	+config CC_HAS_BRANCH_PROT_PAC_RET
	1667	+ # GCC 9 or later, clang 8 or later
	1668	+ def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
	1669	+
	1670	+config CC_HAS_SIGN_RETURN_ADDRESS
	1671	+ # GCC 7, 8
	1672	+ def_bool $(cc-option,-msign-return-address=all)
	1673	+
	1674	+config AS_HAS_PAC
	1675	+ def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
	1676	+
	1677	+config AS_HAS_CFI_NEGATE_RA_STATE
	1678	+ def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
	1679	+
	1680	+endmenu
	1681	+
	1682	+menu "ARMv8.4 architectural features"
	1683	+
	1684	+config ARM64_AMU_EXTN
	1685	+ bool "Enable support for the Activity Monitors Unit CPU extension"
	1686	+ default y
	1687	+ help
	1688	+ The activity monitors extension is an optional extension introduced
	1689	+ by the ARMv8.4 CPU architecture. This enables support for version 1
	1690	+ of the activity monitors architecture, AMUv1.
	1691	+
	1692	+ To enable the use of this extension on CPUs that implement it, say Y.
	1693	+
	1694	+ Note that for architectural reasons, firmware _must_ implement AMU
	1695	+ support when running on CPUs that present the activity monitors
	1696	+ extension. The required support is present in:
	1697	+ * Version 1.5 and later of the ARM Trusted Firmware
	1698	+
	1699	+ For kernels that have this configuration enabled but boot with broken
	1700	+ firmware, you may need to say N here until the firmware is fixed.
	1701	+ Otherwise you may experience firmware panics or lockups when
	1702	+ accessing the counter registers. Even if you are not observing these
	1703	+ symptoms, the values returned by the register reads might not
	1704	+ correctly reflect reality. Most commonly, the value read will be 0,
	1705	+ indicating that the counter is not enabled.
	1706	+
	1707	+config AS_HAS_ARMV8_4
	1708	+ def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
	1709	+
	1710	+config ARM64_TLB_RANGE
	1711	+ bool "Enable support for tlbi range feature"
	1712	+ default y
	1713	+ depends on AS_HAS_ARMV8_4
	1714	+ help
	1715	+ ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
	1716	+ range of input addresses.
	1717	+
	1718	+ The feature introduces new assembly instructions, and they were
	1719	+ support when binutils >= 2.30.
	1720	+
	1721	+endmenu
	1722	+
	1723	+menu "ARMv8.5 architectural features"
	1724	+
	1725	+config AS_HAS_ARMV8_5
	1726	+ def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
	1727	+
	1728	+config ARM64_BTI
	1729	+ bool "Branch Target Identification support"
	1730	+ default y
	1731	+ help
	1732	+ Branch Target Identification (part of the ARMv8.5 Extensions)
	1733	+ provides a mechanism to limit the set of locations to which computed
	1734	+ branch instructions such as BR or BLR can jump.
	1735	+
	1736	+ To make use of BTI on CPUs that support it, say Y.
	1737	+
	1738	+ BTI is intended to provide complementary protection to other control
	1739	+ flow integrity protection mechanisms, such as the Pointer
	1740	+ authentication mechanism provided as part of the ARMv8.3 Extensions.
	1741	+ For this reason, it does not make sense to enable this option without
	1742	+ also enabling support for pointer authentication. Thus, when
	1743	+ enabling this option you should also select ARM64_PTR_AUTH=y.
	1744	+
	1745	+ Userspace binaries must also be specifically compiled to make use of
	1746	+ this mechanism. If you say N here or the hardware does not support
	1747	+ BTI, such binaries can still run, but you get no additional
	1748	+ enforcement of branch destinations.
	1749	+
	1750	+config ARM64_BTI_KERNEL
	1751	+ bool "Use Branch Target Identification for kernel"
	1752	+ default y
	1753	+ depends on ARM64_BTI
	1754	+ depends on ARM64_PTR_AUTH
	1755	+ depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
	1756	+ # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
	1757	+ depends on !CC_IS_GCC \|\| GCC_VERSION >= 100100
	1758	+ # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671
	1759	+ depends on !CC_IS_GCC
	1760	+ # https://bugs.llvm.org/show_bug.cgi?id=46258
	1761	+ depends on !CFI_CLANG \|\| CLANG_VERSION >= 120000
	1762	+ depends on (!FUNCTION_GRAPH_TRACER \|\| DYNAMIC_FTRACE_WITH_REGS)
	1763	+ help
	1764	+ Build the kernel with Branch Target Identification annotations
	1765	+ and enable enforcement of this for kernel code. When this option
	1766	+ is enabled and the system supports BTI all kernel code including
	1767	+ modular code must have BTI enabled.
	1768	+
	1769	+config CC_HAS_BRANCH_PROT_PAC_RET_BTI
	1770	+ # GCC 9 or later, clang 8 or later
	1771	+ def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
	1772	+
	1773	+config ARM64_E0PD
	1774	+ bool "Enable support for E0PD"
	1775	+ default y
	1776	+ help
	1777	+ E0PD (part of the ARMv8.5 extensions) allows us to ensure
	1778	+ that EL0 accesses made via TTBR1 always fault in constant time,
	1779	+ providing similar benefits to KASLR as those provided by KPTI, but
	1780	+ with lower overhead and without disrupting legitimate access to
	1781	+ kernel memory such as SPE.
	1782	+
	1783	+ This option enables E0PD for TTBR1 where available.
	1784	+
	1785	+config ARCH_RANDOM
	1786	+ bool "Enable support for random number generation"
	1787	+ default y
	1788	+ help
	1789	+ Random number generation (part of the ARMv8.5 Extensions)
	1790	+ provides a high bandwidth, cryptographically secure
	1791	+ hardware random number generator.
	1792	+
	1793	+config ARM64_AS_HAS_MTE
	1794	+ # Initial support for MTE went in binutils 2.32.0, checked with
	1795	+ # ".arch armv8.5-a+memtag" below. However, this was incomplete
	1796	+ # as a late addition to the final architecture spec (LDGM/STGM)
	1797	+ # is only supported in the newer 2.32.x and 2.33 binutils
	1798	+ # versions, hence the extra "stgm" instruction check below.
	1799	+ def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
	1800	+
	1801	+config ARM64_MTE
	1802	+ bool "Memory Tagging Extension support"
	1803	+ default y
	1804	+ depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
	1805	+ depends on AS_HAS_ARMV8_5
	1806	+ # Required for tag checking in the uaccess routines
	1807	+ depends on ARM64_PAN
	1808	+ depends on AS_HAS_LSE_ATOMICS
	1809	+ select ARCH_USES_HIGH_VMA_FLAGS
	1810	+ help
	1811	+ Memory Tagging (part of the ARMv8.5 Extensions) provides
	1812	+ architectural support for run-time, always-on detection of
	1813	+ various classes of memory error to aid with software debugging
	1814	+ to eliminate vulnerabilities arising from memory-unsafe
	1815	+ languages.
	1816	+
	1817	+ This option enables the support for the Memory Tagging
	1818	+ Extension at EL0 (i.e. for userspace).
	1819	+
	1820	+ Selecting this option allows the feature to be detected at
	1821	+ runtime. Any secondary CPU not implementing this feature will
	1822	+ not be allowed a late bring-up.
	1823	+
	1824	+ Userspace binaries that want to use this feature must
	1825	+ explicitly opt in. The mechanism for the userspace is
	1826	+ described in:
	1827	+
	1828	+ Documentation/arm64/memory-tagging-extension.rst.
	1829	+
1237	1830	endmenu
1238	1831
1239	1832	config ARM64_SVE
1240	1833	bool "ARM Scalable Vector Extension support"
1241	1834	default y
1242		- depends on !KVM \|\| ARM64_VHE
1243	1835	help
1244	1836	The Scalable Vector Extension (SVE) is an extension to the AArch64
1245	1837	execution state which complements and extends the SIMD functionality
..	..	@@ -1247,6 +1839,9 @@
1247	1839	additional vectorisation opportunities.
1248	1840
1249	1841	To enable use of this extension on CPUs that implement it, say Y.
	1842	+
	1843	+ On CPUs that support the SVE2 extensions, this option will enable
	1844	+ those too.
1250	1845
1251	1846	Note that for architectural reasons, firmware _must_ implement SVE
1252	1847	support when running on SVE capable hardware. The required support
..	..	@@ -1265,19 +1860,55 @@
1265	1860	booting the kernel. If unsure and you are not observing these
1266	1861	symptoms, you should assume that it is safe to say Y.
1267	1862
1268		- CPUs that support SVE are architecturally required to support the
1269		- Virtualization Host Extensions (VHE), so the kernel makes no
1270		- provision for supporting SVE alongside KVM without VHE enabled.
1271		- Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1272		- KVM in the same kernel image.
1273		-
1274	1863	config ARM64_MODULE_PLTS
1275		- bool
	1864	+ bool "Use PLTs to allow module memory to spill over into vmalloc area"
	1865	+ depends on MODULES
1276	1866	select HAVE_MOD_ARCH_SPECIFIC
	1867	+ help
	1868	+ Allocate PLTs when loading modules so that jumps and calls whose
	1869	+ targets are too far away for their relative offsets to be encoded
	1870	+ in the instructions themselves can be bounced via veneers in the
	1871	+ module's PLT. This allows modules to be allocated in the generic
	1872	+ vmalloc area after the dedicated module memory area has been
	1873	+ exhausted.
	1874	+
	1875	+ When running with address space randomization (KASLR), the module
	1876	+ region itself may be too far away for ordinary relative jumps and
	1877	+ calls, and so in that case, module PLTs are required and cannot be
	1878	+ disabled.
	1879	+
	1880	+ Specific errata workaround(s) might also force module PLTs to be
	1881	+ enabled (ARM64_ERRATUM_843419).
	1882	+
	1883	+config ARM64_PSEUDO_NMI
	1884	+ bool "Support for NMI-like interrupts"
	1885	+ select ARM_GIC_V3
	1886	+ help
	1887	+ Adds support for mimicking Non-Maskable Interrupts through the use of
	1888	+ GIC interrupt priority. This support requires version 3 or later of
	1889	+ ARM GIC.
	1890	+
	1891	+ This high priority configuration for interrupts needs to be
	1892	+ explicitly enabled by setting the kernel parameter
	1893	+ "irqchip.gicv3_pseudo_nmi" to 1.
	1894	+
	1895	+ If unsure, say N
	1896	+
	1897	+if ARM64_PSEUDO_NMI
	1898	+config ARM64_DEBUG_PRIORITY_MASKING
	1899	+ bool "Debug interrupt priority masking"
	1900	+ help
	1901	+ This adds runtime checks to functions enabling/disabling
	1902	+ interrupts when using priority masking. The additional checks verify
	1903	+ the validity of ICC_PMR_EL1 when calling concerned functions.
	1904	+
	1905	+ If unsure, say N
	1906	+endif
1277	1907
1278	1908	config RELOCATABLE
1279		- bool
	1909	+ bool "Build a relocatable kernel image" if EXPERT
1280	1910	select ARCH_HAS_RELR
	1911	+ default y
1281	1912	help
1282	1913	This builds the kernel as a Position Independent Executable (PIE),
1283	1914	which retains all relocation metadata required to relocate the
..	..	@@ -1321,6 +1952,13 @@
1321	1952	a limited range that contains the [_stext, _etext] interval of the
1322	1953	core kernel, so branch relocations are always in range.
1323	1954
	1955	+config CC_HAVE_STACKPROTECTOR_SYSREG
	1956	+ def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
	1957	+
	1958	+config STACKPROTECTOR_PER_TASK
	1959	+ def_bool y
	1960	+ depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
	1961	+
1324	1962	endmenu
1325	1963
1326	1964	menu "Boot options"
..	..	@@ -1345,6 +1983,9 @@
1345	1983	choice
1346	1984	prompt "Kernel command line type" if CMDLINE != ""
1347	1985	default CMDLINE_FROM_BOOTLOADER
	1986	+ help
	1987	+ Choose how the kernel will handle the provided default kernel
	1988	+ command line string.
1348	1989
1349	1990	config CMDLINE_FROM_BOOTLOADER
1350	1991	bool "Use bootloader kernel arguments if available"
..	..	@@ -1366,6 +2007,7 @@
1366	2007	loader passes other arguments to the kernel.
1367	2008	This is useful if you cannot or don't want to change the
1368	2009	command-line options your boot loader passes to the kernel.
	2010	+
1369	2011	endchoice
1370	2012
1371	2013	config EFI_STUB
..	..	@@ -1381,7 +2023,7 @@
1381	2023	select EFI_PARAMS_FROM_FDT
1382	2024	select EFI_RUNTIME_WRAPPERS
1383	2025	select EFI_STUB
1384		- select EFI_ARMSTUB
	2026	+ select EFI_GENERIC_STUB
1385	2027	default y
1386	2028	help
1387	2029	This option provides support for runtime services provided
..	..	@@ -1403,57 +2045,18 @@
1403	2045
1404	2046	endmenu
1405	2047
1406		-config COMPAT
1407		- bool "Kernel support for 32-bit EL0"
1408		- depends on ARM64_4K_PAGES \|\| EXPERT
1409		- select COMPAT_BINFMT_ELF if BINFMT_ELF
1410		- select HAVE_UID16
1411		- select OLD_SIGSUSPEND3
1412		- select COMPAT_OLD_SIGACTION
1413		- help
1414		- This option enables support for a 32-bit EL0 running under a 64-bit
1415		- kernel at EL1. AArch32-specific components such as system calls,
1416		- the user helper functions, VFP support and the ptrace interface are
1417		- handled appropriately by the kernel.
1418		-
1419		- If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1420		- that you will only be able to execute AArch32 binaries that were compiled
1421		- with page size aligned segments.
1422		-
1423		- If you want to execute 32-bit userspace applications, say Y.
1424		-
1425		-config KUSER_HELPERS
1426		- bool "Enable kuser helpers page for 32 bit applications."
1427		- depends on COMPAT
1428		- default y
1429		- help
1430		- Warning: disabling this option may break 32-bit user programs.
1431		-
1432		- Provide kuser helpers to compat tasks. The kernel provides
1433		- helper code to userspace in read only form at a fixed location
1434		- to allow userspace to be independent of the CPU type fitted to
1435		- the system. This permits binaries to be run on ARMv4 through
1436		- to ARMv8 without modification.
1437		-
1438		- See Documentation/arm/kernel_user_helpers.txt for details.
1439		-
1440		- However, the fixed address nature of these helpers can be used
1441		- by ROP (return orientated programming) authors when creating
1442		- exploits.
1443		-
1444		- If all of the binaries and libraries which run on your platform
1445		- are built specifically for your platform, and make no use of
1446		- these helpers, then you can turn this option off to hinder
1447		- such exploits. However, in that case, if a binary or library
1448		- relying on those helpers is run, it will not function correctly.
1449		-
1450		- Say N here only if you are absolutely certain that you do not
1451		- need these helpers; otherwise, the safe option is to say Y.
1452		-
1453	2048	config SYSVIPC_COMPAT
1454	2049	def_bool y
1455	2050	depends on COMPAT && SYSVIPC
1456	2051
	2052	+config ARCH_ENABLE_HUGEPAGE_MIGRATION
	2053	+ def_bool y
	2054	+ depends on HUGETLB_PAGE && MIGRATION
	2055	+
	2056	+config ARCH_ENABLE_THP_MIGRATION
	2057	+ def_bool y
	2058	+ depends on TRANSPARENT_HUGEPAGE
	2059	+
1457	2060	menu "Power management options"
1458	2061
1459	2062	source "kernel/power/Kconfig"