mk-rootfs.sh

hc

2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376

 kernel/arch/arm/mach-socfpga/socfpga.c
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@@ -1,24 +1,13 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later
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 /*
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  *  Copyright (C) 2012-2015 Altera Corporation
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License as published by
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- * the Free Software Foundation; either version 2 of the License, or
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- * (at your option) any later version.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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  */
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 #include <linux/irqchip.h>
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 #include <linux/of_address.h>
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 #include <linux/of_irq.h>
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 #include <linux/of_platform.h>
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 #include <linux/reboot.h>
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+#include <linux/reset/socfpga.h>
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 #include <asm/hardware/cache-l2x0.h>
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 #include <asm/mach/arch.h>
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@@ -32,7 +21,7 @@
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 void __iomem *sdr_ctl_base_addr;
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 unsigned long socfpga_cpu1start_addr;
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-void __init socfpga_sysmgr_init(void)
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+static void __init socfpga_sysmgr_init(void)
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 {
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 	struct device_node *np;
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@@ -64,6 +53,7 @@
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 	if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM))
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 		socfpga_init_ocram_ecc();
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+	socfpga_reset_init();
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 }
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 static void __init socfpga_arria10_init_irq(void)
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@@ -74,6 +64,7 @@
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 		socfpga_init_arria10_l2_ecc();
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 	if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM))
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 		socfpga_init_arria10_ocram_ecc();
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+	socfpga_reset_init();
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 }
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 static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
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@@ -82,10 +73,10 @@
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 	temp = readl(rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
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-	if (mode == REBOOT_HARD)
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-		temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
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-	else
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+	if (mode == REBOOT_WARM)
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 		temp |= RSTMGR_CTRL_SWWARMRSTREQ;
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+	else
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+		temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
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 	writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
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 }
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@@ -95,10 +86,10 @@
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 	temp = readl(rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
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-	if (mode == REBOOT_HARD)
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-		temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
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-	else
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+	if (mode == REBOOT_WARM)
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 		temp |= RSTMGR_CTRL_SWWARMRSTREQ;
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+	else
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+		temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
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 	writel(temp, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
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 }
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