forked from ~ljy/RK356X_SDK_RELEASE
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hc
2023-12-11 072de836f53be56a70cecf70b43ae43b7ce17376 
 kernel/arch/arm/boot/dts/rv1126.dtsi
....@@ -24,7 +24,6 @@
2424 	interrupt-parent = <&gic>;
2525 
2626 	aliases {
27
-		ethernet0 = &gmac;
2827 		i2c0 = &i2c0;
2928 		i2c1 = &i2c1;
3029 		i2c2 = &i2c2;
....@@ -126,15 +125,16 @@
126125 		clocks = <&cru PLL_APLL>;
127126 		rockchip,bin-scaling-sel = <
128127 			0	5
129
-			1	18
128
+			1	9
130129 		>;
131130 		rockchip,bin-voltage-sel = <
132131 			1	0
133132 		>;
134133 		rockchip,pvtm-voltage-sel = <
135
-			0        106000   1
136
-			106001   112000   2
137
-			112001   999999   3
134
+			0        100500   1
135
+			100501   104500   2
136
+			104501   109500   3
137
+			109501   999999   4
138138 		>;
139139 		rockchip,pvtm-freq = <408000>;
140140 		rockchip,pvtm-volt = <800000>;
....@@ -172,6 +172,7 @@
172172 			opp-microvolt-L1 = <775000 775000 1000000>;
173173 			opp-microvolt-L2 = <775000 775000 1000000>;
174174 			opp-microvolt-L3 = <750000 750000 1000000>;
175
+			opp-microvolt-L4 = <725000 725000 1000000>;
175176 			clock-latency-ns = <40000>;
176177 		};
177178 		opp-1200000000 {
....@@ -181,22 +182,27 @@
181182 			opp-microvolt-L1 = <850000 850000 1000000>;
182183 			opp-microvolt-L2 = <850000 850000 1000000>;
183184 			opp-microvolt-L3 = <825000 825000 1000000>;
185
+			opp-microvolt-L4 = <800000 800000 1000000>;
184186 			clock-latency-ns = <40000>;
185187 		};
186188 		opp-1296000000 {
187189 			opp-hz = /bits/ 64 <1296000000>;
188190 			opp-microvolt = <875000 875000 1000000>;
191
+			opp-microvolt-L0 = <925000 925000 1000000>;
189192 			opp-microvolt-L1 = <875000 875000 1000000>;
190193 			opp-microvolt-L2 = <875000 875000 1000000>;
191194 			opp-microvolt-L3 = <850000 850000 1000000>;
195
+			opp-microvolt-L4 = <825000 825000 1000000>;
192196 			clock-latency-ns = <40000>;
193197 		};
194198 		opp-1416000000 {
195199 			opp-hz = /bits/ 64 <1416000000>;
196200 			opp-microvolt = <925000 925000 1000000>;
201
+			opp-microvolt-L0 = <975000 975000 1000000>;
197202 			opp-microvolt-L1 = <925000 925000 1000000>;
198203 			opp-microvolt-L2 = <925000 925000 1000000>;
199204 			opp-microvolt-L3 = <900000 900000 1000000>;
205
+			opp-microvolt-L4 = <875000 875000 1000000>;
200206 			clock-latency-ns = <40000>;
201207 		};
202208 		opp-1512000000 {
....@@ -205,6 +211,7 @@
205211 			opp-microvolt-L1 = <975000 975000 1000000>;
206212 			opp-microvolt-L2 = <950000 950000 1000000>;
207213 			opp-microvolt-L3 = <925000 925000 1000000>;
214
+			opp-microvolt-L4 = <900000 900000 1000000>;
208215 			clock-latency-ns = <40000>;
209216 		};
210217 	};
....@@ -346,6 +353,12 @@
346353 		};
347354 	};
348355 
356
+	mipi_csi2: mipi-csi2 {
357
+		compatible = "rockchip,rv1126-mipi-csi2";
358
+		rockchip,hw = <&mipi_csi2_hw>;
359
+		status = "disabled";
360
+	};
361
+
349362 	mpp_srv: mpp-srv {
350363 		compatible = "rockchip,mpp-service";
351364 		rockchip,taskqueue-count = <4>;
....@@ -390,8 +403,6 @@
390403 			console-size = <0x40000>;
391404 			ftrace-size = <0x00000>;
392405 			pmsg-size = <0x40000>;
393
-			mcu-log-size = <0x40000>;
394
-			mcu-log-count = <0x1>;
395406 			status = "disabled";
396407 		};
397408 	};
....@@ -1163,13 +1174,14 @@
11631174 	};
11641175 
11651176 	mipi_dphy: mipi-dphy@ff4d0000 {
1166
-		compatible = "rockchip,rv1126-mipi-dphy", "rockchip,rk1808-mipi-dphy";
1167
-		reg = <0xff4d0000 0x500>;
1177
+		compatible = "rockchip,rv1126-mipi-dphy", "rockchip,rk3568-video-phy";
1178
+		reg = <0xff4d0000 0x500>, <0xffb30000 0x500>;
1179
+		reg-names = "phy", "host";
11681180 		assigned-clocks = <&pmucru CLK_MIPIDSIPHY_REF>;
11691181 		assigned-clock-rates = <24000000>;
1170
-		clocks = <&pmucru CLK_MIPIDSIPHY_REF>, <&cru PCLK_DSIPHY>;
1171
-		clock-names = "ref", "pclk";
1172
-		clock-output-names = "mipi_dphy_pll";
1182
+		clocks = <&pmucru CLK_MIPIDSIPHY_REF>,
1183
+			 <&cru PCLK_DSIPHY>, <&cru PCLK_DSIHOST>;
1184
+		clock-names = "ref", "pclk", "pclk_host";
11731185 		#clock-cells = <0>;
11741186 		resets = <&cru SRST_DSIPHY_P>;
11751187 		reset-names = "apb";
....@@ -1625,7 +1637,7 @@
16251637 	};
16261638 
16271639 	pdm: pdm@ff830000 {
1628
-		compatible = "rockchip,rv1126-pdm";
1640
+		compatible = "rockchip,rv1126-pdm", "rockchip,pdm";
16291641 		reg = <0xff830000 0x1000>;
16301642 		clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>;
16311643 		clock-names = "pdm_clk", "pdm_hclk";
....@@ -1855,8 +1867,8 @@
18551867 		status = "disabled";
18561868 	};
18571869 
1858
-	mipi_csi2: mipi-csi2@ffb10000 {
1859
-		compatible = "rockchip,rv1126-mipi-csi2";
1870
+	mipi_csi2_hw: mipi-csi2-hw@ffb10000 {
1871
+		compatible = "rockchip,rv1126-mipi-csi2-hw";
18601872 		reg = <0xffb10000 0x10000>;
18611873 		reg-names = "csihost_regs";
18621874 		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
....@@ -1904,12 +1916,12 @@
19041916 		compatible = "rockchip,rv1126-mipi-dsi";
19051917 		reg = <0xffb30000 0x500>;
19061918 		interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1907
-		clocks = <&cru PCLK_DSIHOST>, <&mipi_dphy>;
1908
-		clock-names = "pclk", "hs_clk";
1919
+		clocks = <&cru PCLK_DSIHOST>, <&cru HCLK_PDVO>;
1920
+		clock-names = "pclk", "hclk";
19091921 		resets = <&cru SRST_DSIHOST_P>;
19101922 		reset-names = "apb";
19111923 		phys = <&mipi_dphy>;
1912
-		phy-names = "mipi_dphy";
1924
+		phy-names = "dphy";
19131925 		rockchip,grf = <&grf>;
19141926 		#address-cells = <1>;
19151927 		#size-cells = <0>;
....@@ -2107,7 +2119,7 @@
21072119 	};
21082120 
21092121 	rkvdec: rkvdec@ffb80000 {
2110
-		compatible = "rockchip,rkv-decoder-rv1126", "rockchip,rkv-decoder-v1";
2122
+		compatible = "rockchip,rkv-decoder-v1";
21112123 		reg = <0xffb80000 0x400>;
21122124 		interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
21132125 		interrupt-names = "irq_dec";
....@@ -2231,7 +2243,7 @@
22312243 		clocks = <&pmucru PLL_GPLL>;
22322244 		rockchip,bin-scaling-sel = <
22332245 			0	37
2234
-			1	43
2246
+			1	40
22352247 		>;
22362248 		rockchip,bin-voltage-sel = <
22372249 			1	0
....@@ -2253,6 +2265,7 @@
22532265 		opp-500000000 {
22542266 			opp-hz = /bits/ 64 <500000000>;
22552267 			opp-microvolt = <750000 750000 1000000>;
2268
+			opp-microvolt-L0 = <800000 800000 1000000>;
22562269 		};
22572270 		opp-594000000 {
22582271 			opp-hz = /bits/ 64 <594000000>;
....@@ -2364,8 +2377,9 @@
23642377 		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
23652378 		fifo-depth = <0x100>;
23662379 		max-frequency = <200000000>;
2367
-		pinctrl-names = "default";
2380
+		pinctrl-names = "normal", "idle";
23682381 		pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
2382
+		pinctrl-1 = <&sdmmc0_idle_pins &sdmmc0_det>;
23692383 		status = "disabled";
23702384 	};
23712385 
....@@ -2397,7 +2411,7 @@
23972411 		status = "disabled";
23982412 	};
23992413 
2400
-	sfc: sfc@ffc90000  {
2414
+	sfc: spi@ffc90000  {
24012415 		compatible = "rockchip,sfc";
24022416 		reg = <0xffc90000 0x4000>;
24032417 		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
....@@ -2408,6 +2422,8 @@
24082422 		assigned-clocks = <&cru SCLK_SFC>;
24092423 		assigned-clock-rates = <80000000>;
24102424 		power-domains = <&power RV1126_PD_NVM>;
2425
+		#address-cells = <1>;
2426
+		#size-cells = <0>;
24112427 		status = "disabled";
24122428 	};
24132429 
....@@ -2448,9 +2464,9 @@
24482464 			2	0
24492465 		>;
24502466 		rockchip,pvtm-voltage-sel = <
2451
-			0        112500   1
2452
-			112501   117500   2
2453
-			117501   999999   3
2467
+			0        108500   1
2468
+			108501   113500   2
2469
+			113501   999999   3
24542470 		>;
24552471 		rockchip,pvtm-freq = <396000>;
24562472 		rockchip,pvtm-volt = <800000>;
....@@ -2465,27 +2481,27 @@
24652481 		opp-200000000 {
24662482 			opp-hz = /bits/ 64 <200000000>;
24672483 			opp-microvolt = <750000 750000 1000000>;
2468
-			opp-microvolt-L0 = <800000 800000 1000000>;
2484
+			opp-microvolt-L0 = <775000 775000 1000000>;
24692485 		};
24702486 		opp-300000000 {
24712487 			opp-hz = /bits/ 64 <300000000>;
24722488 			opp-microvolt = <750000 750000 1000000>;
2473
-			opp-microvolt-L0 = <800000 800000 1000000>;
2489
+			opp-microvolt-L0 = <775000 775000 1000000>;
24742490 		};
24752491 		opp-396000000 {
24762492 			opp-hz = /bits/ 64 <396000000>;
24772493 			opp-microvolt = <750000 750000 1000000>;
2478
-			opp-microvolt-L0 = <800000 800000 1000000>;
2494
+			opp-microvolt-L0 = <775000 775000 1000000>;
24792495 		};
24802496 		opp-500000000 {
24812497 			opp-hz = /bits/ 64 <500000000>;
24822498 			opp-microvolt = <750000 750000 1000000>;
2483
-			opp-microvolt-L0 = <800000 800000 1000000>;
2499
+			opp-microvolt-L0 = <775000 775000 1000000>;
24842500 		};
24852501 		opp-600000000 {
24862502 			opp-hz = /bits/ 64 <600000000>;
24872503 			opp-microvolt = <750000 750000 1000000>;
2488
-			opp-microvolt-L0 = <800000 800000 1000000>;
2504
+			opp-microvolt-L0 = <775000 775000 1000000>;
24892505 		};
24902506 		opp-700000000 {
24912507 			opp-hz = /bits/ 64 <700000000>;
....@@ -2539,6 +2555,8 @@
25392555 			snps,tx-ipgap-linecheck-dis-quirk;
25402556 			snps,tx-fifo-resize;
25412557 			snps,xhci-trb-ent-quirk;
2558
+			snps,usb2-lpm-disable;
2559
+			snps,parkmode-disable-hs-quirk;
25422560 			status = "disabled";
25432561 		};
25442562 	};