| .. | .. |
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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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| 1 | 2 | /* |
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| 2 | 3 | * Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com) |
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| 3 | | - * |
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| 4 | | - * This program is free software; you can redistribute it and/or modify |
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| 5 | | - * it under the terms of the GNU General Public License version 2 as |
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| 6 | | - * published by the Free Software Foundation. |
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| 7 | 4 | */ |
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| 8 | 5 | /dts-v1/; |
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| 9 | 6 | |
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| .. | .. |
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| 12 | 9 | / { |
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| 13 | 10 | model = "snps,zebu_hs"; |
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| 14 | 11 | compatible = "snps,zebu_hs"; |
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| 15 | | - #address-cells = <1>; |
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| 16 | | - #size-cells = <1>; |
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| 12 | + #address-cells = <2>; |
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| 13 | + #size-cells = <2>; |
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| 17 | 14 | interrupt-parent = <&core_intc>; |
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| 18 | 15 | |
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| 19 | 16 | memory { |
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| 20 | 17 | device_type = "memory"; |
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| 21 | | - reg = <0x80000000 0x20000000>; /* 512 */ |
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| 18 | + /* CONFIG_LINUX_RAM_BASE needs to match low mem start */ |
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| 19 | + reg = <0x0 0x80000000 0x0 0x20000000 /* 512 MB low mem */ |
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| 20 | + 0x1 0x00000000 0x0 0x40000000>; /* 1 GB highmem */ |
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| 22 | 21 | }; |
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| 23 | 22 | |
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| 24 | 23 | chosen { |
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| .. | .. |
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| 34 | 33 | #address-cells = <1>; |
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| 35 | 34 | #size-cells = <1>; |
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| 36 | 35 | |
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| 37 | | - /* child and parent address space 1:1 mapped */ |
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| 38 | | - ranges; |
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| 36 | + /* only perip space at end of low mem accessible |
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| 37 | + bus addr, parent bus addr, size */ |
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| 38 | + ranges = <0x80000000 0x0 0x80000000 0x80000000>; |
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| 39 | 39 | |
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| 40 | 40 | core_clk: core_clk { |
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| 41 | 41 | #clock-cells = <0>; |
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| .. | .. |
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| 50 | 50 | }; |
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| 51 | 51 | |
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| 52 | 52 | uart0: serial@f0000000 { |
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| 53 | | - compatible = "ns8250"; |
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| 53 | + compatible = "ns16550a"; |
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| 54 | 54 | reg = <0xf0000000 0x2000>; |
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| 55 | 55 | interrupts = <24>; |
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| 56 | 56 | clock-frequency = <50000000>; |
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| .. | .. |
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| 65 | 65 | #interrupt-cells = <1>; |
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| 66 | 66 | interrupts = <20>; |
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| 67 | 67 | }; |
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| 68 | + |
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| 69 | + virtio0: virtio@f0100000 { |
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| 70 | + compatible = "virtio,mmio"; |
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| 71 | + reg = <0xf0100000 0x2000>; |
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| 72 | + interrupts = <31>; |
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| 73 | + }; |
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| 74 | + |
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| 75 | + virtio1: virtio@f0102000 { |
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| 76 | + compatible = "virtio,mmio"; |
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| 77 | + reg = <0xf0102000 0x2000>; |
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| 78 | + interrupts = <32>; |
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| 79 | + }; |
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| 80 | + |
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| 81 | + virtio2: virtio@f0104000 { |
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| 82 | + compatible = "virtio,mmio"; |
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| 83 | + reg = <0xf0104000 0x2000>; |
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| 84 | + interrupts = <33>; |
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| 85 | + }; |
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| 86 | + |
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| 87 | + virtio3: virtio@f0106000 { |
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| 88 | + compatible = "virtio,mmio"; |
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| 89 | + reg = <0xf0106000 0x2000>; |
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| 90 | + interrupts = <34>; |
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| 91 | + }; |
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| 92 | + |
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| 93 | + virtio4: virtio@f0108000 { |
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| 94 | + compatible = "virtio,mmio"; |
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| 95 | + reg = <0xf0108000 0x2000>; |
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| 96 | + interrupts = <35>; |
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| 97 | + }; |
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| 68 | 98 | }; |
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| 69 | 99 | }; |
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