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2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390 
 kernel/tools/arch/arm64/include/uapi/asm/kvm.h
....@@ -35,6 +35,7 @@
3535 #include <linux/psci.h>
3636 #include <linux/types.h>
3737 #include <asm/ptrace.h>
38
+#include <asm/sve_context.h>
3839 
3940 #define __KVM_HAVE_GUEST_DEBUG
4041 #define __KVM_HAVE_IRQ_LINE
....@@ -102,6 +103,9 @@
102103 #define KVM_ARM_VCPU_EL1_32BIT		1 /* CPU running a 32bit VM */
103104 #define KVM_ARM_VCPU_PSCI_0_2		2 /* CPU uses PSCI v0.2 */
104105 #define KVM_ARM_VCPU_PMU_V3		3 /* Support guest PMUv3 */
106
+#define KVM_ARM_VCPU_SVE		4 /* enable SVE for this CPU */
107
+#define KVM_ARM_VCPU_PTRAUTH_ADDRESS	5 /* VCPU uses address authentication */
108
+#define KVM_ARM_VCPU_PTRAUTH_GENERIC	6 /* VCPU uses generic authentication */
105109 
106110 struct kvm_vcpu_init {
107111 	__u32 target;
....@@ -155,13 +159,29 @@
155159 struct kvm_arch_memory_slot {
156160 };
157161 
162
+/*
163
+ * PMU filter structure. Describe a range of events with a particular
164
+ * action. To be used with KVM_ARM_VCPU_PMU_V3_FILTER.
165
+ */
166
+struct kvm_pmu_event_filter {
167
+	__u16	base_event;
168
+	__u16	nevents;
169
+
170
+#define KVM_PMU_EVENT_ALLOW	0
171
+#define KVM_PMU_EVENT_DENY	1
172
+
173
+	__u8	action;
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+	__u8	pad[3];
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+};
176
+
158177 /* for KVM_GET/SET_VCPU_EVENTS */
159178 struct kvm_vcpu_events {
160179 	struct {
161180 		__u8 serror_pending;
162181 		__u8 serror_has_esr;
182
+		__u8 ext_dabt_pending;
163183 		/* Align it to 8 bytes */
164
-		__u8 pad[6];
184
+		__u8 pad[5];
165185 		__u64 serror_esr;
166186 	} exception;
167187 	__u32 reserved[12];
....@@ -215,16 +235,89 @@
215235 #define KVM_REG_ARM_PTIMER_CVAL		ARM64_SYS_REG(3, 3, 14, 2, 2)
216236 #define KVM_REG_ARM_PTIMER_CNT		ARM64_SYS_REG(3, 3, 14, 0, 1)
217237 
218
-/* EL0 Virtual Timer Registers */
238
+/*
239
+ * EL0 Virtual Timer Registers
240
+ *
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+ * WARNING:
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+ *      KVM_REG_ARM_TIMER_CVAL and KVM_REG_ARM_TIMER_CNT are not defined
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+ *      with the appropriate register encodings.  Their values have been
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+ *      accidentally swapped.  As this is set API, the definitions here
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+ *      must be used, rather than ones derived from the encodings.
246
+ */
219247 #define KVM_REG_ARM_TIMER_CTL		ARM64_SYS_REG(3, 3, 14, 3, 1)
220
-#define KVM_REG_ARM_TIMER_CNT		ARM64_SYS_REG(3, 3, 14, 3, 2)
221248 #define KVM_REG_ARM_TIMER_CVAL		ARM64_SYS_REG(3, 3, 14, 0, 2)
249
+#define KVM_REG_ARM_TIMER_CNT		ARM64_SYS_REG(3, 3, 14, 3, 2)
222250 
223251 /* KVM-as-firmware specific pseudo-registers */
224252 #define KVM_REG_ARM_FW			(0x0014 << KVM_REG_ARM_COPROC_SHIFT)
225253 #define KVM_REG_ARM_FW_REG(r)		(KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
226254 					 KVM_REG_ARM_FW | ((r) & 0xffff))
227255 #define KVM_REG_ARM_PSCI_VERSION	KVM_REG_ARM_FW_REG(0)
256
+#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1	KVM_REG_ARM_FW_REG(1)
257
+#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL		0
258
+#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_AVAIL		1
259
+#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_REQUIRED	2
260
+
261
+/*
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+ * Only two states can be presented by the host kernel:
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+ * - NOT_REQUIRED: the guest doesn't need to do anything
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+ * - NOT_AVAIL: the guest isn't mitigated (it can still use SSBS if available)
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+ *
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+ * All the other values are deprecated. The host still accepts all
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+ * values (they are ABI), but will narrow them to the above two.
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+ */
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+#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2	KVM_REG_ARM_FW_REG(2)
270
+#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL		0
271
+#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_UNKNOWN		1
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+#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_AVAIL		2
273
+#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED	3
274
+#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED     	(1U << 4)
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+
276
+/* SVE registers */
277
+#define KVM_REG_ARM64_SVE		(0x15 << KVM_REG_ARM_COPROC_SHIFT)
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+
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+/* Z- and P-regs occupy blocks at the following offsets within this range: */
280
+#define KVM_REG_ARM64_SVE_ZREG_BASE	0
281
+#define KVM_REG_ARM64_SVE_PREG_BASE	0x400
282
+#define KVM_REG_ARM64_SVE_FFR_BASE	0x600
283
+
284
+#define KVM_ARM64_SVE_NUM_ZREGS		__SVE_NUM_ZREGS
285
+#define KVM_ARM64_SVE_NUM_PREGS		__SVE_NUM_PREGS
286
+
287
+#define KVM_ARM64_SVE_MAX_SLICES	32
288
+
289
+#define KVM_REG_ARM64_SVE_ZREG(n, i)					\
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+	(KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_ZREG_BASE | \
291
+	 KVM_REG_SIZE_U2048 |						\
292
+	 (((n) & (KVM_ARM64_SVE_NUM_ZREGS - 1)) << 5) |			\
293
+	 ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))
294
+
295
+#define KVM_REG_ARM64_SVE_PREG(n, i)					\
296
+	(KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_PREG_BASE | \
297
+	 KVM_REG_SIZE_U256 |						\
298
+	 (((n) & (KVM_ARM64_SVE_NUM_PREGS - 1)) << 5) |			\
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+	 ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))
300
+
301
+#define KVM_REG_ARM64_SVE_FFR(i)					\
302
+	(KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_FFR_BASE | \
303
+	 KVM_REG_SIZE_U256 |						\
304
+	 ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))
305
+
306
+/*
307
+ * Register values for KVM_REG_ARM64_SVE_ZREG(), KVM_REG_ARM64_SVE_PREG() and
308
+ * KVM_REG_ARM64_SVE_FFR() are represented in memory in an endianness-
309
+ * invariant layout which differs from the layout used for the FPSIMD
310
+ * V-registers on big-endian systems: see sigcontext.h for more explanation.
311
+ */
312
+
313
+#define KVM_ARM64_SVE_VQ_MIN __SVE_VQ_MIN
314
+#define KVM_ARM64_SVE_VQ_MAX __SVE_VQ_MAX
315
+
316
+/* Vector lengths pseudo-register: */
317
+#define KVM_REG_ARM64_SVE_VLS		(KVM_REG_ARM64 | KVM_REG_ARM64_SVE | \
318
+					 KVM_REG_SIZE_U512 | 0xffff)
319
+#define KVM_ARM64_SVE_VLS_WORDS	\
320
+	((KVM_ARM64_SVE_VQ_MAX - KVM_ARM64_SVE_VQ_MIN) / 64 + 1)
228321 
229322 /* Device Control API: ARM VGIC */
230323 #define KVM_DEV_ARM_VGIC_GRP_ADDR	0
....@@ -260,13 +353,18 @@
260353 #define KVM_ARM_VCPU_PMU_V3_CTRL	0
261354 #define   KVM_ARM_VCPU_PMU_V3_IRQ	0
262355 #define   KVM_ARM_VCPU_PMU_V3_INIT	1
356
+#define   KVM_ARM_VCPU_PMU_V3_FILTER	2
263357 #define KVM_ARM_VCPU_TIMER_CTRL		1
264358 #define   KVM_ARM_VCPU_TIMER_IRQ_VTIMER		0
265359 #define   KVM_ARM_VCPU_TIMER_IRQ_PTIMER		1
360
+#define KVM_ARM_VCPU_PVTIME_CTRL	2
361
+#define   KVM_ARM_VCPU_PVTIME_IPA	0
266362 
267363 /* KVM_IRQ_LINE irq field index values */
364
+#define KVM_ARM_IRQ_VCPU2_SHIFT		28
365
+#define KVM_ARM_IRQ_VCPU2_MASK		0xf
268366 #define KVM_ARM_IRQ_TYPE_SHIFT		24
269
-#define KVM_ARM_IRQ_TYPE_MASK		0xff
367
+#define KVM_ARM_IRQ_TYPE_MASK		0xf
270368 #define KVM_ARM_IRQ_VCPU_SHIFT		16
271369 #define KVM_ARM_IRQ_VCPU_MASK		0xff
272370 #define KVM_ARM_IRQ_NUM_SHIFT		0