forked from ~ljy/RK356X_SDK_RELEASE

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hc
2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390 
 kernel/sound/soc/codecs/rk3308_codec.h
....@@ -27,7 +27,8 @@
2727 #define ACODEC_ADC_I2S_CTL1			0x08 /* REG 0x02 */
2828 #define ACODEC_ADC_BIST_MODE_SEL		0x0c /* REG 0x03 */
2929 #define ACODEC_ADC_HPF_PATH			0x10 /* REG 0x04 */
30
-/* Resevred REG 0x05 ~ 0x06 */
30
+#define ACODEC_S_ADC_DIG_VOL_CON_L		0x14 /* REG 0x05 */
31
+#define ACODEC_S_ADC_DIG_VOL_CON_R		0x18 /* REG 0x06 */
3132 #define ACODEC_ADC_DATA_PATH			0x1c /* REG 0x07 */
3233 /* Resevred REG 0x08 ~ 0x0f */
3334 
....@@ -42,7 +43,8 @@
4243 #define ACODEC_ADC_PGA_AGC_L_LO_MIN		0x5c /* REG 0x17 */
4344 #define ACODEC_ADC_PGA_AGC_L_HI_MIN		0x60 /* REG 0x18 */
4445 #define ACODEC_ADC_PGA_AGC_L_CTL5		0x64 /* REG 0x19 */
45
-/* Resevred REG 0x1a ~ 0x1b */
46
+/* Resevred REG 0x1a */
47
+#define ACODEC_S_ADC_PEAK_DET_VALUE_DEC_RATE_L	0x6c /* REG 0x1b */
4648 #define ACODEC_ADC_AGC_L_RO_GAIN		0x70 /* REG 0x1c */
4749 
4850 /* REG 0x20 ~ 0x2c are used to configure AGC of Right channel (ALC2) */
....@@ -56,7 +58,8 @@
5658 #define ACODEC_ADC_PGA_AGC_R_LO_MIN		0x9c /* REG 0x27 */
5759 #define ACODEC_ADC_PGA_AGC_R_HI_MIN		0xa0 /* REG 0x28 */
5860 #define ACODEC_ADC_PGA_AGC_R_CTL5		0xa4 /* REG 0x29 */
59
-/* Resevred REG 0x2a ~ 0x2b */
61
+/* Resevred REG 0x2a */
62
+#define ACODEC_S_ADC_PEAK_DET_VALUE_DEC_RATE_R	0xac /* REG 0x2b */
6063 #define ACODEC_ADC_AGC_R_RO_GAIN		0xb0 /* REG 0x2c */
6164 
6265 /* DAC DIGITAL REGISTERS */
....@@ -65,12 +68,20 @@
6568 #define ACODEC_DAC_BIST_MODE_SEL		0x0c /* REG 0x03 */
6669 #define ACODEC_DAC_DIGITAL_GAIN			0x10 /* REG 0x04 */
6770 #define ACODEC_DAC_DATA_SEL			0x14 /* REG 0x05 */
68
-/* Resevred REG 0x06 ~ 0x09 */
71
+/* Resevred REG 0x06 ~ 0x08 */
6972 #define ACODEC_DAC_DATA_HI			0x28 /* REG 0x0a */
7073 #define ACODEC_DAC_DATA_LO			0x2c /* REG 0x0b */
71
-/* Resevred REG 0x0c */
72
-#define ACODEC_DAC_HPDET_DELAYTIME		0x34 /* REG 0x0d */
74
+
75
+#define ACODEC_DAC_HPDET_DELAYTIME_HI		0x30 /* REG 0x0c */
76
+#define ACODEC_DAC_HPDET_DELAYTIME_LO		0x34 /* REG 0x0d */
7377 #define ACODEC_DAC_HPDET_STATUS			0x38 /* REG 0x0e, Read-only */
78
+
79
+#define ACODEC_S_DAC_DATA_HI			0x24 /* REG 0x09 */
80
+#define ACODEC_S_DAC_DATA_LO			0x28 /* REG 0x0a */
81
+#define ACODEC_S_DAC_HPDET_DELAYTIME_HI		0x2c /* REG 0x0b */
82
+#define ACODEC_S_DAC_HPDET_DELAYTIME_LO		0x30 /* REG 0x0c */
83
+#define ACODEC_S_DAC_HPDET_STATUS		0x34 /* REG 0x0d, Read-only */
84
+
7485 /* Resevred REG 0x0f */
7586 
7687 /* ADC ANALOG REGISTERS */
....@@ -83,8 +94,8 @@
8394 #define ACODEC_ADC_ANA_CTL1			0x18 /* REG 0x06 */
8495 #define ACODEC_ADC_ANA_CTL2			0x1c /* REG 0x07 */
8596 #define ACODEC_ADC_ANA_CTL3			0x20 /* REG 0x08 */
86
-/* Resevred REG 0x09 */
87
-#define ACODEC_ADC_ANA_CTL4			0x28 /* REG 0x0a */
97
+#define ACODEC_S_ADC_ANA_CTL4			0x24 /* REG 0x09 */
98
+#define ACODEC_ADC_ANA_CTL5			0x28 /* REG 0x0a */
8899 #define ACODEC_ADC_ANA_ALC_PGA			0x2c /* REG 0x0b */
89100 /* Resevred REG 0x0c ~ 0x0f */
90101 
....@@ -126,7 +137,9 @@
126137 #define RK3308_ADC_DIG_CON02(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_I2S_CTL1)
127138 #define RK3308_ADC_DIG_CON03(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_BIST_MODE_SEL)
128139 #define RK3308_ADC_DIG_CON04(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_HPF_PATH)
129
-#define RK3308_ADC_DIG_CON07(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_DATA_PATH)
140
+#define RK3308BS_ADC_DIG_CON05(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_S_ADC_DIG_VOL_CON_L)
141
+#define RK3308BS_ADC_DIG_CON06(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_S_ADC_DIG_VOL_CON_R)
142
+#define RK3308_ADC_DIG_CON07(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_DATA_PATH) /* Removed from S */
130143 
131144 #define RK3308_ALC_L_DIG_CON00(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_CTL0)
132145 #define RK3308_ALC_L_DIG_CON01(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_CTL1)
....@@ -138,6 +151,7 @@
138151 #define RK3308_ALC_L_DIG_CON07(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_LO_MIN)
139152 #define RK3308_ALC_L_DIG_CON08(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_HI_MIN)
140153 #define RK3308_ALC_L_DIG_CON09(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_CTL5)
154
+#define RK3308BS_ALC_L_DIG_CON11(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_S_ADC_PEAK_DET_VALUE_DEC_RATE_L)
141155 #define RK3308_ALC_L_DIG_CON12(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_AGC_L_RO_GAIN)
142156 
143157 #define RK3308_ALC_R_DIG_CON00(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_CTL0)
....@@ -150,6 +164,7 @@
150164 #define RK3308_ALC_R_DIG_CON07(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_LO_MIN)
151165 #define RK3308_ALC_R_DIG_CON08(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_HI_MIN)
152166 #define RK3308_ALC_R_DIG_CON09(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_CTL5)
167
+#define RK3308BS_ALC_R_DIG_CON11(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_S_ADC_PEAK_DET_VALUE_DEC_RATE_R)
153168 #define RK3308_ALC_R_DIG_CON12(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_AGC_R_RO_GAIN)
154169 
155170 /* DAC DIGITAL REGISTERS */
....@@ -159,11 +174,25 @@
159174 #define RK3308_DAC_DIG_CON02			(RK3308_DAC_DIG_OFFSET + ACODEC_DAC_I2S_CTL1)
160175 #define RK3308_DAC_DIG_CON03			(RK3308_DAC_DIG_OFFSET + ACODEC_DAC_BIST_MODE_SEL)
161176 #define RK3308_DAC_DIG_CON04			(RK3308_DAC_DIG_OFFSET + ACODEC_DAC_DIGITAL_GAIN)
177
+#define RK3308BS_DAC_DIG_CON04			(RK3308_DAC_DIG_OFFSET + ACODEC_DAC_DIGITAL_GAIN)
162178 #define RK3308_DAC_DIG_CON05			(RK3308_DAC_DIG_OFFSET + ACODEC_DAC_DATA_SEL)
179
+#define RK3308BS_DAC_DIG_CON05			(RK3308_DAC_DIG_OFFSET + ACODEC_DAC_DATA_SEL)
180
+
163181 #define RK3308_DAC_DIG_CON10			(RK3308_DAC_DIG_OFFSET + ACODEC_DAC_DATA_HI)
164182 #define RK3308_DAC_DIG_CON11			(RK3308_DAC_DIG_OFFSET + ACODEC_DAC_DATA_LO)
165
-#define RK3308_DAC_DIG_CON13			(RK3308_DAC_DIG_OFFSET + ACODEC_DAC_HPDET_DELAYTIME)
183
+
184
+#define RK3308_DAC_DIG_CON12			(RK3308_DAC_DIG_OFFSET + ACODEC_DAC_HPDET_DELAYTIME_HI)
185
+#define RK3308_DAC_DIG_CON13			(RK3308_DAC_DIG_OFFSET + ACODEC_DAC_HPDET_DELAYTIME_LO)
166186 #define RK3308_DAC_DIG_CON14			(RK3308_DAC_DIG_OFFSET + ACODEC_DAC_HPDET_STATUS)
187
+
188
+#define RK3308BS_DAC_DIG_CON09			(RK3308_DAC_DIG_OFFSET + ACODEC_S_DAC_DATA_HI)
189
+#define RK3308BS_DAC_DIG_CON10			(RK3308_DAC_DIG_OFFSET + ACODEC_S_DAC_DATA_LO)
190
+#define RK3308BS_DAC_DIG_CON11			(RK3308_DAC_DIG_OFFSET + ACODEC_S_DAC_DELAY_TIME_DET_HI)
191
+#define RK3308BS_DAC_DIG_CON12			(RK3308_DAC_DIG_OFFSET + ACODEC_S_DAC_DELAY_TIME_DET_LO)
192
+#define RK3308BS_DAC_DIG_CON13			(RK3308_DAC_DIG_OFFSET + ACODEC_S_DAC_HPDET_STATUS)
193
+
194
+#define RK3308_CODEC_HEADPHONE_CON		RK3308_DAC_DIG_CON14
195
+#define RK3308BS_CODEC_HEADPHONE_CON		RK3308BS_DAC_DIG_CON13
167196 
168197 /* ADC ANALOG REGISTERS */
169198 /*
....@@ -174,7 +203,7 @@
174203  * CH2: left_2(ADC5) and right_2(ADC6)
175204  * CH3: left_3(ADC7) and right_3(ADC8)
176205  */
177
-#define RK3308_ADC_ANA_OFFSET(ch)		((ch & 0x3) * 0x40 + 0x340)
206
+#define RK3308_ADC_ANA_OFFSET(ch)		(((ch) & 0x3) * 0x40 + 0x340)
178207 
179208 #define RK3308_ADC_ANA_CON00(ch)		(RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_MIC_CTL)
180209 #define RK3308_ADC_ANA_CON01(ch)		(RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_MIC_GAIN)
....@@ -185,7 +214,8 @@
185214 #define RK3308_ADC_ANA_CON06(ch)		(RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_CTL1)
186215 #define RK3308_ADC_ANA_CON07(ch)		(RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_CTL2)
187216 #define RK3308_ADC_ANA_CON08(ch)		(RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_CTL3)
188
-#define RK3308_ADC_ANA_CON10(ch)		(RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_CTL4)
217
+#define RK3308BS_ADC_ANA_CON09(ch)		(RK3308_ADC_ANA_OFFSET(ch) + ACODEC_S_ADC_ANA_CTL4)
218
+#define RK3308_ADC_ANA_CON10(ch)		(RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_CTL5)
189219 #define RK3308_ADC_ANA_CON11(ch)		(RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_ALC_PGA)
190220 
191221 /* DAC ANALOG REGISTERS */
....@@ -249,6 +279,11 @@
249279 #define RK3308_ADC_I2S_TYPE_MSK			(1 << 0)
250280 #define RK3308_ADC_I2S_MONO			(1 << 0)
251281 #define RK3308_ADC_I2S_STEREO			(0 << 0)
282
+#define RK3308BS_ADC_I2S_SWAP_SFT		0
283
+#define RK3308BS_ADC_I2S_LR			(0 << RK3308BS_ADC_I2S_SWAP_SFT)
284
+#define RK3308BS_ADC_I2S_LL			(1 << RK3308BS_ADC_I2S_SWAP_SFT)
285
+#define RK3308BS_ADC_I2S_RR			(2 << RK3308BS_ADC_I2S_SWAP_SFT)
286
+#define RK3308BS_ADC_I2S_RL			(3 << RK3308BS_ADC_I2S_SWAP_SFT)
252287 
253288 /* RK3308_ADC_DIG_CON02 - REG: 0x0008 */
254289 #define RK3308_ADC_IO_MODE_MSK			(1 << 5)
....@@ -295,11 +330,19 @@
295330 #define RK3308_ADC_HPF_CUTOFF_245HZ		(0x1 << RK3308_ADC_HPF_CUTOFF_SFT)
296331 #define RK3308_ADC_HPF_CUTOFF_20HZ		(0x0 << RK3308_ADC_HPF_CUTOFF_SFT)
297332 
333
+/* RK3308BS_ADC_DIG_CON05 - REG: 0x0014 */
334
+#define RK3308_ADC_DIG_VOL_CON_L_MSK		0xff
335
+#define RK3308_ADC_DIG_VOL_CON_L(x)		((x) & RK3308_ADC_DIG_VOL_CON_L_MSK)
336
+/* RK3308BS_ADC_DIG_CON06 - REG: 0x0018 */
337
+#define RK3308_ADC_DIG_VOL_CON_R_MSK		0xff
338
+#define RK3308_ADC_DIG_VOL_CON_R(x)		((x) & RK3308_ADC_DIG_VOL_CON_R_MSK)
339
+#define RK3308_ADC_DIG_VOL_0DB			0xc2
340
+
298341 /* RK3308_ADC_DIG_CON07 - REG: 0x001c */
299342 #define RK3308_ADCL_DATA_SFT			4
300
-#define RK3308_ADCL_DATA(x)			(x << RK3308_ADCL_DATA_SFT)
343
+#define RK3308_ADCL_DATA(x)			((x) << RK3308_ADCL_DATA_SFT)
301344 #define RK3308_ADCR_DATA_SFT			2
302
-#define RK3308_ADCR_DATA(x)			(x << RK3308_ADCR_DATA_SFT)
345
+#define RK3308_ADCR_DATA(x)			((x) << RK3308_ADCR_DATA_SFT)
303346 #define RK3308_ADCL_DATA_SEL_ADCL		(0x1 << 1)
304347 #define RK3308_ADCL_DATA_SEL_NORMAL		(0x0 << 1)
305348 #define RK3308_ADCR_DATA_SEL_ADCR		(0x1 << 0)
....@@ -533,10 +576,32 @@
533576 #define RK3308_AGC_MIN_GAIN_PGA_NDB_18		(0x0 << RK3308_AGC_MIN_GAIN_PGA_SFT)
534577 
535578 /*
536
- * RK3308_ALC_L_DIG_CON12 - REG: 0x0068 + ch * 0xc0
537
- * RK3308_ALC_R_DIG_CON12 - REG: 0x00a8 + ch * 0xc0
579
+ * RK3308BS_ALC_L_DIG_CON11 - REG: 0x006c + ch * 0xc0
580
+ * RK3308BS_ALC_R_DIG_CON11 - REG: 0x00ac + ch * 0xc0
581
+ */
582
+#define ACODEC_S_ADC_PEAK_DET_VALUE_DEC_RATE(x)	((x) & 0x1f)
583
+
584
+/*
585
+ * RK3308_ALC_L_DIG_CON12 - REG: 0x0070 + ch * 0xc0
586
+ * RK3308_ALC_R_DIG_CON12 - REG: 0x00b0 + ch * 0xc0
538587  */
539588 #define RK3308_AGC_GAIN_MSK			0x1f
589
+
590
+/*
591
+ * RK3308BS_ALC_L_DIG_CON12 - REG: 0x0070 + ch * 0xc0
592
+ * RK3308BS_ALC_R_DIG_CON12 - REG: 0x00b0 + ch * 0xc0
593
+ */
594
+
595
+/*
596
+ * RK3308BS_ALC_L_DIG_CON13 - REG: 0x0074 + ch * 0xc0
597
+ * RK3308BS_ALC_R_DIG_CON13 - REG: 0x00b4 + ch * 0xc0
598
+ */
599
+
600
+/*
601
+ * RK3308BS_ALC_L_DIG_CON14 - REG: 0x0078 + ch * 0xc0
602
+ * RK3308BS_ALC_R_DIG_CON14 - REG: 0x00b8 + ch * 0xc0
603
+ */
604
+#define RK3308BS_AGC_GAIN_MSK			0x1f
540605 
541606 /* RK3308_DAC_DIG_CON01 - REG: 0x0304 */
542607 #define RK3308_DAC_I2S_LRC_POL_MSK		(0x1 << 7)
....@@ -557,8 +622,17 @@
557622 #define RK3308_DAC_I2S_LR_MSK			(0x1 << 2)
558623 #define RK3308_DAC_I2S_LR_SWAP			(0x1 << 2)
559624 #define RK3308_DAC_I2S_LR_NORMAL		(0x0 << 2)
625
+#define RK3308BS_DAC_I2S_BYPASS_MSK		(0x1 << 1)
626
+#define RK3308BS_DAC_I2S_BYPASS_EN		(0x1 << 1)
627
+#define RK3308BS_DAC_I2S_BYPASS_DIS		(0x0 << 1)
560628 
561629 /* RK3308_DAC_DIG_CON02 - REG: 0x0308 */
630
+#define RK3308BS_DAC_IO_MODE_MSK		(0x1 << 7)
631
+#define RK3308BS_DAC_IO_MODE_MASTER		(0x1 << 7)
632
+#define RK3308BS_DAC_IO_MODE_SLAVE		(0x0 << 7)
633
+#define RK3308BS_DAC_MODE_MSK			(0x1 << 6)
634
+#define RK3308BS_DAC_MODE_MASTER		(0x1 << 6)
635
+#define RK3308BS_DAC_MODE_SLAVE			(0x0 << 6)
562636 #define RK3308_DAC_IO_MODE_MSK			(0x1 << 5)
563637 #define RK3308_DAC_IO_MODE_MASTER		(0x1 << 5)
564638 #define RK3308_DAC_IO_MODE_SLAVE		(0x0 << 5)
....@@ -604,17 +678,41 @@
604678 #define RK3308_DAC_CIC_IF_GAIN_SFT		0
605679 #define RK3308_DAC_CIC_IF_GAIN_MSK		(0x7 << RK3308_DAC_CIC_IF_GAIN_SFT)
606680 
681
+/* RK3308BS_DAC_DIG_CON04 - REG: 0x0310 */
682
+#define RK3308BS_DAC_DIG_GAIN_SFT		0
683
+#define RK3308BS_DAC_DIG_GAIN_MSK		(0xff << RK3308BS_DAC_DIG_GAIN_SFT)
684
+#define RK3308BS_DAC_DIG_GAIN(x)		((x) & RK3308BS_DAC_DIG_GAIN_MSK)
685
+#define RK3308BS_DAC_DIG_0DB			0xed
686
+
607687 /* RK3308_DAC_DIG_CON05 - REG: 0x0314 */
608
-#define RK3308_DAC_L_REG_CTL_INDATA		(0x1 << 2)
609
-#define RK3308_DAC_L_NORMAL_DATA		(0x0 << 2)
610
-#define RK3308_DAC_R_REG_CTL_INDATA		(0x1 << 1)
611
-#define RK3308_DAC_R_NORMAL_DATA		(0x0 << 1)
688
+#define RK3308_DAC_L_DATA_SEL_INPUT		(0x1 << 2)
689
+#define RK3308_DAC_L_DATA_SEL_NORMAL		(0x0 << 2)
690
+#define RK3308_DAC_R_DATA_SEL_INPUT		(0x1 << 1)
691
+#define RK3308_DAC_R_DATA_SEL_NORMAL		(0x0 << 1)
692
+
693
+/* RK3308BS_DAC_DIG_CON05 - REG: 0x0314 */
694
+#define RK3308BS_DAC_L_DATA_SEL_MUTE		(0x1 << 2)
695
+#define RK3308BS_DAC_L_DATA_SEL_NORMAL		(0x0 << 2)
696
+#define RK3308BS_DAC_R_DATA_SEL_MUTE		(0x1 << 1)
697
+#define RK3308BS_DAC_R_DATA_SEL_NORMAL		(0x0 << 1)
612698 
613699 /* RK3308_DAC_DIG_CON10 - REG: 0x0328 */
614
-#define RK3308_DAC_DATA_HI4(x)			(x & 0xf) /* Need to RK3308_DAC_x_REG_CTL_INDATA */
700
+#define RK3308_DAC_DATA_HI4(x)			((x) & 0xf) /* Need to RK3308_DAC_x_REG_CTL_INDATA */
615701 
616702 /* RK3308_DAC_DIG_CON11 - REG: 0x032c */
617
-#define RK3308_DAC_DATA_LO8(x)			(x & 0xff) /* Need to RK3308_DAC_x_REG_CTL_INDATA */
703
+#define RK3308_DAC_DATA_LO8(x)			((x) & 0xff) /* Need to RK3308_DAC_x_REG_CTL_INDATA */
704
+
705
+/* RK3308BS_DAC_DIG_CON09 - REG: 0x0324 */
706
+#define RK3308BS_DAC_DATA_HI4(x)		((x) & 0xf) /* Need to RK3308_DAC_x_REG_CTL_INDATA */
707
+
708
+/* RK3308BS_DAC_DIG_CON10 - REG: 0x0328 */
709
+#define RK3308BS_DAC_DATA_LO8(x)		((x) & 0xff) /* Need to RK3308_DAC_x_REG_CTL_INDATA */
710
+
711
+/* RK3308BS_DAC_DIG_CON11 - REG: 0x032c */
712
+#define RK3308BS_DAC_DELAY_TIME_DETECT_HI2(x)	((x) & 0x3)
713
+
714
+/* RK3308BS_DAC_DIG_CON12 - REG: 0x0330 */
715
+#define RK3308BS_DAC_DELAY_TIME_DETECT_LO8(x)	((x) & 0xff)
618716 
619717 /* RK3308_ADC_ANA_CON00 - REG: 0x0340 */
620718 #define RK3308_ADC_CH1_CH2_MIC_ALL_MSK		(0xff << 0)
....@@ -816,6 +914,12 @@
816914 #define RK3308_ADC_MICBIAS_CURRENT_MSK		(0x1 << 4)
817915 #define RK3308_ADC_MICBIAS_CURRENT_EN		(0x1 << 4)
818916 #define RK3308_ADC_MICBIAS_CURRENT_DIS		(0x0 << 4)
917
+#define RK3308BS_ADC_MICBIAS_CURRENT_SEL(x)	((x) & 0xf)
918
+
919
+/* RK3308BS_ADC_ANA_CON09 - REG: 0x0364 */
920
+#define RK3308BS_ADC_MICBIAS_OPA_VBIAS(x)	(((x) & 0x7) << 4)
921
+#define RK3308BS_ADC_VCM_SETUP_MIN_CURRENT_EN	(0x0 << 1)
922
+#define RK3308BS_ADC_VCM_SETUP_MIN_CURRENT_DIS	(0x0 << 0)
819923 
820924 /* RK3308_ADC_ANA_CON10 - REG: 0x0368 */
821925 #define RK3308_ADC_REF_EN			(0x1 << 7)
....@@ -826,7 +930,7 @@
826930  * 1: Choose the current I
827931  * 0: Don't choose the current I
828932  */
829
-#define RK3308_ADC_SEL_I(x)			(x & 0x7f)
933
+#define RK3308_ADC_SEL_I(x)			((x) & 0x7f)
830934 
831935 /* RK3308_ADC_ANA_CON11 - REG: 0x036c */
832936 #define RK3308_ADC_ALCR_CON_GAIN_PGAR_MSK	(0x1 << 1)
....@@ -837,6 +941,9 @@
837941 #define RK3308_ADC_ALCL_CON_GAIN_PGAL_DIS	(0x0 << 0)
838942 
839943 /* RK3308_DAC_ANA_CON00 - REG: 0x0440 */
944
+#define RK3308_DAC_CURRENT_SEL_SFT		4
945
+#define RK3308_DAC_CURRENT_SEL_MSK		(0xf << RK3308_DAC_CURRENT_SEL_SFT)
946
+#define RK3308_DAC_CURRENT_SEL(x)		((x) & RK3308_DAC_CURRENT_SEL_MSK)
840947 #define RK3308_DAC_HEADPHONE_DET_MSK		(0x1 << 1)
841948 #define RK3308_DAC_HEADPHONE_DET_EN		(0x1 << 1)
842949 #define RK3308_DAC_HEADPHONE_DET_DIS		(0x0 << 1)
....@@ -852,6 +959,7 @@
852959 #define RK3308_DAC_HPOUT_POP_SOUND_R_MSK	(0x3 << RK3308_DAC_HPOUT_POP_SOUND_R_SFT)
853960 #define RK3308_DAC_HPOUT_POP_SOUND_R_WORK	(0x2 << RK3308_DAC_HPOUT_POP_SOUND_R_SFT)
854961 #define RK3308_DAC_HPOUT_POP_SOUND_R_INIT	(0x1 << RK3308_DAC_HPOUT_POP_SOUND_R_SFT)
962
+#define RK3308_DAC_HPOUT_POP_SOUND_R_DIS	(0x0 << RK3308_DAC_HPOUT_POP_SOUND_R_SFT)
855963 #define RK3308_DAC_BUF_REF_L_MSK		(0x1 << 2)
856964 #define RK3308_DAC_BUF_REF_L_EN			(0x1 << 2)
857965 #define RK3308_DAC_BUF_REF_L_DIS		(0x0 << 2)
....@@ -859,6 +967,7 @@
859967 #define RK3308_DAC_HPOUT_POP_SOUND_L_MSK	(0x3 << RK3308_DAC_HPOUT_POP_SOUND_L_SFT)
860968 #define RK3308_DAC_HPOUT_POP_SOUND_L_WORK	(0x2 << RK3308_DAC_HPOUT_POP_SOUND_L_SFT)
861969 #define RK3308_DAC_HPOUT_POP_SOUND_L_INIT	(0x1 << RK3308_DAC_HPOUT_POP_SOUND_L_SFT)
970
+#define RK3308_DAC_HPOUT_POP_SOUND_L_DIS	(0x0 << RK3308_DAC_HPOUT_POP_SOUND_L_SFT)
862971 
863972 /* RK3308_DAC_ANA_CON02 - REG: 0x0448 */
864973 #define RK3308_DAC_R_DAC_WORK			(0x1 << 7)
....@@ -991,14 +1100,18 @@
9911100 /* RK3308_DAC_ANA_CON07 - REG: 0x045c */
9921101 #define RK3308_DAC_R_HPOUT_DRV_SFT		4
9931102 #define RK3308_DAC_R_HPOUT_DRV_MSK		(0xf << RK3308_DAC_R_HPOUT_DRV_SFT)
1103
+#define RK3308_DAC_R_HPOUT_DRV(x)		(((x) << RK3308_DAC_R_HPOUT_DRV_SFT) & RK3308_DAC_R_HPOUT_DRV_MSK)
9941104 #define RK3308_DAC_L_HPOUT_DRV_SFT		0
9951105 #define RK3308_DAC_L_HPOUT_DRV_MSK		(0xf << RK3308_DAC_L_HPOUT_DRV_SFT)
1106
+#define RK3308_DAC_L_HPOUT_DRV(x)		(((x) << RK3308_DAC_L_HPOUT_DRV_SFT) & RK3308_DAC_L_HPOUT_DRV_MSK)
9961107 
9971108 /* RK3308_DAC_ANA_CON08 - REG: 0x0460 */
9981109 #define RK3308_DAC_R_LINEOUT_DRV_SFT		4
9991110 #define RK3308_DAC_R_LINEOUT_DRV_MSK		(0xf << RK3308_DAC_R_LINEOUT_DRV_SFT)
1111
+#define RK3308_DAC_R_LINEOUT_DRV(x)		(((x) << RK3308_DAC_R_LINEOUT_DRV_SFT) & RK3308_DAC_R_LINEOUT_DRV_MSK)
10001112 #define RK3308_DAC_L_LINEOUT_DRV_SFT		0
10011113 #define RK3308_DAC_L_LINEOUT_DRV_MSK		(0xf << RK3308_DAC_L_LINEOUT_DRV_SFT)
1114
+#define RK3308_DAC_L_LINEOUT_DRV(x)		(((x) << RK3308_DAC_L_LINEOUT_DRV_SFT) & RK3308_DAC_L_LINEOUT_DRV_MSK)
10021115 
10031116 /* RK3308_DAC_ANA_CON12 - REG: 0x0470 */
10041117 #define RK3308_DAC_R_HPMIX_SEL_SFT		6
....@@ -1050,7 +1163,7 @@
10501163  * 1: Choose the current I
10511164  * 0: Don't choose the current I
10521165  */
1053
-#define RK3308_DAC_SEL_I(x)			(x & 0xf)
1166
+#define RK3308_DAC_SEL_I(x)			((x) & 0xf)
10541167 
10551168 /* RK3308_DAC_ANA_CON15 - REG: 0x047C */
10561169 #define RK3308_DAC_LINEOUT_POP_SOUND_R_SFT	4