change wifi driver to cypress

hc

2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390

 kernel/include/uapi/drm/v3d_drm.h
..
..
@@ -36,6 +36,8 @@
36
36
 #define DRM_V3D_MMAP_BO                           0x03
37
37
 #define DRM_V3D_GET_PARAM                         0x04
38
38
 #define DRM_V3D_GET_BO_OFFSET                     0x05
39
+#define DRM_V3D_SUBMIT_TFU                        0x06
40
+#define DRM_V3D_SUBMIT_CSD                        0x07
39
41
 
40
42
 #define DRM_IOCTL_V3D_SUBMIT_CL           DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)
41
43
 #define DRM_IOCTL_V3D_WAIT_BO             DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)
..
..
@@ -43,6 +45,10 @@
43
45
 #define DRM_IOCTL_V3D_MMAP_BO             DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_MMAP_BO, struct drm_v3d_mmap_bo)
44
46
 #define DRM_IOCTL_V3D_GET_PARAM           DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_PARAM, struct drm_v3d_get_param)
45
47
 #define DRM_IOCTL_V3D_GET_BO_OFFSET       DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset)
48
+#define DRM_IOCTL_V3D_SUBMIT_TFU          DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu)
49
+#define DRM_IOCTL_V3D_SUBMIT_CSD          DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CSD, struct drm_v3d_submit_csd)
50
+
51
+#define DRM_V3D_SUBMIT_CL_FLUSH_CACHE             0x01
46
52
 
47
53
 /**
48
54
  * struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D
..
..
@@ -50,6 +56,14 @@
50
56
  *
51
57
  * This asks the kernel to have the GPU execute an optional binner
52
58
  * command list, and a render command list.
59
+ *
60
+ * The L1T, slice, L2C, L2T, and GCA caches will be flushed before
61
+ * each CL executes.  The VCD cache should be flushed (if necessary)
62
+ * by the submitted CLs.  The TLB writes are guaranteed to have been
63
+ * flushed by the time the render done IRQ happens, which is the
64
+ * trigger for out_sync.  Any dirtying of cachelines by the job (only
65
+ * possible using TMU writes) must be flushed by the caller using the
66
+ * DRM_V3D_SUBMIT_CL_FLUSH_CACHE_FLAG flag.
53
67
  */
54
68
 struct drm_v3d_submit_cl {
55
69
 	/* Pointer to the binner command list.
..
..
@@ -58,10 +72,15 @@
58
72
 	 * coordinate shader to determine where primitives land on the screen,
59
73
 	 * then writes out the state updates and draw calls necessary per tile
60
74
 	 * to the tile allocation BO.
75
+	 *
76
+	 * This BCL will block on any previous BCL submitted on the
77
+	 * same FD, but not on any RCL or BCLs submitted by other
78
+	 * clients -- that is left up to the submitter to control
79
+	 * using in_sync_bcl if necessary.
61
80
 	 */
62
81
 	__u32 bcl_start;
63
82
 
64
-	 /** End address of the BCL (first byte after the BCL) */
83
+	/** End address of the BCL (first byte after the BCL) */
65
84
 	__u32 bcl_end;
66
85
 
67
86
 	/* Offset of the render command list.
..
..
@@ -69,10 +88,15 @@
69
88
 	 * This is the second set of commands executed, which will either
70
89
 	 * execute the tiles that have been set up by the BCL, or a fixed set
71
90
 	 * of tiles (in the case of RCL-only blits).
91
+	 *
92
+	 * This RCL will block on this submit's BCL, and any previous
93
+	 * RCL submitted on the same FD, but not on any RCL or BCLs
94
+	 * submitted by other clients -- that is left up to the
95
+	 * submitter to control using in_sync_rcl if necessary.
72
96
 	 */
73
97
 	__u32 rcl_start;
74
98
 
75
-	 /** End address of the RCL (first byte after the RCL) */
99
+	/** End address of the RCL (first byte after the RCL) */
76
100
 	__u32 rcl_end;
77
101
 
78
102
 	/** An optional sync object to wait on before starting the BCL. */
..
..
@@ -102,8 +126,7 @@
102
126
 	/* Number of BO handles passed in (size is that times 4). */
103
127
 	__u32 bo_handle_count;
104
128
 
105
-	/* Pad, must be zero-filled. */
106
-	__u32 pad;
129
+	__u32 flags;
107
130
 };
108
131
 
109
132
 /**
..
..
@@ -169,6 +192,9 @@
169
192
 	DRM_V3D_PARAM_V3D_CORE0_IDENT0,
170
193
 	DRM_V3D_PARAM_V3D_CORE0_IDENT1,
171
194
 	DRM_V3D_PARAM_V3D_CORE0_IDENT2,
195
+	DRM_V3D_PARAM_SUPPORTS_TFU,
196
+	DRM_V3D_PARAM_SUPPORTS_CSD,
197
+	DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH,
172
198
 };
173
199
 
174
200
 struct drm_v3d_get_param {
..
..
@@ -187,6 +213,53 @@
187
213
 	__u32 offset;
188
214
 };
189
215
 
216
+struct drm_v3d_submit_tfu {
217
+	__u32 icfg;
218
+	__u32 iia;
219
+	__u32 iis;
220
+	__u32 ica;
221
+	__u32 iua;
222
+	__u32 ioa;
223
+	__u32 ios;
224
+	__u32 coef[4];
225
+	/* First handle is the output BO, following are other inputs.
226
+	 * 0 for unused.
227
+	 */
228
+	__u32 bo_handles[4];
229
+	/* sync object to block on before running the TFU job.  Each TFU
230
+	 * job will execute in the order submitted to its FD.  Synchronization
231
+	 * against rendering jobs requires using sync objects.
232
+	 */
233
+	__u32 in_sync;
234
+	/* Sync object to signal when the TFU job is done. */
235
+	__u32 out_sync;
236
+};
237
+
238
+/* Submits a compute shader for dispatch.  This job will block on any
239
+ * previous compute shaders submitted on this fd, and any other
240
+ * synchronization must be performed with in_sync/out_sync.
241
+ */
242
+struct drm_v3d_submit_csd {
243
+	__u32 cfg[7];
244
+	__u32 coef[4];
245
+
246
+	/* Pointer to a u32 array of the BOs that are referenced by the job.
247
+	 */
248
+	__u64 bo_handles;
249
+
250
+	/* Number of BO handles passed in (size is that times 4). */
251
+	__u32 bo_handle_count;
252
+
253
+	/* sync object to block on before running the CSD job.  Each
254
+	 * CSD job will execute in the order submitted to its FD.
255
+	 * Synchronization against rendering/TFU jobs or CSD from
256
+	 * other fds requires using sync objects.
257
+	 */
258
+	__u32 in_sync;
259
+	/* Sync object to signal when the CSD job is done. */
260
+	__u32 out_sync;
261
+};
262
+
190
263
 #if defined(__cplusplus)
191
264
 }
192
265
 #endif