.. | .. |
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29 | 29 | struct resource res; |
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30 | 30 | struct resource busr; |
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31 | 31 | void *priv; |
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32 | | - struct pci_ecam_ops *ops; |
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| 32 | + const struct pci_ecam_ops *ops; |
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33 | 33 | union { |
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34 | 34 | void __iomem *win; /* 64-bit single mapping */ |
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35 | 35 | void __iomem **winp; /* 32-bit per-bus mapping */ |
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.. | .. |
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40 | 40 | /* create and free pci_config_window */ |
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41 | 41 | struct pci_config_window *pci_ecam_create(struct device *dev, |
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42 | 42 | struct resource *cfgres, struct resource *busr, |
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43 | | - struct pci_ecam_ops *ops); |
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| 43 | + const struct pci_ecam_ops *ops); |
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44 | 44 | void pci_ecam_free(struct pci_config_window *cfg); |
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45 | 45 | |
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46 | 46 | /* map_bus when ->sysdata is an instance of pci_config_window */ |
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47 | 47 | void __iomem *pci_ecam_map_bus(struct pci_bus *bus, unsigned int devfn, |
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48 | 48 | int where); |
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49 | 49 | /* default ECAM ops */ |
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50 | | -extern struct pci_ecam_ops pci_generic_ecam_ops; |
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| 50 | +extern const struct pci_ecam_ops pci_generic_ecam_ops; |
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51 | 51 | |
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52 | 52 | #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS) |
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53 | | -extern struct pci_ecam_ops pci_32b_ops; /* 32-bit accesses only */ |
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54 | | -extern struct pci_ecam_ops hisi_pcie_ops; /* HiSilicon */ |
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55 | | -extern struct pci_ecam_ops thunder_pem_ecam_ops; /* Cavium ThunderX 1.x & 2.x */ |
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56 | | -extern struct pci_ecam_ops pci_thunder_ecam_ops; /* Cavium ThunderX 1.x */ |
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57 | | -extern struct pci_ecam_ops xgene_v1_pcie_ecam_ops; /* APM X-Gene PCIe v1 */ |
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58 | | -extern struct pci_ecam_ops xgene_v2_pcie_ecam_ops; /* APM X-Gene PCIe v2.x */ |
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| 53 | +extern const struct pci_ecam_ops pci_32b_ops; /* 32-bit accesses only */ |
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| 54 | +extern const struct pci_ecam_ops pci_32b_read_ops; /* 32-bit read only */ |
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| 55 | +extern const struct pci_ecam_ops hisi_pcie_ops; /* HiSilicon */ |
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| 56 | +extern const struct pci_ecam_ops rk_pcie_ecam_ops; /* Rockchip */ |
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| 57 | +extern const struct pci_ecam_ops thunder_pem_ecam_ops; /* Cavium ThunderX 1.x & 2.x */ |
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| 58 | +extern const struct pci_ecam_ops pci_thunder_ecam_ops; /* Cavium ThunderX 1.x */ |
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| 59 | +extern const struct pci_ecam_ops xgene_v1_pcie_ecam_ops; /* APM X-Gene PCIe v1 */ |
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| 60 | +extern const struct pci_ecam_ops xgene_v2_pcie_ecam_ops; /* APM X-Gene PCIe v2.x */ |
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| 61 | +extern const struct pci_ecam_ops al_pcie_ops; /* Amazon Annapurna Labs PCIe */ |
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59 | 62 | #endif |
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60 | 63 | |
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61 | | -#ifdef CONFIG_PCI_HOST_COMMON |
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| 64 | +#if IS_ENABLED(CONFIG_PCI_HOST_COMMON) |
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62 | 65 | /* for DT-based PCI controllers that support ECAM */ |
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63 | | -int pci_host_common_probe(struct platform_device *pdev, |
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64 | | - struct pci_ecam_ops *ops); |
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| 66 | +int pci_host_common_probe(struct platform_device *pdev); |
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65 | 67 | int pci_host_common_remove(struct platform_device *pdev); |
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66 | 68 | #endif |
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67 | 69 | #endif |
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