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2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390 
 kernel/include/linux/mlx5/device.h
....@@ -67,7 +67,7 @@
6767 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
6868 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
6969 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
70
-#define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
70
+#define MLX5_ADDR_OF(typ, p, fld) ((void *)((uint8_t *)(p) + MLX5_BYTE_OFF(typ, fld)))
7171 
7272 /* insert a value to a struct */
7373 #define MLX5_SET(typ, p, fld, v) do { \
....@@ -212,6 +212,13 @@
212212 	MLX5_PFAULT_SUBTYPE_RDMA = 1,
213213 };
214214 
215
+enum wqe_page_fault_type {
216
+	MLX5_WQE_PF_TYPE_RMP = 0,
217
+	MLX5_WQE_PF_TYPE_REQ_SEND_OR_WRITE = 1,
218
+	MLX5_WQE_PF_TYPE_RESP = 2,
219
+	MLX5_WQE_PF_TYPE_REQ_READ_OR_ATOMIC = 3,
220
+};
221
+
215222 enum {
216223 	MLX5_PERM_LOCAL_READ	= 1 << 2,
217224 	MLX5_PERM_LOCAL_WRITE	= 1 << 3,
....@@ -269,7 +276,9 @@
269276 	MLX5_MKEY_MASK_RW		= 1ull << 20,
270277 	MLX5_MKEY_MASK_A		= 1ull << 21,
271278 	MLX5_MKEY_MASK_SMALL_FENCE	= 1ull << 23,
272
-	MLX5_MKEY_MASK_FREE		= 1ull << 29,
279
+	MLX5_MKEY_MASK_RELAXED_ORDERING_WRITE	= 1ull << 25,
280
+	MLX5_MKEY_MASK_FREE			= 1ull << 29,
281
+	MLX5_MKEY_MASK_RELAXED_ORDERING_READ	= 1ull << 47,
273282 };
274283 
275284 enum {
....@@ -294,9 +303,15 @@
294303 	MLX5_EVENT_QUEUE_TYPE_DCT = 6,
295304 };
296305 
306
+/* mlx5 components can subscribe to any one of these events via
307
+ * mlx5_eq_notifier_register API.
308
+ */
297309 enum mlx5_event {
310
+	/* Special value to subscribe to any event */
311
+	MLX5_EVENT_TYPE_NOTIFY_ANY	   = 0x0,
312
+	/* HW events enum start: comp events are not subscribable */
298313 	MLX5_EVENT_TYPE_COMP		   = 0x0,
299
-
314
+	/* HW Async events enum start: subscribable events */
300315 	MLX5_EVENT_TYPE_PATH_MIG	   = 0x01,
301316 	MLX5_EVENT_TYPE_COMM_EST	   = 0x02,
302317 	MLX5_EVENT_TYPE_SQ_DRAINED	   = 0x03,
....@@ -315,8 +330,10 @@
315330 	MLX5_EVENT_TYPE_GPIO_EVENT	   = 0x15,
316331 	MLX5_EVENT_TYPE_PORT_MODULE_EVENT  = 0x16,
317332 	MLX5_EVENT_TYPE_TEMP_WARN_EVENT    = 0x17,
333
+	MLX5_EVENT_TYPE_XRQ_ERROR	   = 0x18,
318334 	MLX5_EVENT_TYPE_REMOTE_CONFIG	   = 0x19,
319335 	MLX5_EVENT_TYPE_GENERAL_EVENT	   = 0x22,
336
+	MLX5_EVENT_TYPE_MONITOR_COUNTER    = 0x24,
320337 	MLX5_EVENT_TYPE_PPS_EVENT          = 0x25,
321338 
322339 	MLX5_EVENT_TYPE_DB_BF_CONGESTION   = 0x1a,
....@@ -328,12 +345,17 @@
328345 	MLX5_EVENT_TYPE_PAGE_FAULT	   = 0xc,
329346 	MLX5_EVENT_TYPE_NIC_VPORT_CHANGE   = 0xd,
330347 
348
+	MLX5_EVENT_TYPE_ESW_FUNCTIONS_CHANGED = 0xe,
349
+
331350 	MLX5_EVENT_TYPE_DCT_DRAINED        = 0x1c,
351
+	MLX5_EVENT_TYPE_DCT_KEY_VIOLATION  = 0x1d,
332352 
333353 	MLX5_EVENT_TYPE_FPGA_ERROR         = 0x20,
334354 	MLX5_EVENT_TYPE_FPGA_QP_ERROR      = 0x21,
335355 
336356 	MLX5_EVENT_TYPE_DEVICE_TRACER      = 0x26,
357
+
358
+	MLX5_EVENT_TYPE_MAX                = 0x100,
337359 };
338360 
339361 enum {
....@@ -343,6 +365,9 @@
343365 
344366 enum {
345367 	MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1,
368
+	MLX5_GENERAL_SUBTYPE_PCI_POWER_CHANGE_EVENT = 0x5,
369
+	MLX5_GENERAL_SUBTYPE_FW_LIVE_PATCH_EVENT = 0x7,
370
+	MLX5_GENERAL_SUBTYPE_PCI_SYNC_FOR_FW_UPDATE_EVENT = 0x8,
346371 };
347372 
348373 enum {
....@@ -405,6 +430,7 @@
405430 	MLX5_OPCODE_ATOMIC_MASKED_FA	= 0x15,
406431 	MLX5_OPCODE_BIND_MW		= 0x18,
407432 	MLX5_OPCODE_CONFIG_CMD		= 0x1f,
433
+	MLX5_OPCODE_ENHANCED_MPSW	= 0x29,
408434 
409435 	MLX5_RECV_OPCODE_RDMA_WRITE_IMM	= 0x00,
410436 	MLX5_RECV_OPCODE_SEND		= 0x01,
....@@ -417,11 +443,31 @@
417443 	MLX5_OPCODE_SET_PSV		= 0x20,
418444 	MLX5_OPCODE_GET_PSV		= 0x21,
419445 	MLX5_OPCODE_CHECK_PSV		= 0x22,
446
+	MLX5_OPCODE_DUMP		= 0x23,
420447 	MLX5_OPCODE_RGET_PSV		= 0x26,
421448 	MLX5_OPCODE_RCHECK_PSV		= 0x27,
422449 
423450 	MLX5_OPCODE_UMR			= 0x25,
424451 
452
+};
453
+
454
+enum {
455
+	MLX5_OPC_MOD_TLS_TIS_STATIC_PARAMS = 0x1,
456
+	MLX5_OPC_MOD_TLS_TIR_STATIC_PARAMS = 0x2,
457
+};
458
+
459
+enum {
460
+	MLX5_OPC_MOD_TLS_TIS_PROGRESS_PARAMS = 0x1,
461
+	MLX5_OPC_MOD_TLS_TIR_PROGRESS_PARAMS = 0x2,
462
+};
463
+
464
+struct mlx5_wqe_tls_static_params_seg {
465
+	u8     ctx[MLX5_ST_SZ_BYTES(tls_static_params)];
466
+};
467
+
468
+struct mlx5_wqe_tls_progress_params_seg {
469
+	__be32 tis_tir_num;
470
+	u8     ctx[MLX5_ST_SZ_BYTES(tls_progress_params)];
425471 };
426472 
427473 enum {
....@@ -490,6 +536,10 @@
490536 	u8		status_own;
491537 };
492538 
539
+enum mlx5_fatal_assert_bit_offsets {
540
+	MLX5_RFR_OFFSET = 31,
541
+};
542
+
493543 struct health_buffer {
494544 	__be32		assert_var[5];
495545 	__be32		rsvd0[3];
....@@ -498,10 +548,18 @@
498548 	__be32		rsvd1[2];
499549 	__be32		fw_ver;
500550 	__be32		hw_id;
501
-	__be32		rsvd2;
551
+	__be32		rfr;
502552 	u8		irisc_index;
503553 	u8		synd;
504554 	__be16		ext_synd;
555
+};
556
+
557
+enum mlx5_initializing_bit_offsets {
558
+	MLX5_FW_RESET_SUPPORTED_OFFSET = 30,
559
+};
560
+
561
+enum mlx5_cmd_addr_l_sz_offset {
562
+	MLX5_NIC_IFC_OFFSET = 8,
505563 };
506564 
507565 struct mlx5_init_seg {
....@@ -543,6 +601,12 @@
543601 	u8	syndrome;
544602 };
545603 
604
+struct mlx5_eqe_xrq_err {
605
+	__be32	reserved1[5];
606
+	__be32	type_xrqn;
607
+	__be32	reserved2;
608
+};
609
+
546610 struct mlx5_eqe_port_state {
547611 	u8	reserved0[8];
548612 	u8	port;
....@@ -570,7 +634,7 @@
570634 };
571635 
572636 struct mlx5_eqe_page_req {
573
-	u8		rsvd0[2];
637
+	__be16		ec_function;
574638 	__be16		func_id;
575639 	__be32		num_pages;
576640 	__be32		rsvd1[5];
....@@ -640,6 +704,19 @@
640704 	__be64 sensor_warning_lsb;
641705 } __packed;
642706 
707
+#define SYNC_RST_STATE_MASK    0xf
708
+
709
+enum sync_rst_state_type {
710
+	MLX5_SYNC_RST_STATE_RESET_REQUEST	= 0x0,
711
+	MLX5_SYNC_RST_STATE_RESET_NOW		= 0x1,
712
+	MLX5_SYNC_RST_STATE_RESET_ABORT		= 0x2,
713
+};
714
+
715
+struct mlx5_eqe_sync_fw_update {
716
+	u8 reserved_at_0[3];
717
+	u8 sync_rst_state;
718
+};
719
+
643720 union ev_data {
644721 	__be32				raw[7];
645722 	struct mlx5_eqe_cmd		cmd;
....@@ -657,6 +734,8 @@
657734 	struct mlx5_eqe_pps		pps;
658735 	struct mlx5_eqe_dct             dct;
659736 	struct mlx5_eqe_temp_warning	temp_warning;
737
+	struct mlx5_eqe_xrq_err		xrq_err;
738
+	struct mlx5_eqe_sync_fw_update	sync_fw_update;
660739 } __packed;
661740 
662741 struct mlx5_eqe {
....@@ -699,7 +778,7 @@
699778 };
700779 
701780 struct mlx5_cqe64 {
702
-	u8		outer_l3_tunneled;
781
+	u8		tls_outer_l3_tunneled;
703782 	u8		rsvd0;
704783 	__be16		wqe_id;
705784 	u8		lro_tcppsh_abort_dupack;
....@@ -717,7 +796,12 @@
717796 	u8		l4_l3_hdr_type;
718797 	__be16		vlan_info;
719798 	__be32		srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
720
-	__be32		imm_inval_pkey;
799
+	union {
800
+		__be32 immediate;
801
+		__be32 inval_rkey;
802
+		__be32 pkey;
803
+		__be32 ft_metadata;
804
+	};
721805 	u8		rsvd40[4];
722806 	__be32		byte_cnt;
723807 	__be32		timestamp_h;
....@@ -733,7 +817,7 @@
733817 		__be32 rx_hash_result;
734818 		struct {
735819 			__be16 checksum;
736
-			__be16 rsvd;
820
+			__be16 stridx;
737821 		};
738822 		struct {
739823 			__be16 wqe_counter;
....@@ -753,6 +837,7 @@
753837 
754838 enum {
755839 	MLX5_CQE_FORMAT_CSUM = 0x1,
840
+	MLX5_CQE_FORMAT_CSUM_STRIDX = 0x3,
756841 };
757842 
758843 #define MLX5_MINI_CQE_ARRAY_SIZE 8
....@@ -760,6 +845,11 @@
760845 static inline u8 mlx5_get_cqe_format(struct mlx5_cqe64 *cqe)
761846 {
762847 	return (cqe->op_own >> 2) & 0x3;
848
+}
849
+
850
+static inline u8 get_cqe_opcode(struct mlx5_cqe64 *cqe)
851
+{
852
+	return cqe->op_own >> 4;
763853 }
764854 
765855 static inline u8 get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
....@@ -779,7 +869,12 @@
779869 
780870 static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe)
781871 {
782
-	return cqe->outer_l3_tunneled & 0x1;
872
+	return cqe->tls_outer_l3_tunneled & 0x1;
873
+}
874
+
875
+static inline u8 get_cqe_tls_offload(struct mlx5_cqe64 *cqe)
876
+{
877
+	return (cqe->tls_outer_l3_tunneled >> 3) & 0x3;
783878 }
784879 
785880 static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe)
....@@ -867,6 +962,13 @@
867962 	CQE_L4_OK	= 1 << 2,
868963 };
869964 
965
+enum {
966
+	CQE_TLS_OFFLOAD_NOT_DECRYPTED		= 0x0,
967
+	CQE_TLS_OFFLOAD_DECRYPTED		= 0x1,
968
+	CQE_TLS_OFFLOAD_RESYNC			= 0x2,
969
+	CQE_TLS_OFFLOAD_ERROR			= 0x3,
970
+};
971
+
870972 struct mlx5_sig_err_cqe {
871973 	u8		rsvd0[16];
872974 	__be32		expected_trans_sig;
....@@ -909,7 +1011,6 @@
9091011 	MLX5_MKEY_REMOTE_INVAL	= 1 << 24,
9101012 	MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
9111013 	MLX5_MKEY_BSF_EN	= 1 << 30,
912
-	MLX5_MKEY_LEN64		= 1 << 31,
9131014 };
9141015 
9151016 struct mlx5_mkey_seg {
....@@ -973,7 +1074,8 @@
9731074 	MLX5_MATCH_OUTER_HEADERS	= 1 << 0,
9741075 	MLX5_MATCH_MISC_PARAMETERS	= 1 << 1,
9751076 	MLX5_MATCH_INNER_HEADERS	= 1 << 2,
976
-
1077
+	MLX5_MATCH_MISC_PARAMETERS_2	= 1 << 3,
1078
+	MLX5_MATCH_MISC_PARAMETERS_3	= 1 << 4,
9771079 };
9781080 
9791081 enum {
....@@ -1017,6 +1119,7 @@
10171119 };
10181120 
10191121 enum mlx5_flex_parser_protos {
1122
+	MLX5_FLEX_PROTO_GENEVE	      = 1 << 3,
10201123 	MLX5_FLEX_PROTO_CW_MPLS_GRE   = 1 << 4,
10211124 	MLX5_FLEX_PROTO_CW_MPLS_UDP   = 1 << 5,
10221125 };
....@@ -1046,6 +1149,11 @@
10461149 	MLX5_CAP_DEBUG,
10471150 	MLX5_CAP_RESERVED_14,
10481151 	MLX5_CAP_DEV_MEM,
1152
+	MLX5_CAP_RESERVED_16,
1153
+	MLX5_CAP_TLS,
1154
+	MLX5_CAP_VDPA_EMULATION = 0x13,
1155
+	MLX5_CAP_DEV_EVENT = 0x14,
1156
+	MLX5_CAP_IPSEC,
10491157 	/* NUM OF CAP Types */
10501158 	MLX5_CAP_NUM
10511159 };
....@@ -1060,6 +1168,9 @@
10601168 
10611169 enum mlx5_mcam_reg_groups {
10621170 	MLX5_MCAM_REGS_FIRST_128                    = 0x0,
1171
+	MLX5_MCAM_REGS_0x9080_0x90FF                = 0x1,
1172
+	MLX5_MCAM_REGS_0x9100_0x917F                = 0x2,
1173
+	MLX5_MCAM_REGS_NUM                          = 0x3,
10631174 };
10641175 
10651176 enum mlx5_mcam_feature_groups {
....@@ -1111,6 +1222,9 @@
11111222 #define MLX5_CAP_FLOWTABLE(mdev, cap) \
11121223 	MLX5_GET(flow_table_nic_cap, mdev->caps.hca_cur[MLX5_CAP_FLOW_TABLE], cap)
11131224 
1225
+#define MLX5_CAP64_FLOWTABLE(mdev, cap) \
1226
+	MLX5_GET64(flow_table_nic_cap, (mdev)->caps.hca_cur[MLX5_CAP_FLOW_TABLE], cap)
1227
+
11141228 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
11151229 	MLX5_GET(flow_table_nic_cap, mdev->caps.hca_max[MLX5_CAP_FLOW_TABLE], cap)
11161230 
....@@ -1119,6 +1233,12 @@
11191233 
11201234 #define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \
11211235 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
1236
+
1237
+#define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \
1238
+		MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit.cap)
1239
+
1240
+#define MLX5_CAP_FLOWTABLE_NIC_TX_MAX(mdev, cap) \
1241
+	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit.cap)
11221242 
11231243 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \
11241244 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
....@@ -1131,6 +1251,18 @@
11311251 
11321252 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \
11331253 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1254
+
1255
+#define MLX5_CAP_FLOWTABLE_RDMA_RX(mdev, cap) \
1256
+	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_rdma.cap)
1257
+
1258
+#define MLX5_CAP_FLOWTABLE_RDMA_RX_MAX(mdev, cap) \
1259
+	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_rdma.cap)
1260
+
1261
+#define MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, cap) \
1262
+	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_rdma.cap)
1263
+
1264
+#define MLX5_CAP_FLOWTABLE_RDMA_TX_MAX(mdev, cap) \
1265
+	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_rdma.cap)
11341266 
11351267 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
11361268 	MLX5_GET(flow_table_eswitch_cap, \
....@@ -1162,12 +1294,19 @@
11621294 	MLX5_GET(e_switch_cap, \
11631295 		 mdev->caps.hca_cur[MLX5_CAP_ESWITCH], cap)
11641296 
1297
+#define MLX5_CAP64_ESW_FLOWTABLE(mdev, cap) \
1298
+	MLX5_GET64(flow_table_eswitch_cap, \
1299
+		(mdev)->caps.hca_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1300
+
11651301 #define MLX5_CAP_ESW_MAX(mdev, cap) \
11661302 	MLX5_GET(e_switch_cap, \
11671303 		 mdev->caps.hca_max[MLX5_CAP_ESWITCH], cap)
11681304 
11691305 #define MLX5_CAP_ODP(mdev, cap)\
11701306 	MLX5_GET(odp_cap, mdev->caps.hca_cur[MLX5_CAP_ODP], cap)
1307
+
1308
+#define MLX5_CAP_ODP_MAX(mdev, cap)\
1309
+	MLX5_GET(odp_cap, mdev->caps.hca_max[MLX5_CAP_ODP], cap)
11711310 
11721311 #define MLX5_CAP_VECTOR_CALC(mdev, cap) \
11731312 	MLX5_GET(vector_calc_cap, \
....@@ -1186,7 +1325,16 @@
11861325 	MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg)
11871326 
11881327 #define MLX5_CAP_MCAM_REG(mdev, reg) \
1189
-	MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg)
1328
+	MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_FIRST_128], \
1329
+		 mng_access_reg_cap_mask.access_regs.reg)
1330
+
1331
+#define MLX5_CAP_MCAM_REG1(mdev, reg) \
1332
+	MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9080_0x90FF], \
1333
+		 mng_access_reg_cap_mask.access_regs1.reg)
1334
+
1335
+#define MLX5_CAP_MCAM_REG2(mdev, reg) \
1336
+	MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9100_0x917F], \
1337
+		 mng_access_reg_cap_mask.access_regs2.reg)
11901338 
11911339 #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \
11921340 	MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
....@@ -1208,6 +1356,23 @@
12081356 
12091357 #define MLX5_CAP64_DEV_MEM(mdev, cap)\
12101358 	MLX5_GET64(device_mem_cap, mdev->caps.hca_cur[MLX5_CAP_DEV_MEM], cap)
1359
+
1360
+#define MLX5_CAP_TLS(mdev, cap) \
1361
+	MLX5_GET(tls_cap, (mdev)->caps.hca_cur[MLX5_CAP_TLS], cap)
1362
+
1363
+#define MLX5_CAP_DEV_EVENT(mdev, cap)\
1364
+	MLX5_ADDR_OF(device_event_cap, (mdev)->caps.hca_cur[MLX5_CAP_DEV_EVENT], cap)
1365
+
1366
+#define MLX5_CAP_DEV_VDPA_EMULATION(mdev, cap)\
1367
+	MLX5_GET(virtio_emulation_cap, \
1368
+		(mdev)->caps.hca_cur[MLX5_CAP_VDPA_EMULATION], cap)
1369
+
1370
+#define MLX5_CAP64_DEV_VDPA_EMULATION(mdev, cap)\
1371
+	MLX5_GET64(virtio_emulation_cap, \
1372
+		(mdev)->caps.hca_cur[MLX5_CAP_VDPA_EMULATION], cap)
1373
+
1374
+#define MLX5_CAP_IPSEC(mdev, cap)\
1375
+	MLX5_GET(ipsec_cap, (mdev)->caps.hca_cur[MLX5_CAP_IPSEC], cap)
12111376 
12121377 enum {
12131378 	MLX5_CMD_STAT_OK			= 0x0,
....@@ -1237,6 +1402,7 @@
12371402 	MLX5_PER_PRIORITY_COUNTERS_GROUP      = 0x10,
12381403 	MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
12391404 	MLX5_PHYSICAL_LAYER_COUNTERS_GROUP    = 0x12,
1405
+	MLX5_PER_TRAFFIC_CLASS_CONGESTION_GROUP = 0x13,
12401406 	MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16,
12411407 	MLX5_INFINIBAND_PORT_COUNTERS_GROUP   = 0x20,
12421408 };