change wifi driver to cypress

hc

2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390

 kernel/include/linux/mfd/rk630.h
..
..
@@ -17,149 +17,206 @@
17
17
 #define HIWORD_MASK(h, l)	((GENMASK((h), (l)) << 16) | GENMASK((h), (l)))
18
18
 #define HIWORD_UPDATE(v, h, l)	((((v) << (l)) & GENMASK((h), (l))) | (GENMASK((h), (l)) << 16))
19
19
 
20
-#define GRF_REG(x)                    ((x) + 0x20000)
21
-#define PLUMAGE_GRF_GPIO0A_IOMUX      GRF_REG(0x0000)
22
-#define GPIO0A0_SEL_MASK              HIWORD_MASK(1, 0)
23
-#define GPIO0A0_SEL(x)                HIWORD_UPDATE(x, 1, 0)
24
-#define GPIO0A1_SEL_MASK              HIWORD_MASK(3, 2)
25
-#define GPIO0A1_SEL(x)                HIWORD_UPDATE(x, 3, 2)
26
-#define GPIO0A2_SEL_MASK              HIWORD_MASK(5, 4)
27
-#define GPIO0A2_SEL(x)                HIWORD_UPDATE(x, 5, 4)
28
-#define GPIO0A3_SEL_MASK              HIWORD_MASK(7, 6)
29
-#define GPIO0A3_SEL(x)                HIWORD_UPDATE(x, 7, 6)
30
-#define GPIO0A4_SEL_MASK              HIWORD_MASK(9, 8)
31
-#define GPIO0A4_SEL(x)                HIWORD_UPDATE(x, 9, 8)
32
-#define GPIO0A5_SEL_MASK              HIWORD_MASK(11, 10)
33
-#define GPIO0A5_SEL(x)                HIWORD_UPDATE(x, 11, 10)
34
-#define GPIO0A6_SEL_MASK              HIWORD_MASK(13, 12)
35
-#define GPIO0A6_SEL(x)                HIWORD_UPDATE(x, 13, 12)
36
-#define GPIO0A7_SEL_MASK              HIWORD_MASK(15, 14)
37
-#define GPIO0A7_SEL(x)                HIWORD_UPDATE(x, 15, 14)
38
-#define PLUMAGE_GRF_GPIO0B_IOMUX      GRF_REG(0x0008)
39
-#define GPIO0B0_SEL_MASK              HIWORD_MASK(1, 0)
40
-#define GPIO0B0_SEL(x)                HIWORD_UPDATE(x, 1, 0)
41
-#define PLUMAGE_GRF_GPIO0C_IOMUX      GRF_REG(0x0010)
42
-#define PLUMAGE_GRF_GPIO0D_IOMUX      GRF_REG(0x0018)
43
-#define PLUMAGE_GRF_GPIO1A_IOMUX      GRF_REG(0x0020)
44
-#define PLUMAGE_GRF_GPIO1B_IOMUX      GRF_REG(0x0028)
45
-#define PLUMAGE_GRF_GPIO0A_P          GRF_REG(0x0080)
46
-#define PLUMAGE_GRF_GPIO0B_P          GRF_REG(0x0084)
47
-#define PLUMAGE_GRF_GPIO0C_P          GRF_REG(0x0088)
48
-#define PLUMAGE_GRF_GPIO0D_P          GRF_REG(0x008C)
49
-#define PLUMAGE_GRF_GPIO1A_P          GRF_REG(0x0090)
50
-#define PLUMAGE_GRF_GPIO1B_P          GRF_REG(0x0094)
51
-#define PLUMAGE_GRF_GPIO1B_SR         GRF_REG(0x00D4)
52
-#define PLUMAGE_GRF_GPIO1B_E          GRF_REG(0x0154)
53
-#define PLUMAGE_GRF_SOC_CON0          GRF_REG(0x0400)
54
-#define SW_TVE_DCLK_POL_MASK          HIWORD_MASK(4, 4)
55
-#define SW_TVE_DCLK_POL(x)            HIWORD_UPDATE(x, 4, 4)
56
-#define SW_TVE_DCLK_EN_MASK           HIWORD_MASK(3, 3)
57
-#define SW_TVE_DCLK_EN(x)             HIWORD_UPDATE(x, 3, 3)
58
-#define SW_DCLK_UPSAMPLE_EN_MASK      HIWORD_MASK(2, 2)
59
-#define SW_DCLK_UPSAMPLE_EN(x)        HIWORD_UPDATE(x, 2, 2)
60
-#define SW_TVE_MODE_MASK              HIWORD_MASK(1, 1)
61
-#define SW_TVE_MODE(x)                HIWORD_UPDATE(x, 1, 1)
62
-#define SW_TVE_EN_MASK                HIWORD_MASK(0, 0)
63
-#define SW_TVE_EN(x)                  HIWORD_UPDATE(x, 0, 0)
64
-#define PLUMAGE_GRF_SOC_CON1          GRF_REG(0x0404)
65
-#define PLUMAGE_GRF_SOC_CON2          GRF_REG(0x0408)
66
-#define PLUMAGE_GRF_SOC_CON3          GRF_REG(0x040C)
67
-#define VDAC_ENVBG_MASK               HIWORD_MASK(12, 12)
68
-#define VDAC_ENVBG(x)                 HIWORD_UPDATE(x, 12, 12)
69
-#define VDAC_ENSC0_MASK               HIWORD_MASK(11, 11)
70
-#define VDAC_ENSC0(x)                 HIWORD_UPDATE(x, 11, 11)
71
-#define VDAC_ENEXTREF_MASK            HIWORD_MASK(10, 10)
72
-#define VDAC_ENEXTREF(x)              HIWORD_UPDATE(x, 10, 10)
73
-#define VDAC_ENDAC0_MASK              HIWORD_MASK(9, 9)
74
-#define VDAC_ENDAC0(x)                HIWORD_UPDATE(x, 9, 9)
75
-#define VDAC_ENCTR2_MASK              HIWORD_MASK(8, 8)
76
-#define VDAC_ENCTR2(x)                HIWORD_UPDATE(x, 8, 8)
77
-#define VDAC_ENCTR1_MASK              HIWORD_MASK(7, 7)
78
-#define VDAC_ENCTR1(x)                HIWORD_UPDATE(x, 7, 7)
79
-#define VDAC_ENCTR0_MASK              HIWORD_MASK(6, 6)
80
-#define VDAC_ENCTR0(x)                HIWORD_UPDATE(x, 6, 6)
81
-#define VDAC_GAIN_MASK                GENMASK(x, 5, 0)
82
-#define VDAC_GAIN(x)                  HIWORD_UPDATE(x, 5, 0)
83
-#define PLUMAGE_GRF_SOC_CON4          GRF_REG(0x0410)
84
-#define PLUMAGE_GRF_SOC_STATUS        GRF_REG(0x0480)
85
-#define PLUMAGE_GRF_GPIO0_REN0        GRF_REG(0x0500)
86
-#define PLUMAGE_GRF_GPIO0_REN1        GRF_REG(0x0504)
87
-#define PLUMAGE_GRF_GPIO1_REN0        GRF_REG(0x0508)
88
-#define GRF_MAX_REGISTER              PLUMAGE_GRF_GPIO1_REN0
20
+#define RTC_REG(x)			((x) + 0x60000)
21
+#define RTC_SET_SECONDS			RTC_REG(0x0)
22
+#define RTC_SET_MINUTES			RTC_REG(0x4)
23
+#define RTC_SET_HOURS			RTC_REG(0x8)
24
+#define RTC_SET_DAYS			RTC_REG(0xc)
25
+#define RTC_SET_MONTHS			RTC_REG(0x10)
26
+#define RTC_SET_YEARL			RTC_REG(0x14)
27
+#define RTC_SET_YEARH			RTC_REG(0x18)
28
+#define RTC_SET_WEEKS			RTC_REG(0x1c)
29
+#define RTC_ALARM_SECONDS		RTC_REG(0x20)
30
+#define RTC_ALARM_MINUTES		RTC_REG(0x24)
31
+#define RTC_ALARM_HOURS			RTC_REG(0x28)
32
+#define RTC_ALARM_DAYS			RTC_REG(0x2c)
33
+#define RTC_ALARM_MONTHS		RTC_REG(0x30)
34
+#define RTC_ALARM_YEARL			RTC_REG(0x34)
35
+#define RTC_ALARM_YEARH			RTC_REG(0x38)
36
+#define RTC_CTRL			RTC_REG(0x3C)
37
+#define RTC_STATUS0			RTC_REG(0x40)
38
+#define RTC_STATUS1			RTC_REG(0x44)
39
+#define RTC_INT0_EN			RTC_REG(0x48)
40
+#define RTC_INT1_EN			RTC_REG(0x4c)
41
+#define RTC_MSEC_CTRL			RTC_REG(0x50)
42
+#define RTC_MSEC_CNT			RTC_REG(0x54)
43
+#define RTC_COMP_H			RTC_REG(0x58)
44
+#define RTC_COMP_D			RTC_REG(0x5c)
45
+#define RTC_COMP_M			RTC_REG(0x60)
46
+#define RTC_ANALOG_CTRL			RTC_REG(0x64)
47
+#define RTC_ANALOG_TEST			RTC_REG(0x68)
48
+#define RTC_LDO_CTRL			RTC_REG(0x6c)
49
+#define RTC_XO_TRIM0			RTC_REG(0x70)
50
+#define RTC_XO_TRIM1			RTC_REG(0x74)
51
+#define RTC_VPTAT_TRIM			RTC_REG(0x78)
52
+#define RTC_ANALOG_EN			RTC_REG(0x7c)
53
+#define RTC_CLK32K_TEST			RTC_REG(0x80)
54
+#define RTC_TEST_ST			RTC_REG(0x84)
55
+#define RTC_TEST_LEN			RTC_REG(0x88)
56
+#define RTC_CNT_0			RTC_REG(0x8c)
57
+#define RTC_CNT_1			RTC_REG(0x90)
58
+#define RTC_CNT_2			RTC_REG(0x94)
59
+#define RTC_CNT_3			RTC_REG(0x98)
60
+#define RTC_MAX_REGISTER		RTC_CNT_3
89
61
 
90
-#define CRU_REG(x)                    ((x) + 0x140000)
91
-#define CRU_SPLL_CON0                 CRU_REG(0x0000)
92
-#define POSTDIV1_MASK                 HIWORD_MASK(14, 12)
93
-#define POSTDIV1(x)                   HIWORD_UPDATE(x, 14, 12)
94
-#define FBDIV_MASK                    HIWORD_MASK(14, 12)
95
-#define FBDIV(x)                      HIWORD_UPDATE(x, 14, 12)
96
-#define CRU_SPLL_CON1                 CRU_REG(0x0004)
97
-#define PLLPD0_MASK                   HIWORD_MASK(13, 13)
98
-#define PLLPD0(x)                     HIWORD_UPDATE(x, 13, 13)
99
-#define PLL_LOCK                      BIT(10)
100
-#define POSTDIV2_MASK                 HIWORD_MASK(8, 6)
101
-#define POSTDIV2(x)                   HIWORD_UPDATE(x, 8, 6)
102
-#define REFDIV_MASK                   HIWORD_MASK(5, 0)
103
-#define REFDIV(x)                     HIWORD_UPDATE(x, 5, 0)
104
-#define CRU_SPLL_CON2                 CRU_REG(0x0008)
105
-#define CRU_MODE_CON                  CRU_REG(0x0020)
106
-#define CLK_SPLL_MODE_MASK            HIWORD_MASK(2, 0)
107
-#define CLK_SPLL_MODE(x)              HIWORD_UPDATE(x, 2, 0)
108
-#define CRU_CLKSEL_CON0               CRU_REG(0x0030)
109
-#define CRU_CLKSEL_CON1               CRU_REG(0x0034)
110
-#define DCLK_CVBS_4X_DIV_CON_MASK     HIWORD_MASK(12, 8)
111
-#define DCLK_CVBS_4X_DIV_CON(x)       HIWORD_UPDATE(x, 12, 8)
112
-#define CRU_CLKSEL_CON2               CRU_REG(0x0038)
113
-#define CRU_CLKSEL_CON3               CRU_REG(0x003c)
114
-#define CRU_GATE_CON0                 CRU_REG(0x0040)
115
-#define CRU_SOFTRST_CON0              CRU_REG(0x0050)
116
-#define DRESETN_CVBS_1X_MASK          HIWORD_MASK(10, 10)
117
-#define DRESETN_CVBS_1X(x)            HIWORD_UPDATE(x, 10, 10)
118
-#define DRESETN_CVBS_4X_MASK          HIWORD_MASK(9, 9)
119
-#define DRESETN_CVBS_4X(x)            HIWORD_UPDATE(x, 9, 9)
120
-#define PRESETN_CVBS_MASK             HIWORD_MASK(8, 8)
121
-#define PRESETN_CVBS(x)               HIWORD_UPDATE(x, 8, 8)
122
-#define PRESETN_GRF_MASK              HIWORD_MASK(3, 3)
123
-#define PRESETN_GRF(x)                HIWORD_UPDATE(x, 3, 3)
124
-#define CRU_MAX_REGISTER              CRU_SOFTRST_CON0
62
+#define GRF_REG(x)			((x) + 0x20000)
63
+#define PLUMAGE_GRF_GPIO0A_IOMUX	GRF_REG(0x0000)
64
+#define GPIO0A0_SEL_MASK		HIWORD_MASK(1, 0)
65
+#define GPIO0A0_SEL(x)			HIWORD_UPDATE(x, 1, 0)
66
+#define GPIO0A1_SEL_MASK		HIWORD_MASK(3, 2)
67
+#define GPIO0A1_SEL(x)			HIWORD_UPDATE(x, 3, 2)
68
+#define GPIO0A2_SEL_MASK		HIWORD_MASK(5, 4)
69
+#define GPIO0A2_SEL(x)			HIWORD_UPDATE(x, 5, 4)
70
+#define GPIO0A3_SEL_MASK		HIWORD_MASK(7, 6)
71
+#define GPIO0A3_SEL(x)			HIWORD_UPDATE(x, 7, 6)
72
+#define GPIO0A4_SEL_MASK		HIWORD_MASK(9, 8)
73
+#define GPIO0A4_SEL(x)			HIWORD_UPDATE(x, 9, 8)
74
+#define GPIO0A5_SEL_MASK		HIWORD_MASK(11, 10)
75
+#define GPIO0A5_SEL(x)			HIWORD_UPDATE(x, 11, 10)
76
+#define GPIO0A6_SEL_MASK		HIWORD_MASK(13, 12)
77
+#define GPIO0A6_SEL(x)			HIWORD_UPDATE(x, 13, 12)
78
+#define GPIO0A7_SEL_MASK		HIWORD_MASK(15, 14)
79
+#define GPIO0A7_SEL(x)			HIWORD_UPDATE(x, 15, 14)
80
+#define PLUMAGE_GRF_GPIO0B_IOMUX	GRF_REG(0x0008)
81
+#define GPIO0B0_SEL_MASK		HIWORD_MASK(1, 0)
82
+#define GPIO0B0_SEL(x)			HIWORD_UPDATE(x, 1, 0)
83
+#define PLUMAGE_GRF_GPIO0C_IOMUX	GRF_REG(0x0010)
84
+#define PLUMAGE_GRF_GPIO0D_IOMUX	GRF_REG(0x0018)
85
+#define PLUMAGE_GRF_GPIO1A_IOMUX	GRF_REG(0x0020)
86
+#define PLUMAGE_GRF_GPIO1B_IOMUX	GRF_REG(0x0028)
87
+#define PLUMAGE_GRF_GPIO0A_P		GRF_REG(0x0080)
88
+#define PLUMAGE_GRF_GPIO0B_P		GRF_REG(0x0084)
89
+#define PLUMAGE_GRF_GPIO0C_P		GRF_REG(0x0088)
90
+#define PLUMAGE_GRF_GPIO0D_P		GRF_REG(0x008C)
91
+#define PLUMAGE_GRF_GPIO1A_P		GRF_REG(0x0090)
92
+#define PLUMAGE_GRF_GPIO1B_P		GRF_REG(0x0094)
93
+#define PLUMAGE_GRF_GPIO1B_SR		GRF_REG(0x00D4)
94
+#define PLUMAGE_GRF_GPIO1B_E		GRF_REG(0x0154)
95
+#define PLUMAGE_GRF_SOC_CON0		GRF_REG(0x0400)
96
+#define RTC_CLAMP_EN_MASK		HIWORD_MASK(13, 13)
97
+#define RTC_CLAMP_EN(x)			HIWORD_UPDATE(x, 13, 13)
98
+#define SW_TVE_DCLK_POL_MASK		HIWORD_MASK(4, 4)
99
+#define SW_TVE_DCLK_POL(x)		HIWORD_UPDATE(x, 4, 4)
100
+#define SW_TVE_DCLK_POL_MASK		HIWORD_MASK(4, 4)
101
+#define SW_TVE_DCLK_POL(x)		HIWORD_UPDATE(x, 4, 4)
102
+#define SW_TVE_DCLK_EN_MASK		HIWORD_MASK(3, 3)
103
+#define SW_TVE_DCLK_EN(x)		HIWORD_UPDATE(x, 3, 3)
104
+#define SW_DCLK_UPSAMPLE_EN_MASK	HIWORD_MASK(2, 2)
105
+#define SW_DCLK_UPSAMPLE_EN(x)		HIWORD_UPDATE(x, 2, 2)
106
+#define SW_TVE_MODE_MASK		HIWORD_MASK(1, 1)
107
+#define SW_TVE_MODE(x)			HIWORD_UPDATE(x, 1, 1)
108
+#define SW_TVE_EN_MASK			HIWORD_MASK(0, 0)
109
+#define SW_TVE_EN(x)			HIWORD_UPDATE(x, 0, 0)
110
+#define PLUMAGE_GRF_SOC_CON1		GRF_REG(0x0404)
111
+#define PLUMAGE_GRF_SOC_CON2		GRF_REG(0x0408)
112
+#define PLUMAGE_GRF_SOC_CON3		GRF_REG(0x040C)
113
+#define VDAC_ENVBG_MASK			HIWORD_MASK(12, 12)
114
+#define VDAC_ENVBG(x)			HIWORD_UPDATE(x, 12, 12)
115
+#define VDAC_ENSC0_MASK			HIWORD_MASK(11, 11)
116
+#define VDAC_ENSC0(x)			HIWORD_UPDATE(x, 11, 11)
117
+#define VDAC_ENEXTREF_MASK		HIWORD_MASK(10, 10)
118
+#define VDAC_ENEXTREF(x)		HIWORD_UPDATE(x, 10, 10)
119
+#define VDAC_ENDAC0_MASK		HIWORD_MASK(9, 9)
120
+#define VDAC_ENDAC0(x)			HIWORD_UPDATE(x, 9, 9)
121
+#define VDAC_ENCTR2_MASK		HIWORD_MASK(8, 8)
122
+#define VDAC_ENCTR2(x)			HIWORD_UPDATE(x, 8, 8)
123
+#define VDAC_ENCTR1_MASK		HIWORD_MASK(7, 7)
124
+#define VDAC_ENCTR1(x)			HIWORD_UPDATE(x, 7, 7)
125
+#define VDAC_ENCTR0_MASK		HIWORD_MASK(6, 6)
126
+#define VDAC_ENCTR0(x)			HIWORD_UPDATE(x, 6, 6)
127
+#define VDAC_GAIN_MASK			GENMASK(x, 5, 0)
128
+#define VDAC_GAIN(x)			HIWORD_UPDATE(x, 5, 0)
129
+#define PLUMAGE_GRF_SOC_CON4		GRF_REG(0x0410)
130
+#define PLUMAGE_GRF_SOC_STATUS		GRF_REG(0x0480)
131
+#define PLUMAGE_GRF_GPIO0_REN0		GRF_REG(0x0500)
132
+#define PLUMAGE_GRF_GPIO0_REN1		GRF_REG(0x0504)
133
+#define PLUMAGE_GRF_GPIO1_REN0		GRF_REG(0x0508)
134
+#define PLUMAGE_GRF_RTC_STATUS		GRF_REG(0x0610)
125
135
 
126
-#define TVE_REG(x)                      ((x) + 0x10000)
127
-#define BT656_DECODER_CTRL              TVE_REG(0x3D00)
128
-#define BT656_DECODER_CROP              TVE_REG(0x3D04)
129
-#define BT656_DECODER_SIZE              TVE_REG(0x3D08)
130
-#define BT656_DECODER_HTOTAL_HS_END     TVE_REG(0x3D0C)
131
-#define BT656_DECODER_VACT_ST_HACT_ST   TVE_REG(0x3D10)
132
-#define BT656_DECODER_VTOTAL_VS_END     TVE_REG(0x3D14)
133
-#define BT656_DECODER_VS_ST_END_F1      TVE_REG(0x3D18)
134
-#define BT656_DECODER_DBG_REG           TVE_REG(0x3D1C)
135
-#define TVE_MODE_CTRL                   TVE_REG(0x3E00)
136
-#define TVE_HOR_TIMING1                 TVE_REG(0x3E04)
137
-#define TVE_HOR_TIMING2                 TVE_REG(0x3E08)
138
-#define TVE_HOR_TIMING3                 TVE_REG(0x3E0C)
139
-#define TVE_SUB_CAR_FRQ                 TVE_REG(0x3E10)
140
-#define TVE_LUMA_FILTER1                TVE_REG(0x3E14)
141
-#define TVE_LUMA_FILTER2                TVE_REG(0x3E18)
142
-#define TVE_LUMA_FILTER3                TVE_REG(0x3E1C)
143
-#define TVE_LUMA_FILTER4                TVE_REG(0x3E20)
144
-#define TVE_LUMA_FILTER5                TVE_REG(0x3E24)
145
-#define TVE_LUMA_FILTER6                TVE_REG(0x3E28)
146
-#define TVE_LUMA_FILTER7                TVE_REG(0x3E2C)
147
-#define TVE_LUMA_FILTER8                TVE_REG(0x3E30)
148
-#define TVE_IMAGE_POSITION              TVE_REG(0x3E34)
149
-#define TVE_ROUTING                     TVE_REG(0x3E38)
150
-#define TVE_SYNC_ADJUST                 TVE_REG(0x3E50)
151
-#define TVE_STATUS                      TVE_REG(0x3E54)
152
-#define TVE_CTRL                        TVE_REG(0x3E68)
153
-#define TVE_INTR_STATUS                 TVE_REG(0x3E6C)
154
-#define TVE_INTR_EN                     TVE_REG(0x3E70)
155
-#define TVE_INTR_CLR                    TVE_REG(0x3E74)
156
-#define TVE_COLOR_BUSRT_SAT             TVE_REG(0x3E78)
157
-#define TVE_CHROMA_BANDWIDTH            TVE_REG(0x3E8C)
158
-#define TVE_BRIGHTNESS_CONTRAST         TVE_REG(0x3E90)
159
-#define TVE_ID                          TVE_REG(0x3E98)
160
-#define TVE_REVISION                    TVE_REG(0x3E9C)
161
-#define TVE_CLAMP                       TVE_REG(0x3EA0)
162
-#define TVE_MAX_REGISTER                TVE_CLAMP
136
+#ifndef GRF_MAX_REGISTER
137
+#define GRF_MAX_REGISTER		PLUMAGE_GRF_RTC_STATUS
138
+#endif
139
+
140
+#define CRU_REG(x)			((x) + 0x140000)
141
+#define CRU_SPLL_CON0			CRU_REG(0x0000)
142
+#define POSTDIV1_MASK			HIWORD_MASK(14, 12)
143
+#define POSTDIV1(x)			HIWORD_UPDATE(x, 14, 12)
144
+#define FBDIV_MASK			HIWORD_MASK(14, 12)
145
+#define FBDIV(x)			HIWORD_UPDATE(x, 14, 12)
146
+#define CRU_SPLL_CON1			CRU_REG(0x0004)
147
+#define PLLPD0_MASK			HIWORD_MASK(13, 13)
148
+#define PLLPD0(x)			HIWORD_UPDATE(x, 13, 13)
149
+#define PLL_LOCK			BIT(10)
150
+#define POSTDIV2_MASK			HIWORD_MASK(8, 6)
151
+#define POSTDIV2(x)			HIWORD_UPDATE(x, 8, 6)
152
+#define REFDIV_MASK			HIWORD_MASK(5, 0)
153
+#define REFDIV(x)			HIWORD_UPDATE(x, 5, 0)
154
+#define CRU_SPLL_CON2			CRU_REG(0x0008)
155
+#define CRU_MODE_CON			CRU_REG(0x0020)
156
+#define CLK_SPLL_MODE_MASK		HIWORD_MASK(2, 0)
157
+#define CLK_SPLL_MODE(x)		HIWORD_UPDATE(x, 2, 0)
158
+#define CRU_CLKSEL_CON0			CRU_REG(0x0030)
159
+#define CRU_CLKSEL_CON1			CRU_REG(0x0034)
160
+#define DCLK_CVBS_4X_DIV_CON_MASK	HIWORD_MASK(12, 8)
161
+#define DCLK_CVBS_4X_DIV_CON(x)		HIWORD_UPDATE(x, 12, 8)
162
+#define CRU_CLKSEL_CON2			CRU_REG(0x0038)
163
+#define CRU_CLKSEL_CON3			CRU_REG(0x003c)
164
+#define CRU_GATE_CON0			CRU_REG(0x0040)
165
+#define CRU_SOFTRST_CON0		CRU_REG(0x0050)
166
+#define DRESETN_CVBS_1X_MASK		HIWORD_MASK(10, 10)
167
+#define DRESETN_CVBS_1X(x)		HIWORD_UPDATE(x, 10, 10)
168
+#define DRESETN_CVBS_4X_MASK		HIWORD_MASK(9, 9)
169
+#define DRESETN_CVBS_4X(x)		HIWORD_UPDATE(x, 9, 9)
170
+#define PRESETN_CVBS_MASK		HIWORD_MASK(8, 8)
171
+#define PRESETN_CVBS(x)			HIWORD_UPDATE(x, 8, 8)
172
+#define PRESETN_GRF_MASK		HIWORD_MASK(3, 3)
173
+#define PRESETN_GRF(x)			HIWORD_UPDATE(x, 3, 3)
174
+#define CRU_MAX_REGISTER		CRU_SOFTRST_CON0
175
+
176
+#define TVE_REG(x)			((x) + 0x10000)
177
+#define BT656_DECODER_CTRL		TVE_REG(0x3D00)
178
+#define BT656_DECODER_CROP		TVE_REG(0x3D04)
179
+#define BT656_DECODER_SIZE		TVE_REG(0x3D08)
180
+#define BT656_DECODER_HTOTAL_HS_END	TVE_REG(0x3D0C)
181
+#define BT656_DECODER_VACT_ST_HACT_ST	TVE_REG(0x3D10)
182
+#define BT656_DECODER_VTOTAL_VS_END	TVE_REG(0x3D14)
183
+#define BT656_DECODER_VS_ST_END_F1	TVE_REG(0x3D18)
184
+#define BT656_DECODER_DBG_REG		TVE_REG(0x3D1C)
185
+#define TVE_MODE_CTRL			TVE_REG(0x3E00)
186
+#define TVE_HOR_TIMING1			TVE_REG(0x3E04)
187
+#define TVE_HOR_TIMING2			TVE_REG(0x3E08)
188
+#define TVE_HOR_TIMING3			TVE_REG(0x3E0C)
189
+#define TVE_SUB_CAR_FRQ			TVE_REG(0x3E10)
190
+#define TVE_LUMA_FILTER1		TVE_REG(0x3E14)
191
+#define TVE_LUMA_FILTER2		TVE_REG(0x3E18)
192
+#define TVE_LUMA_FILTER3		TVE_REG(0x3E1C)
193
+#define TVE_LUMA_FILTER4		TVE_REG(0x3E20)
194
+#define TVE_LUMA_FILTER5		TVE_REG(0x3E24)
195
+#define TVE_LUMA_FILTER6		TVE_REG(0x3E28)
196
+#define TVE_LUMA_FILTER7		TVE_REG(0x3E2C)
197
+#define TVE_LUMA_FILTER8		TVE_REG(0x3E30)
198
+#define TVE_IMAGE_POSITION		TVE_REG(0x3E34)
199
+#define TVE_ROUTING			TVE_REG(0x3E38)
200
+#define TVE_SYNC_ADJUST			TVE_REG(0x3E50)
201
+#define TVE_STATUS			TVE_REG(0x3E54)
202
+#define TVE_CTRL			TVE_REG(0x3E68)
203
+#define TVE_INTR_STATUS			TVE_REG(0x3E6C)
204
+#define TVE_INTR_EN			TVE_REG(0x3E70)
205
+#define TVE_INTR_CLR			TVE_REG(0x3E74)
206
+#define TVE_COLOR_BUSRT_SAT		TVE_REG(0x3E78)
207
+#define TVE_CHROMA_BANDWIDTH		TVE_REG(0x3E8C)
208
+#define TVE_BRIGHTNESS_CONTRAST		TVE_REG(0x3E90)
209
+#define TVE_ID				TVE_REG(0x3E98)
210
+#define TVE_REVISION			TVE_REG(0x3E9C)
211
+#define TVE_CLAMP			TVE_REG(0x3EA0)
212
+#define TVE_MAX_REGISTER		TVE_CLAMP
213
+
214
+/* RK630 IRQ Definitions */
215
+#define RK630_IRQ_RTC_ALARM		0
216
+#define RK630_IRQ_SYS_INT		1
217
+
218
+#define RK630_IRQ_RTC_ALARM_MSK		BIT(7)
219
+#define RK630_IRQ_SYS_MSK		BIT(4)
163
220
 
164
221
 struct rk630 {
165
222
 	struct device *dev;
..
..
@@ -167,9 +224,14 @@
167
224
 	struct regmap *grf;
168
225
 	struct regmap *cru;
169
226
 	struct regmap *tve;
227
+	struct regmap *rtc;
170
228
 	struct gpio_desc *reset_gpio;
229
+	int irq;
230
+	struct regmap_irq_chip_data *irq_data;
231
+	const struct regmap_irq_chip *regmap_irq_chip;
171
232
 };
172
233
 
234
+extern const struct regmap_config rk630_rtc_regmap_config;
173
235
 extern const struct regmap_config rk630_grf_regmap_config;
174
236
 extern const struct regmap_config rk630_cru_regmap_config;
175
237
 extern const struct regmap_config rk630_tve_regmap_config;