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2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390 
 kernel/include/linux/coresight.h
....@@ -7,6 +7,7 @@
77 #define _LINUX_CORESIGHT_H
88 
99 #include <linux/device.h>
10
+#include <linux/io.h>
1011 #include <linux/perf_event.h>
1112 #include <linux/sched.h>
1213 
....@@ -41,12 +42,15 @@
4142 	CORESIGHT_DEV_TYPE_LINKSINK,
4243 	CORESIGHT_DEV_TYPE_SOURCE,
4344 	CORESIGHT_DEV_TYPE_HELPER,
45
+	CORESIGHT_DEV_TYPE_ECT,
4446 };
4547 
4648 enum coresight_dev_subtype_sink {
4749 	CORESIGHT_DEV_SUBTYPE_SINK_NONE,
4850 	CORESIGHT_DEV_SUBTYPE_SINK_PORT,
4951 	CORESIGHT_DEV_SUBTYPE_SINK_BUFFER,
52
+	CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM,
53
+	CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM,
5054 };
5155 
5256 enum coresight_dev_subtype_link {
....@@ -68,6 +72,12 @@
6872 	CORESIGHT_DEV_SUBTYPE_HELPER_CATU,
6973 };
7074 
75
+/* Embedded Cross Trigger (ECT) sub-types */
76
+enum coresight_dev_subtype_ect {
77
+	CORESIGHT_DEV_SUBTYPE_ECT_NONE,
78
+	CORESIGHT_DEV_SUBTYPE_ECT_CTI,
79
+};
80
+
7181 /**
7282  * union coresight_dev_subtype - further characterisation of a type
7383  * @sink_subtype:	type of sink this component is, as defined
....@@ -78,6 +88,8 @@
7888  *			by @coresight_dev_subtype_source.
7989  * @helper_subtype:	type of helper this component is, as defined
8090  *			by @coresight_dev_subtype_helper.
91
+ * @ect_subtype:        type of cross trigger this component is, as
92
+ *			defined by @coresight_dev_subtype_ect
8193  */
8294 union coresight_dev_subtype {
8395 	/* We have some devices which acts as LINK and SINK */
....@@ -87,39 +99,61 @@
8799 	};
88100 	enum coresight_dev_subtype_source source_subtype;
89101 	enum coresight_dev_subtype_helper helper_subtype;
102
+	enum coresight_dev_subtype_ect ect_subtype;
90103 };
91104 
92105 /**
93
- * struct coresight_platform_data - data harvested from the DT specification
94
- * @cpu:	the CPU a source belongs to. Only applicable for ETM/PTMs.
95
- * @name:	name of the component as shown under sysfs.
96
- * @nr_inport:	number of input ports for this component.
97
- * @outports:	list of remote endpoint port number.
98
- * @child_names:name of all child components connected to this device.
99
- * @child_ports:child component port number the current component is
100
-		connected  to.
101
- * @nr_outport:	number of output ports for this component.
106
+ * struct coresight_platform_data - data harvested from the firmware
107
+ * specification.
108
+ *
109
+ * @nr_inport:	Number of elements for the input connections.
110
+ * @nr_outport:	Number of elements for the output connections.
111
+ * @conns:	Sparse array of nr_outport connections from this component.
102112  */
103113 struct coresight_platform_data {
104
-	int cpu;
105
-	const char *name;
106114 	int nr_inport;
107
-	int *outports;
108
-	const char **child_names;
109
-	int *child_ports;
110115 	int nr_outport;
116
+	struct coresight_connection *conns;
111117 };
118
+
119
+/**
120
+ * struct csdev_access - Abstraction of a CoreSight device access.
121
+ *
122
+ * @io_mem	: True if the device has memory mapped I/O
123
+ * @base	: When io_mem == true, base address of the component
124
+ * @read	: Read from the given "offset" of the given instance.
125
+ * @write	: Write "val" to the given "offset".
126
+ */
127
+struct csdev_access {
128
+	bool io_mem;
129
+	union {
130
+		void __iomem *base;
131
+		struct {
132
+			u64 (*read)(u32 offset, bool relaxed, bool _64bit);
133
+			void (*write)(u64 val, u32 offset, bool relaxed,
134
+				      bool _64bit);
135
+		};
136
+	};
137
+};
138
+
139
+#define CSDEV_ACCESS_IOMEM(_addr)		\
140
+	((struct csdev_access)	{		\
141
+		.io_mem		= true,		\
142
+		.base		= (_addr),	\
143
+	})
112144 
113145 /**
114146  * struct coresight_desc - description of a component required from drivers
115147  * @type:	as defined by @coresight_dev_type.
116148  * @subtype:	as defined by @coresight_dev_subtype.
117149  * @ops:	generic operations for this component, as defined
118
-		by @coresight_ops.
150
+ *		by @coresight_ops.
119151  * @pdata:	platform data collected from DT.
120152  * @dev:	The device entity associated to this component.
121153  * @groups:	operations specific to this component. These will end up
122
-		in the component's sysfs sub-directory.
154
+ *		in the component's sysfs sub-directory.
155
+ * @name:	name for the coresight device, also shown under sysfs.
156
+ * @access:	Describe access to the device
123157  */
124158 struct coresight_desc {
125159 	enum coresight_dev_type type;
....@@ -128,48 +162,71 @@
128162 	struct coresight_platform_data *pdata;
129163 	struct device *dev;
130164 	const struct attribute_group **groups;
165
+	const char *name;
166
+	struct csdev_access access;
131167 };
132168 
133169 /**
134170  * struct coresight_connection - representation of a single connection
135171  * @outport:	a connection's output port number.
136
- * @chid_name:	remote component's name.
137172  * @child_port:	remote component's port number @output is connected to.
173
+ * @chid_fwnode: remote component's fwnode handle.
138174  * @child_dev:	a @coresight_device representation of the component
139175 		connected to @outport.
176
+ * @link: Representation of the connection as a sysfs link.
140177  */
141178 struct coresight_connection {
142179 	int outport;
143
-	const char *child_name;
144180 	int child_port;
181
+	struct fwnode_handle *child_fwnode;
145182 	struct coresight_device *child_dev;
183
+	struct coresight_sysfs_link *link;
184
+};
185
+
186
+/**
187
+ * struct coresight_sysfs_link - representation of a connection in sysfs.
188
+ * @orig:		Originating (master) coresight device for the link.
189
+ * @orig_name:		Name to use for the link orig->target.
190
+ * @target:		Target (slave) coresight device for the link.
191
+ * @target_name:	Name to use for the link target->orig.
192
+ */
193
+struct coresight_sysfs_link {
194
+	struct coresight_device *orig;
195
+	const char *orig_name;
196
+	struct coresight_device *target;
197
+	const char *target_name;
146198 };
147199 
148200 /**
149201  * struct coresight_device - representation of a device as used by the framework
150
- * @conns:	array of coresight_connections associated to this component.
151
- * @nr_inport:	number of input port associated to this component.
152
- * @nr_outport:	number of output port associated to this component.
202
+ * @pdata:	Platform data with device connections associated to this device.
153203  * @type:	as defined by @coresight_dev_type.
154204  * @subtype:	as defined by @coresight_dev_subtype.
155205  * @ops:	generic operations for this component, as defined
156
-		by @coresight_ops.
206
+ *		by @coresight_ops.
207
+ * @access:	Device i/o access abstraction for this device.
157208  * @dev:	The device entity associated to this component.
158209  * @refcnt:	keep track of what is in use.
159210  * @orphan:	true if the component has connections that haven't been linked.
160211  * @enable:	'true' if component is currently part of an active path.
161212  * @activated:	'true' only if a _sink_ has been activated.  A sink can be
162213  *		activated but not yet enabled.  Enabling for a _sink_
163
- *		appens when a source has been selected for that it.
214
+ *		happens when a source has been selected and a path is enabled
215
+ *		from source to that sink.
164216  * @ea:		Device attribute for sink representation under PMU directory.
217
+ * @def_sink:	cached reference to default sink found for this device.
218
+ * @ect_dev:	Associated cross trigger device. Not part of the trace data
219
+ *		path or connections.
220
+ * @nr_links:   number of sysfs links created to other components from this
221
+ *		device. These will appear in the "connections" group.
222
+ * @has_conns_grp: Have added a "connections" group for sysfs links.
165223  */
166224 struct coresight_device {
167
-	struct coresight_connection *conns;
168
-	int nr_inport;
169
-	int nr_outport;
225
+	struct coresight_platform_data *pdata;
170226 	enum coresight_dev_type type;
171227 	union coresight_dev_subtype subtype;
172228 	const struct coresight_ops *ops;
229
+	struct csdev_access access;
173230 	struct device dev;
174231 	atomic_t *refcnt;
175232 	bool orphan;
....@@ -177,7 +234,36 @@
177234 	/* sink specific fields */
178235 	bool activated;	/* true only if a sink is part of a path */
179236 	struct dev_ext_attribute *ea;
237
+	struct coresight_device *def_sink;
238
+	/* cross trigger handling */
239
+	struct coresight_device *ect_dev;
240
+	/* sysfs links between components */
241
+	int nr_links;
242
+	bool has_conns_grp;
243
+	bool ect_enabled; /* true only if associated ect device is enabled */
180244 };
245
+
246
+/*
247
+ * coresight_dev_list - Mapping for devices to "name" index for device
248
+ * names.
249
+ *
250
+ * @nr_idx:		Number of entries already allocated.
251
+ * @pfx:		Prefix pattern for device name.
252
+ * @fwnode_list:	Array of fwnode_handles associated with each allocated
253
+ *			index, upto nr_idx entries.
254
+ */
255
+struct coresight_dev_list {
256
+	int			nr_idx;
257
+	const char		*pfx;
258
+	struct fwnode_handle	**fwnode_list;
259
+};
260
+
261
+#define DEFINE_CORESIGHT_DEVLIST(var, dev_pfx)				\
262
+static struct coresight_dev_list (var) = {				\
263
+						.pfx = dev_pfx,		\
264
+						.nr_idx = 0,		\
265
+						.fwnode_list = NULL,	\
266
+}
181267 
182268 #define to_coresight_device(d) container_of(d, struct coresight_device, dev)
183269 
....@@ -185,6 +271,7 @@
185271 #define sink_ops(csdev)		csdev->ops->sink_ops
186272 #define link_ops(csdev)		csdev->ops->link_ops
187273 #define helper_ops(csdev)	csdev->ops->helper_ops
274
+#define ect_ops(csdev)		csdev->ops->ect_ops
188275 
189276 /**
190277  * struct coresight_ops_sink - basic operations for a sink
....@@ -251,29 +338,165 @@
251338 	int (*disable)(struct coresight_device *csdev, void *data);
252339 };
253340 
341
+/**
342
+ * struct coresight_ops_ect - Ops for an embedded cross trigger device
343
+ *
344
+ * @enable	: Enable the device
345
+ * @disable	: Disable the device
346
+ */
347
+struct coresight_ops_ect {
348
+	int (*enable)(struct coresight_device *csdev);
349
+	int (*disable)(struct coresight_device *csdev);
350
+};
351
+
254352 struct coresight_ops {
255353 	const struct coresight_ops_sink *sink_ops;
256354 	const struct coresight_ops_link *link_ops;
257355 	const struct coresight_ops_source *source_ops;
258356 	const struct coresight_ops_helper *helper_ops;
357
+	const struct coresight_ops_ect *ect_ops;
259358 };
260359 
261
-#ifdef CONFIG_CORESIGHT
360
+#if IS_ENABLED(CONFIG_CORESIGHT)
361
+
362
+static inline u32 csdev_access_relaxed_read32(struct csdev_access *csa,
363
+					      u32 offset)
364
+{
365
+	if (likely(csa->io_mem))
366
+		return readl_relaxed(csa->base + offset);
367
+
368
+	return csa->read(offset, true, false);
369
+}
370
+
371
+static inline u32 csdev_access_read32(struct csdev_access *csa, u32 offset)
372
+{
373
+	if (likely(csa->io_mem))
374
+		return readl(csa->base + offset);
375
+
376
+	return csa->read(offset, false, false);
377
+}
378
+
379
+static inline void csdev_access_relaxed_write32(struct csdev_access *csa,
380
+						u32 val, u32 offset)
381
+{
382
+	if (likely(csa->io_mem))
383
+		writel_relaxed(val, csa->base + offset);
384
+	else
385
+		csa->write(val, offset, true, false);
386
+}
387
+
388
+static inline void csdev_access_write32(struct csdev_access *csa, u32 val, u32 offset)
389
+{
390
+	if (likely(csa->io_mem))
391
+		writel(val, csa->base + offset);
392
+	else
393
+		csa->write(val, offset, false, false);
394
+}
395
+
396
+#ifdef CONFIG_64BIT
397
+
398
+static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa,
399
+					      u32 offset)
400
+{
401
+	if (likely(csa->io_mem))
402
+		return readq_relaxed(csa->base + offset);
403
+
404
+	return csa->read(offset, true, true);
405
+}
406
+
407
+static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset)
408
+{
409
+	if (likely(csa->io_mem))
410
+		return readq(csa->base + offset);
411
+
412
+	return csa->read(offset, false, true);
413
+}
414
+
415
+static inline void csdev_access_relaxed_write64(struct csdev_access *csa,
416
+						u64 val, u32 offset)
417
+{
418
+	if (likely(csa->io_mem))
419
+		writeq_relaxed(val, csa->base + offset);
420
+	else
421
+		csa->write(val, offset, true, true);
422
+}
423
+
424
+static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset)
425
+{
426
+	if (likely(csa->io_mem))
427
+		writeq(val, csa->base + offset);
428
+	else
429
+		csa->write(val, offset, false, true);
430
+}
431
+
432
+#else	/* !CONFIG_64BIT */
433
+
434
+static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa,
435
+					      u32 offset)
436
+{
437
+	WARN_ON(1);
438
+	return 0;
439
+}
440
+
441
+static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset)
442
+{
443
+	WARN_ON(1);
444
+	return 0;
445
+}
446
+
447
+static inline void csdev_access_relaxed_write64(struct csdev_access *csa,
448
+						u64 val, u32 offset)
449
+{
450
+	WARN_ON(1);
451
+}
452
+
453
+static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset)
454
+{
455
+	WARN_ON(1);
456
+}
457
+#endif	/* CONFIG_64BIT */
458
+
459
+static inline bool coresight_is_percpu_source(struct coresight_device *csdev)
460
+{
461
+	return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SOURCE) &&
462
+	       (csdev->subtype.source_subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_PROC);
463
+}
464
+
465
+static inline bool coresight_is_percpu_sink(struct coresight_device *csdev)
466
+{
467
+	return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SINK) &&
468
+	       (csdev->subtype.sink_subtype == CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM);
469
+}
470
+
262471 extern struct coresight_device *
263472 coresight_register(struct coresight_desc *desc);
264473 extern void coresight_unregister(struct coresight_device *csdev);
265474 extern int coresight_enable(struct coresight_device *csdev);
266475 extern void coresight_disable(struct coresight_device *csdev);
267
-extern int coresight_timeout(void __iomem *addr, u32 offset,
476
+extern int coresight_timeout(struct csdev_access *csa, u32 offset,
268477 			     int position, int value);
269478 
270
-extern int coresight_claim_device(void __iomem *base);
271
-extern int coresight_claim_device_unlocked(void __iomem *base);
479
+extern int coresight_claim_device(struct coresight_device *csdev);
480
+extern int coresight_claim_device_unlocked(struct coresight_device *csdev);
272481 
273
-extern void coresight_disclaim_device(void __iomem *base);
274
-extern void coresight_disclaim_device_unlocked(void __iomem *base);
482
+extern void coresight_disclaim_device(struct coresight_device *csdev);
483
+extern void coresight_disclaim_device_unlocked(struct coresight_device *csdev);
484
+extern char *coresight_alloc_device_name(struct coresight_dev_list *devs,
485
+					 struct device *dev);
275486 
276487 extern bool coresight_loses_context_with_cpu(struct device *dev);
488
+
489
+u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset);
490
+u32 coresight_read32(struct coresight_device *csdev, u32 offset);
491
+void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset);
492
+void coresight_relaxed_write32(struct coresight_device *csdev,
493
+			       u32 val, u32 offset);
494
+u64 coresight_relaxed_read64(struct coresight_device *csdev, u32 offset);
495
+u64 coresight_read64(struct coresight_device *csdev, u32 offset);
496
+void coresight_relaxed_write64(struct coresight_device *csdev,
497
+			       u64 val, u32 offset);
498
+void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset);
499
+
277500 #else
278501 static inline struct coresight_device *
279502 coresight_register(struct coresight_desc *desc) { return NULL; }
....@@ -281,37 +504,78 @@
281504 static inline int
282505 coresight_enable(struct coresight_device *csdev) { return -ENOSYS; }
283506 static inline void coresight_disable(struct coresight_device *csdev) {}
284
-static inline int coresight_timeout(void __iomem *addr, u32 offset,
285
-				     int position, int value) { return 1; }
286
-static inline int coresight_claim_device_unlocked(void __iomem *base)
507
+
508
+static inline int coresight_timeout(struct csdev_access *csa, u32 offset,
509
+				    int position, int value)
510
+{
511
+	return 1;
512
+}
513
+
514
+static inline int coresight_claim_device_unlocked(struct coresight_device *csdev)
287515 {
288516 	return -EINVAL;
289517 }
290518 
291
-static inline int coresight_claim_device(void __iomem *base)
519
+static inline int coresight_claim_device(struct coresight_device *csdev)
292520 {
293521 	return -EINVAL;
294522 }
295523 
296
-static inline void coresight_disclaim_device(void __iomem *base) {}
297
-static inline void coresight_disclaim_device_unlocked(void __iomem *base) {}
524
+static inline void coresight_disclaim_device(struct coresight_device *csdev) {}
525
+static inline void coresight_disclaim_device_unlocked(struct coresight_device *csdev) {}
298526 
299527 static inline bool coresight_loses_context_with_cpu(struct device *dev)
300528 {
301529 	return false;
302530 }
303
-#endif
304531 
305
-#ifdef CONFIG_OF
306
-extern int of_coresight_get_cpu(const struct device_node *node);
307
-extern struct coresight_platform_data *
308
-of_get_coresight_platform_data(struct device *dev,
309
-			       const struct device_node *node);
310
-#else
311
-static inline int of_coresight_get_cpu(const struct device_node *node)
312
-{ return 0; }
313
-static inline struct coresight_platform_data *of_get_coresight_platform_data(
314
-	struct device *dev, const struct device_node *node) { return NULL; }
315
-#endif
532
+static inline u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset)
533
+{
534
+	WARN_ON_ONCE(1);
535
+	return 0;
536
+}
316537 
317
-#endif
538
+static inline u32 coresight_read32(struct coresight_device *csdev, u32 offset)
539
+{
540
+	WARN_ON_ONCE(1);
541
+	return 0;
542
+}
543
+
544
+static inline void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset)
545
+{
546
+}
547
+
548
+static inline void coresight_relaxed_write32(struct coresight_device *csdev,
549
+					     u32 val, u32 offset)
550
+{
551
+}
552
+
553
+static inline u64 coresight_relaxed_read64(struct coresight_device *csdev,
554
+					   u32 offset)
555
+{
556
+	WARN_ON_ONCE(1);
557
+	return 0;
558
+}
559
+
560
+static inline u64 coresight_read64(struct coresight_device *csdev, u32 offset)
561
+{
562
+	WARN_ON_ONCE(1);
563
+	return 0;
564
+}
565
+
566
+static inline void coresight_relaxed_write64(struct coresight_device *csdev,
567
+					     u64 val, u32 offset)
568
+{
569
+}
570
+
571
+static inline void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset)
572
+{
573
+}
574
+
575
+#endif		/* IS_ENABLED(CONFIG_CORESIGHT) */
576
+
577
+extern int coresight_get_cpu(struct device *dev);
578
+
579
+struct coresight_platform_data *coresight_get_platform_data(struct device *dev);
580
+
581
+#endif		/* _LINUX_COREISGHT_H */