change wifi driver to cypress

hc

2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390

 kernel/include/linux/clk/at91_pmc.h
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@@ -1,3 +1,4 @@
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+/* SPDX-License-Identifier: GPL-2.0-or-later */
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 /*
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  * include/linux/clk/at91_pmc.h
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  *
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@@ -6,15 +7,13 @@
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  *
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  * Power Management Controller (PMC) - System peripherals registers.
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  * Based on AT91RM9200 datasheet revision E.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License as published by
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- * the Free Software Foundation; either version 2 of the License, or
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- * (at your option) any later version.
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  */
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 #ifndef AT91_PMC_H
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 #define AT91_PMC_H
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+
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+#define AT91_PMC_V1		(1)			/* PMC version 1 */
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+#define AT91_PMC_V2		(2)			/* PMC version 2 [SAM9X60] */
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 #define	AT91_PMC_SCER		0x00			/* System Clock Enable Register */
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 #define	AT91_PMC_SCDR		0x04			/* System Clock Disable Register */
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@@ -34,15 +33,34 @@
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 #define		AT91_PMC_HCK0		(1 << 16)		/* AHB Clock (USB host) [AT91SAM9261 only] */
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 #define		AT91_PMC_HCK1		(1 << 17)		/* AHB Clock (LCD) [AT91SAM9261 only] */
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+#define AT91_PMC_PLL_CTRL0		0x0C		/* PLL Control Register 0 [for SAM9X60] */
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+#define		AT91_PMC_PLL_CTRL0_ENPLL	(1 << 28)	/* Enable PLL */
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+#define		AT91_PMC_PLL_CTRL0_ENPLLCK	(1 << 29)	/* Enable PLL clock for PMC */
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+#define		AT91_PMC_PLL_CTRL0_ENLOCK	(1 << 31)	/* Enable PLL lock */
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+
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+#define AT91_PMC_PLL_CTRL1		0x10		/* PLL Control Register 1 [for SAM9X60] */
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+
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 #define	AT91_PMC_PCER		0x10			/* Peripheral Clock Enable Register */
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 #define	AT91_PMC_PCDR		0x14			/* Peripheral Clock Disable Register */
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 #define	AT91_PMC_PCSR		0x18			/* Peripheral Clock Status Register */
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+
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+#define AT91_PMC_PLL_ACR	0x18			/* PLL Analog Control Register [for SAM9X60] */
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+#define		AT91_PMC_PLL_ACR_DEFAULT_UPLL	0x12020010UL	/* Default PLL ACR value for UPLL */
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+#define		AT91_PMC_PLL_ACR_DEFAULT_PLLA	0x00020010UL	/* Default PLL ACR value for PLLA */
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+#define		AT91_PMC_PLL_ACR_UTMIVR		(1 << 12)	/* UPLL Voltage regulator Control */
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+#define		AT91_PMC_PLL_ACR_UTMIBG		(1 << 13)	/* UPLL Bandgap Control */
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 #define	AT91_CKGR_UCKR		0x1C			/* UTMI Clock Register [some SAM9] */
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 #define		AT91_PMC_UPLLEN		(1   << 16)		/* UTMI PLL Enable */
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 #define		AT91_PMC_UPLLCOUNT	(0xf << 20)		/* UTMI PLL Start-up Time */
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 #define		AT91_PMC_BIASEN		(1   << 24)		/* UTMI BIAS Enable */
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 #define		AT91_PMC_BIASCOUNT	(0xf << 28)		/* UTMI BIAS Start-up Time */
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+
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+#define AT91_PMC_PLL_UPDT		0x1C		/* PMC PLL update register [for SAM9X60] */
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+#define		AT91_PMC_PLL_UPDT_UPDATE	(1 << 8)	/* Update PLL settings */
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+#define		AT91_PMC_PLL_UPDT_ID		(1 << 0)	/* PLL ID */
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+#define		AT91_PMC_PLL_UPDT_ID_MSK	(0xf)		/* PLL ID mask */
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+#define		AT91_PMC_PLL_UPDT_STUPTIM	(0xff << 16)	/* Startup time */
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 #define	AT91_CKGR_MOR		0x20			/* Main Oscillator Register [not on SAM9RL] */
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 #define		AT91_PMC_MOSCEN		(1    <<  0)		/* Main Oscillator Enable */
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@@ -73,6 +91,8 @@
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 #define			AT91_PMC_USBDIV_2		(1 << 28)
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 #define			AT91_PMC_USBDIV_4		(2 << 28)
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 #define		AT91_PMC_USB96M		(1     << 28)		/* Divider by 2 Enable (PLLB only) */
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+
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+#define AT91_PMC_CPU_CKR	0x28			/* CPU Clock Register */
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 #define	AT91_PMC_MCKR		0x30			/* Master Clock Register */
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 #define		AT91_PMC_CSS		(3 <<  0)		/* Master Clock Selection */
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@@ -117,6 +137,8 @@
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 #define			AT91_PMC_PLLADIV2_ON		(1 << 12)
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 #define		AT91_PMC_H32MXDIV	BIT(24)
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+#define AT91_PMC_XTALF		0x34			/* Main XTAL Frequency Register [SAMA7G5 only] */
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+
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 #define	AT91_PMC_USB		0x38			/* USB Clock Register [some SAM9 only] */
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 #define		AT91_PMC_USBS		(0x1 <<  0)		/* USB OHCI Input clock selection */
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 #define			AT91_PMC_USBS_PLLA		(0 << 0)
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@@ -155,10 +177,12 @@
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 #define		AT91_PMC_MOSCRCS	(1 << 17)		/* Main On-Chip RC [some SAM9] */
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 #define		AT91_PMC_CFDEV		(1 << 18)		/* Clock Failure Detector Event [some SAM9] */
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 #define		AT91_PMC_GCKRDY		(1 << 24)		/* Generated Clocks */
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+#define		AT91_PMC_MCKXRDY	(1 << 26)		/* Master Clock x [x=1..4] Ready Status */
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 #define	AT91_PMC_IMR		0x6c			/* Interrupt Mask Register */
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 #define AT91_PMC_FSMR		0x70		/* Fast Startup Mode Register */
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 #define AT91_PMC_FSTT(n)	BIT(n)
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+#define AT91_PMC_RTTAL		BIT(16)
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 #define AT91_PMC_RTCAL		BIT(17)		/* RTC Alarm Enable */
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 #define AT91_PMC_USBAL		BIT(18)		/* USB Resume Enable */
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 #define AT91_PMC_SDMMC_CD	BIT(19)		/* SDMMC Card Detect Enable */
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@@ -181,22 +205,16 @@
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 #define		AT91_PMC_WPVS		(0x1  <<  0)		/* Write Protect Violation Status */
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 #define		AT91_PMC_WPVSRC		(0xffff  <<  8)		/* Write Protect Violation Source */
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+#define AT91_PMC_PLL_ISR0	0xEC			/* PLL Interrupt Status Register 0 [SAM9X60 only] */
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+
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 #define AT91_PMC_PCER1		0x100			/* Peripheral Clock Enable Register 1 [SAMA5 only]*/
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 #define AT91_PMC_PCDR1		0x104			/* Peripheral Clock Enable Register 1 */
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 #define AT91_PMC_PCSR1		0x108			/* Peripheral Clock Enable Register 1 */
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 #define AT91_PMC_PCR		0x10c			/* Peripheral Control Register [some SAM9 and SAMA5] */
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 #define		AT91_PMC_PCR_PID_MASK		0x3f
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-#define		AT91_PMC_PCR_GCKCSS_OFFSET	8
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-#define		AT91_PMC_PCR_GCKCSS_MASK	(0x7  << AT91_PMC_PCR_GCKCSS_OFFSET)
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-#define		AT91_PMC_PCR_GCKCSS(n)		((n)  << AT91_PMC_PCR_GCKCSS_OFFSET)	/* GCK Clock Source Selection */
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 #define		AT91_PMC_PCR_CMD		(0x1  <<  12)				/* Command (read=0, write=1) */
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-#define		AT91_PMC_PCR_DIV_OFFSET		16
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-#define		AT91_PMC_PCR_DIV_MASK		(0x3  << AT91_PMC_PCR_DIV_OFFSET)
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-#define		AT91_PMC_PCR_DIV(n)		((n)  << AT91_PMC_PCR_DIV_OFFSET)	/* Divisor Value */
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-#define		AT91_PMC_PCR_GCKDIV_OFFSET	20
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-#define		AT91_PMC_PCR_GCKDIV_MASK	(0xff  << AT91_PMC_PCR_GCKDIV_OFFSET)
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-#define		AT91_PMC_PCR_GCKDIV(n)		((n)  << AT91_PMC_PCR_GCKDIV_OFFSET)	/* Generated Clock Divisor Value */
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+#define		AT91_PMC_PCR_GCKDIV_MASK	GENMASK(27, 20)
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 #define		AT91_PMC_PCR_EN			(0x1  <<  28)				/* Enable */
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 #define		AT91_PMC_PCR_GCKEN		(0x1  <<  29)				/* GCK Enable */
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