forked from ~ljy/RK356X_SDK_RELEASE

blame | history | patch | commit | commitdiff
hc
2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390 
 kernel/include/dt-bindings/iio/qcom,spmi-vadc.h
....@@ -1,14 +1,6 @@
1
+/* SPDX-License-Identifier: GPL-2.0 */
12 /*
2
- * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
3
- *
4
- * This program is free software; you can redistribute it and/or modify
5
- * it under the terms of the GNU General Public License version 2 and
6
- * only version 2 as published by the Free Software Foundation.
7
- *
8
- * This program is distributed in the hope that it will be useful
9
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
10
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11
- * GNU General Public License for more details.
3
+ * Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved.
124  */
135 
146 #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H
....@@ -116,4 +108,193 @@
116108 #define VADC_LR_MUX10_PU1_PU2_AMUX_USB_ID	0xf9
117109 #define VADC_LR_MUX3_BUF_PU1_PU2_XO_THERM	0xfc
118110 
111
+/* ADC channels for SPMI PMIC5 */
112
+
113
+#define ADC5_REF_GND				0x00
114
+#define ADC5_1P25VREF				0x01
115
+#define ADC5_VREF_VADC				0x02
116
+#define ADC5_VREF_VADC5_DIV_3			0x82
117
+#define ADC5_VPH_PWR				0x83
118
+#define ADC5_VBAT_SNS				0x84
119
+#define ADC5_VCOIN				0x85
120
+#define ADC5_DIE_TEMP				0x06
121
+#define ADC5_USB_IN_I				0x07
122
+#define ADC5_USB_IN_V_16			0x08
123
+#define ADC5_CHG_TEMP				0x09
124
+#define ADC5_BAT_THERM				0x0a
125
+#define ADC5_BAT_ID				0x0b
126
+#define ADC5_XO_THERM				0x0c
127
+#define ADC5_AMUX_THM1				0x0d
128
+#define ADC5_AMUX_THM2				0x0e
129
+#define ADC5_AMUX_THM3				0x0f
130
+#define ADC5_AMUX_THM4				0x10
131
+#define ADC5_AMUX_THM5				0x11
132
+#define ADC5_GPIO1				0x12
133
+#define ADC5_GPIO2				0x13
134
+#define ADC5_GPIO3				0x14
135
+#define ADC5_GPIO4				0x15
136
+#define ADC5_GPIO5				0x16
137
+#define ADC5_GPIO6				0x17
138
+#define ADC5_GPIO7				0x18
139
+#define ADC5_SBUx				0x99
140
+#define ADC5_MID_CHG_DIV6			0x1e
141
+#define ADC5_OFF				0xff
142
+
143
+/* 30k pull-up1 */
144
+#define ADC5_BAT_THERM_30K_PU			0x2a
145
+#define ADC5_BAT_ID_30K_PU			0x2b
146
+#define ADC5_XO_THERM_30K_PU			0x2c
147
+#define ADC5_AMUX_THM1_30K_PU			0x2d
148
+#define ADC5_AMUX_THM2_30K_PU			0x2e
149
+#define ADC5_AMUX_THM3_30K_PU			0x2f
150
+#define ADC5_AMUX_THM4_30K_PU			0x30
151
+#define ADC5_AMUX_THM5_30K_PU			0x31
152
+#define ADC5_GPIO1_30K_PU			0x32
153
+#define ADC5_GPIO2_30K_PU			0x33
154
+#define ADC5_GPIO3_30K_PU			0x34
155
+#define ADC5_GPIO4_30K_PU			0x35
156
+#define ADC5_GPIO5_30K_PU			0x36
157
+#define ADC5_GPIO6_30K_PU			0x37
158
+#define ADC5_GPIO7_30K_PU			0x38
159
+#define ADC5_SBUx_30K_PU			0x39
160
+
161
+/* 100k pull-up2 */
162
+#define ADC5_BAT_THERM_100K_PU			0x4a
163
+#define ADC5_BAT_ID_100K_PU			0x4b
164
+#define ADC5_XO_THERM_100K_PU			0x4c
165
+#define ADC5_AMUX_THM1_100K_PU			0x4d
166
+#define ADC5_AMUX_THM2_100K_PU			0x4e
167
+#define ADC5_AMUX_THM3_100K_PU			0x4f
168
+#define ADC5_AMUX_THM4_100K_PU			0x50
169
+#define ADC5_AMUX_THM5_100K_PU			0x51
170
+#define ADC5_GPIO1_100K_PU			0x52
171
+#define ADC5_GPIO2_100K_PU			0x53
172
+#define ADC5_GPIO3_100K_PU			0x54
173
+#define ADC5_GPIO4_100K_PU			0x55
174
+#define ADC5_GPIO5_100K_PU			0x56
175
+#define ADC5_GPIO6_100K_PU			0x57
176
+#define ADC5_GPIO7_100K_PU			0x58
177
+#define ADC5_SBUx_100K_PU			0x59
178
+
179
+/* 400k pull-up3 */
180
+#define ADC5_BAT_THERM_400K_PU			0x6a
181
+#define ADC5_BAT_ID_400K_PU			0x6b
182
+#define ADC5_XO_THERM_400K_PU			0x6c
183
+#define ADC5_AMUX_THM1_400K_PU			0x6d
184
+#define ADC5_AMUX_THM2_400K_PU			0x6e
185
+#define ADC5_AMUX_THM3_400K_PU			0x6f
186
+#define ADC5_AMUX_THM4_400K_PU			0x70
187
+#define ADC5_AMUX_THM5_400K_PU			0x71
188
+#define ADC5_GPIO1_400K_PU			0x72
189
+#define ADC5_GPIO2_400K_PU			0x73
190
+#define ADC5_GPIO3_400K_PU			0x74
191
+#define ADC5_GPIO4_400K_PU			0x75
192
+#define ADC5_GPIO5_400K_PU			0x76
193
+#define ADC5_GPIO6_400K_PU			0x77
194
+#define ADC5_GPIO7_400K_PU			0x78
195
+#define ADC5_SBUx_400K_PU			0x79
196
+
197
+/* 1/3 Divider */
198
+#define ADC5_GPIO1_DIV3				0x92
199
+#define ADC5_GPIO2_DIV3				0x93
200
+#define ADC5_GPIO3_DIV3				0x94
201
+#define ADC5_GPIO4_DIV3				0x95
202
+#define ADC5_GPIO5_DIV3				0x96
203
+#define ADC5_GPIO6_DIV3				0x97
204
+#define ADC5_GPIO7_DIV3				0x98
205
+#define ADC5_SBUx_DIV3				0x99
206
+
207
+/* Current and combined current/voltage channels */
208
+#define ADC5_INT_EXT_ISENSE			0xa1
209
+#define ADC5_PARALLEL_ISENSE			0xa5
210
+#define ADC5_CUR_REPLICA_VDS			0xa7
211
+#define ADC5_CUR_SENS_BATFET_VDS_OFFSET		0xa9
212
+#define ADC5_CUR_SENS_REPLICA_VDS_OFFSET	0xab
213
+#define ADC5_EXT_SENS_OFFSET			0xad
214
+
215
+#define ADC5_INT_EXT_ISENSE_VBAT_VDATA		0xb0
216
+#define ADC5_INT_EXT_ISENSE_VBAT_IDATA		0xb1
217
+#define ADC5_EXT_ISENSE_VBAT_VDATA		0xb2
218
+#define ADC5_EXT_ISENSE_VBAT_IDATA		0xb3
219
+#define ADC5_PARALLEL_ISENSE_VBAT_VDATA		0xb4
220
+#define ADC5_PARALLEL_ISENSE_VBAT_IDATA		0xb5
221
+
222
+#define ADC5_MAX_CHANNEL			0xc0
223
+
224
+/* ADC channels for ADC for PMIC7 */
225
+
226
+#define ADC7_REF_GND				0x00
227
+#define ADC7_1P25VREF				0x01
228
+#define ADC7_VREF_VADC				0x02
229
+#define ADC7_DIE_TEMP				0x03
230
+
231
+#define ADC7_AMUX_THM1				0x04
232
+#define ADC7_AMUX_THM2				0x05
233
+#define ADC7_AMUX_THM3				0x06
234
+#define ADC7_AMUX_THM4				0x07
235
+#define ADC7_AMUX_THM5				0x08
236
+#define ADC7_AMUX_THM6				0x09
237
+#define ADC7_GPIO1				0x0a
238
+#define ADC7_GPIO2				0x0b
239
+#define ADC7_GPIO3				0x0c
240
+#define ADC7_GPIO4				0x0d
241
+
242
+#define ADC7_CHG_TEMP				0x10
243
+#define ADC7_USB_IN_V_16			0x11
244
+#define ADC7_VDC_16				0x12
245
+#define ADC7_CC1_ID				0x13
246
+#define ADC7_VREF_BAT_THERM			0x15
247
+#define ADC7_IIN_FB				0x17
248
+
249
+/* 30k pull-up1 */
250
+#define ADC7_AMUX_THM1_30K_PU			0x24
251
+#define ADC7_AMUX_THM2_30K_PU			0x25
252
+#define ADC7_AMUX_THM3_30K_PU			0x26
253
+#define ADC7_AMUX_THM4_30K_PU			0x27
254
+#define ADC7_AMUX_THM5_30K_PU			0x28
255
+#define ADC7_AMUX_THM6_30K_PU			0x29
256
+#define ADC7_GPIO1_30K_PU			0x2a
257
+#define ADC7_GPIO2_30K_PU			0x2b
258
+#define ADC7_GPIO3_30K_PU			0x2c
259
+#define ADC7_GPIO4_30K_PU			0x2d
260
+#define ADC7_CC1_ID_30K_PU			0x33
261
+
262
+/* 100k pull-up2 */
263
+#define ADC7_AMUX_THM1_100K_PU			0x44
264
+#define ADC7_AMUX_THM2_100K_PU			0x45
265
+#define ADC7_AMUX_THM3_100K_PU			0x46
266
+#define ADC7_AMUX_THM4_100K_PU			0x47
267
+#define ADC7_AMUX_THM5_100K_PU			0x48
268
+#define ADC7_AMUX_THM6_100K_PU			0x49
269
+#define ADC7_GPIO1_100K_PU			0x4a
270
+#define ADC7_GPIO2_100K_PU			0x4b
271
+#define ADC7_GPIO3_100K_PU			0x4c
272
+#define ADC7_GPIO4_100K_PU			0x4d
273
+#define ADC7_CC1_ID_100K_PU			0x53
274
+
275
+/* 400k pull-up3 */
276
+#define ADC7_AMUX_THM1_400K_PU			0x64
277
+#define ADC7_AMUX_THM2_400K_PU			0x65
278
+#define ADC7_AMUX_THM3_400K_PU			0x66
279
+#define ADC7_AMUX_THM4_400K_PU			0x67
280
+#define ADC7_AMUX_THM5_400K_PU			0x68
281
+#define ADC7_AMUX_THM6_400K_PU			0x69
282
+#define ADC7_GPIO1_400K_PU			0x6a
283
+#define ADC7_GPIO2_400K_PU			0x6b
284
+#define ADC7_GPIO3_400K_PU			0x6c
285
+#define ADC7_GPIO4_400K_PU			0x6d
286
+#define ADC7_CC1_ID_400K_PU			0x73
287
+
288
+/* 1/3 Divider */
289
+#define ADC7_GPIO1_DIV3				0x8a
290
+#define ADC7_GPIO2_DIV3				0x8b
291
+#define ADC7_GPIO3_DIV3				0x8c
292
+#define ADC7_GPIO4_DIV3				0x8d
293
+
294
+#define ADC7_VPH_PWR				0x8e
295
+#define ADC7_VBAT_SNS				0x8f
296
+
297
+#define ADC7_SBUx				0x94
298
+#define ADC7_VBAT_2S_MID			0x96
299
+
119300 #endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */