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| 1 | +/* SPDX-License-Identifier: GPL-2.0-only */ |
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1 | 2 | /* |
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2 | 3 | * linux/drivers/video/omap2/dss/dss.h |
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3 | 4 | * |
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.. | .. |
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6 | 7 | * |
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7 | 8 | * Some code and ideas taken from drivers/video/omap/ driver |
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8 | 9 | * by Imre Deak. |
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9 | | - * |
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10 | | - * This program is free software; you can redistribute it and/or modify it |
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11 | | - * under the terms of the GNU General Public License version 2 as published by |
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12 | | - * the Free Software Foundation. |
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13 | | - * |
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14 | | - * This program is distributed in the hope that it will be useful, but WITHOUT |
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15 | | - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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16 | | - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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17 | | - * more details. |
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18 | | - * |
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19 | | - * You should have received a copy of the GNU General Public License along with |
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20 | | - * this program. If not, see <http://www.gnu.org/licenses/>. |
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21 | 10 | */ |
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22 | 11 | |
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23 | 12 | #ifndef __OMAP2_DSS_H |
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.. | .. |
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98 | 87 | enum dss_dsi_content_type { |
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99 | 88 | DSS_DSI_CONTENT_DCS, |
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100 | 89 | DSS_DSI_CONTENT_GENERIC, |
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101 | | -}; |
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102 | | - |
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103 | | -enum dss_writeback_channel { |
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104 | | - DSS_WB_LCD1_MGR = 0, |
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105 | | - DSS_WB_LCD2_MGR = 1, |
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106 | | - DSS_WB_TV_MGR = 2, |
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107 | | - DSS_WB_OVL0 = 3, |
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108 | | - DSS_WB_OVL1 = 4, |
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109 | | - DSS_WB_OVL2 = 5, |
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110 | | - DSS_WB_OVL3 = 6, |
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111 | | - DSS_WB_LCD3_MGR = 7, |
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112 | 90 | }; |
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113 | 91 | |
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114 | 92 | enum dss_pll_id { |
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.. | .. |
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214 | 192 | int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask); |
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215 | 193 | void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask); |
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216 | 194 | int dss_set_min_bus_tput(struct device *dev, unsigned long tput); |
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217 | | -int dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *)); |
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| 195 | +void dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *)); |
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218 | 196 | |
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219 | 197 | /* display */ |
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220 | 198 | int dss_suspend_all_devices(void); |
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.. | .. |
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414 | 392 | struct dispc_clock_info *cinfo); |
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415 | 393 | void dispc_set_tv_pclk(unsigned long pclk); |
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416 | 394 | |
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417 | | -u32 dispc_wb_get_framedone_irq(void); |
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418 | | -bool dispc_wb_go_busy(void); |
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419 | | -void dispc_wb_go(void); |
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420 | | -void dispc_wb_enable(bool enable); |
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421 | | -bool dispc_wb_is_enabled(void); |
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422 | | -void dispc_wb_set_channel_in(enum dss_writeback_channel channel); |
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423 | | -int dispc_wb_setup(const struct omap_dss_writeback_info *wi, |
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424 | | - bool mem_to_mem, const struct omap_video_timings *timings); |
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425 | | - |
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426 | 395 | u32 dispc_read_irqstatus(void); |
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427 | 396 | void dispc_clear_irqstatus(u32 mask); |
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428 | 397 | u32 dispc_read_irqenable(void); |
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.. | .. |
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471 | 440 | |
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472 | 441 | int hdmi5_init_platform_driver(void) __init; |
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473 | 442 | void hdmi5_uninit_platform_driver(void); |
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474 | | - |
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475 | | -/* RFBI */ |
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476 | | -int rfbi_init_platform_driver(void) __init; |
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477 | | -void rfbi_uninit_platform_driver(void); |
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478 | 443 | |
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479 | 444 | |
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480 | 445 | #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS |
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