forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390 
 kernel/drivers/usb/phy/phy-tegra-usb.c
....@@ -9,54 +9,55 @@
99  *	Venu Byravarasu <vbyravarasu@nvidia.com>
1010  */
1111 
12
-#include <linux/resource.h>
1312 #include <linux/delay.h>
14
-#include <linux/slab.h>
1513 #include <linux/err.h>
1614 #include <linux/export.h>
17
-#include <linux/module.h>
18
-#include <linux/platform_device.h>
15
+#include <linux/gpio/consumer.h>
1916 #include <linux/iopoll.h>
20
-#include <linux/gpio.h>
17
+#include <linux/module.h>
2118 #include <linux/of.h>
2219 #include <linux/of_device.h>
23
-#include <linux/of_gpio.h>
24
-#include <linux/usb/otg.h>
25
-#include <linux/usb/ulpi.h>
26
-#include <linux/usb/of.h>
27
-#include <linux/usb/ehci_def.h>
28
-#include <linux/usb/tegra_usb_phy.h>
20
+#include <linux/platform_device.h>
21
+#include <linux/resource.h>
22
+#include <linux/slab.h>
23
+#include <linux/spinlock.h>
24
+
2925 #include <linux/regulator/consumer.h>
3026 
31
-#define ULPI_VIEWPORT		0x170
27
+#include <linux/usb/ehci_def.h>
28
+#include <linux/usb/of.h>
29
+#include <linux/usb/tegra_usb_phy.h>
30
+#include <linux/usb/ulpi.h>
31
+
32
+#define ULPI_VIEWPORT				0x170
3233 
3334 /* PORTSC PTS/PHCD bits, Tegra20 only */
34
-#define TEGRA_USB_PORTSC1				0x184
35
-#define TEGRA_USB_PORTSC1_PTS(x)			(((x) & 0x3) << 30)
36
-#define TEGRA_USB_PORTSC1_PHCD				(1 << 23)
35
+#define TEGRA_USB_PORTSC1			0x184
36
+#define TEGRA_USB_PORTSC1_PTS(x)		(((x) & 0x3) << 30)
37
+#define TEGRA_USB_PORTSC1_PHCD			BIT(23)
3738 
3839 /* HOSTPC1 PTS/PHCD bits, Tegra30 and above */
39
-#define TEGRA_USB_HOSTPC1_DEVLC		0x1b4
40
-#define TEGRA_USB_HOSTPC1_DEVLC_PTS(x)	(((x) & 0x7) << 29)
41
-#define TEGRA_USB_HOSTPC1_DEVLC_PHCD	(1 << 22)
40
+#define TEGRA_USB_HOSTPC1_DEVLC			0x1b4
41
+#define TEGRA_USB_HOSTPC1_DEVLC_PTS(x)		(((x) & 0x7) << 29)
42
+#define TEGRA_USB_HOSTPC1_DEVLC_PHCD		BIT(22)
4243 
4344 /* Bits of PORTSC1, which will get cleared by writing 1 into them */
4445 #define TEGRA_PORTSC1_RWC_BITS	(PORT_CSC | PORT_PEC | PORT_OCC)
4546 
46
-#define USB_SUSP_CTRL		0x400
47
-#define   USB_WAKE_ON_CNNT_EN_DEV	(1 << 3)
48
-#define   USB_WAKE_ON_DISCON_EN_DEV	(1 << 4)
49
-#define   USB_SUSP_CLR		(1 << 5)
50
-#define   USB_PHY_CLK_VALID	(1 << 7)
51
-#define   UTMIP_RESET			(1 << 11)
52
-#define   UHSIC_RESET			(1 << 11)
53
-#define   UTMIP_PHY_ENABLE		(1 << 12)
54
-#define   ULPI_PHY_ENABLE	(1 << 13)
55
-#define   USB_SUSP_SET		(1 << 14)
56
-#define   USB_WAKEUP_DEBOUNCE_COUNT(x)	(((x) & 0x7) << 16)
47
+#define USB_SUSP_CTRL				0x400
48
+#define   USB_WAKE_ON_CNNT_EN_DEV		BIT(3)
49
+#define   USB_WAKE_ON_DISCON_EN_DEV		BIT(4)
50
+#define   USB_SUSP_CLR				BIT(5)
51
+#define   USB_PHY_CLK_VALID			BIT(7)
52
+#define   UTMIP_RESET				BIT(11)
53
+#define   UHSIC_RESET				BIT(11)
54
+#define   UTMIP_PHY_ENABLE			BIT(12)
55
+#define   ULPI_PHY_ENABLE			BIT(13)
56
+#define   USB_SUSP_SET				BIT(14)
57
+#define   USB_WAKEUP_DEBOUNCE_COUNT(x)		(((x) & 0x7) << 16)
5758 
58
-#define USB1_LEGACY_CTRL	0x410
59
-#define   USB1_NO_LEGACY_MODE			(1 << 0)
59
+#define USB1_LEGACY_CTRL			0x410
60
+#define   USB1_NO_LEGACY_MODE			BIT(0)
6061 #define   USB1_VBUS_SENSE_CTL_MASK		(3 << 1)
6162 #define   USB1_VBUS_SENSE_CTL_VBUS_WAKEUP	(0 << 1)
6263 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
....@@ -64,94 +65,94 @@
6465 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD	(2 << 1)
6566 #define   USB1_VBUS_SENSE_CTL_A_SESS_VLD	(3 << 1)
6667 
67
-#define ULPI_TIMING_CTRL_0	0x424
68
-#define   ULPI_OUTPUT_PINMUX_BYP	(1 << 10)
69
-#define   ULPI_CLKOUT_PINMUX_BYP	(1 << 11)
68
+#define ULPI_TIMING_CTRL_0			0x424
69
+#define   ULPI_OUTPUT_PINMUX_BYP		BIT(10)
70
+#define   ULPI_CLKOUT_PINMUX_BYP		BIT(11)
7071 
71
-#define ULPI_TIMING_CTRL_1	0x428
72
-#define   ULPI_DATA_TRIMMER_LOAD	(1 << 0)
73
-#define   ULPI_DATA_TRIMMER_SEL(x)	(((x) & 0x7) << 1)
74
-#define   ULPI_STPDIRNXT_TRIMMER_LOAD	(1 << 16)
75
-#define   ULPI_STPDIRNXT_TRIMMER_SEL(x)	(((x) & 0x7) << 17)
76
-#define   ULPI_DIR_TRIMMER_LOAD		(1 << 24)
77
-#define   ULPI_DIR_TRIMMER_SEL(x)	(((x) & 0x7) << 25)
72
+#define ULPI_TIMING_CTRL_1			0x428
73
+#define   ULPI_DATA_TRIMMER_LOAD		BIT(0)
74
+#define   ULPI_DATA_TRIMMER_SEL(x)		(((x) & 0x7) << 1)
75
+#define   ULPI_STPDIRNXT_TRIMMER_LOAD		BIT(16)
76
+#define   ULPI_STPDIRNXT_TRIMMER_SEL(x)		(((x) & 0x7) << 17)
77
+#define   ULPI_DIR_TRIMMER_LOAD			BIT(24)
78
+#define   ULPI_DIR_TRIMMER_SEL(x)		(((x) & 0x7) << 25)
7879 
79
-#define UTMIP_PLL_CFG1		0x804
80
+#define UTMIP_PLL_CFG1				0x804
8081 #define   UTMIP_XTAL_FREQ_COUNT(x)		(((x) & 0xfff) << 0)
8182 #define   UTMIP_PLLU_ENABLE_DLY_COUNT(x)	(((x) & 0x1f) << 27)
8283 
83
-#define UTMIP_XCVR_CFG0		0x808
84
+#define UTMIP_XCVR_CFG0				0x808
8485 #define   UTMIP_XCVR_SETUP(x)			(((x) & 0xf) << 0)
8586 #define   UTMIP_XCVR_SETUP_MSB(x)		((((x) & 0x70) >> 4) << 22)
8687 #define   UTMIP_XCVR_LSRSLEW(x)			(((x) & 0x3) << 8)
8788 #define   UTMIP_XCVR_LSFSLEW(x)			(((x) & 0x3) << 10)
88
-#define   UTMIP_FORCE_PD_POWERDOWN		(1 << 14)
89
-#define   UTMIP_FORCE_PD2_POWERDOWN		(1 << 16)
90
-#define   UTMIP_FORCE_PDZI_POWERDOWN		(1 << 18)
91
-#define   UTMIP_XCVR_LSBIAS_SEL			(1 << 21)
89
+#define   UTMIP_FORCE_PD_POWERDOWN		BIT(14)
90
+#define   UTMIP_FORCE_PD2_POWERDOWN		BIT(16)
91
+#define   UTMIP_FORCE_PDZI_POWERDOWN		BIT(18)
92
+#define   UTMIP_XCVR_LSBIAS_SEL			BIT(21)
9293 #define   UTMIP_XCVR_HSSLEW(x)			(((x) & 0x3) << 4)
9394 #define   UTMIP_XCVR_HSSLEW_MSB(x)		((((x) & 0x1fc) >> 2) << 25)
9495 
95
-#define UTMIP_BIAS_CFG0		0x80c
96
-#define   UTMIP_OTGPD			(1 << 11)
97
-#define   UTMIP_BIASPD			(1 << 10)
98
-#define   UTMIP_HSSQUELCH_LEVEL(x)	(((x) & 0x3) << 0)
99
-#define   UTMIP_HSDISCON_LEVEL(x)	(((x) & 0x3) << 2)
100
-#define   UTMIP_HSDISCON_LEVEL_MSB(x)	((((x) & 0x4) >> 2) << 24)
96
+#define UTMIP_BIAS_CFG0				0x80c
97
+#define   UTMIP_OTGPD				BIT(11)
98
+#define   UTMIP_BIASPD				BIT(10)
99
+#define   UTMIP_HSSQUELCH_LEVEL(x)		(((x) & 0x3) << 0)
100
+#define   UTMIP_HSDISCON_LEVEL(x)		(((x) & 0x3) << 2)
101
+#define   UTMIP_HSDISCON_LEVEL_MSB(x)		((((x) & 0x4) >> 2) << 24)
101102 
102
-#define UTMIP_HSRX_CFG0		0x810
103
-#define   UTMIP_ELASTIC_LIMIT(x)	(((x) & 0x1f) << 10)
104
-#define   UTMIP_IDLE_WAIT(x)		(((x) & 0x1f) << 15)
103
+#define UTMIP_HSRX_CFG0				0x810
104
+#define   UTMIP_ELASTIC_LIMIT(x)		(((x) & 0x1f) << 10)
105
+#define   UTMIP_IDLE_WAIT(x)			(((x) & 0x1f) << 15)
105106 
106
-#define UTMIP_HSRX_CFG1		0x814
107
-#define   UTMIP_HS_SYNC_START_DLY(x)	(((x) & 0x1f) << 1)
107
+#define UTMIP_HSRX_CFG1				0x814
108
+#define   UTMIP_HS_SYNC_START_DLY(x)		(((x) & 0x1f) << 1)
108109 
109
-#define UTMIP_TX_CFG0		0x820
110
-#define   UTMIP_FS_PREABMLE_J		(1 << 19)
111
-#define   UTMIP_HS_DISCON_DISABLE	(1 << 8)
110
+#define UTMIP_TX_CFG0				0x820
111
+#define   UTMIP_FS_PREABMLE_J			BIT(19)
112
+#define   UTMIP_HS_DISCON_DISABLE		BIT(8)
112113 
113
-#define UTMIP_MISC_CFG0		0x824
114
-#define   UTMIP_DPDM_OBSERVE		(1 << 26)
115
-#define   UTMIP_DPDM_OBSERVE_SEL(x)	(((x) & 0xf) << 27)
116
-#define   UTMIP_DPDM_OBSERVE_SEL_FS_J	UTMIP_DPDM_OBSERVE_SEL(0xf)
117
-#define   UTMIP_DPDM_OBSERVE_SEL_FS_K	UTMIP_DPDM_OBSERVE_SEL(0xe)
118
-#define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
119
-#define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
120
-#define   UTMIP_SUSPEND_EXIT_ON_EDGE	(1 << 22)
114
+#define UTMIP_MISC_CFG0				0x824
115
+#define   UTMIP_DPDM_OBSERVE			BIT(26)
116
+#define   UTMIP_DPDM_OBSERVE_SEL(x)		(((x) & 0xf) << 27)
117
+#define   UTMIP_DPDM_OBSERVE_SEL_FS_J		UTMIP_DPDM_OBSERVE_SEL(0xf)
118
+#define   UTMIP_DPDM_OBSERVE_SEL_FS_K		UTMIP_DPDM_OBSERVE_SEL(0xe)
119
+#define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1		UTMIP_DPDM_OBSERVE_SEL(0xd)
120
+#define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0		UTMIP_DPDM_OBSERVE_SEL(0xc)
121
+#define   UTMIP_SUSPEND_EXIT_ON_EDGE		BIT(22)
121122 
122
-#define UTMIP_MISC_CFG1		0x828
123
-#define   UTMIP_PLL_ACTIVE_DLY_COUNT(x)	(((x) & 0x1f) << 18)
124
-#define   UTMIP_PLLU_STABLE_COUNT(x)	(((x) & 0xfff) << 6)
123
+#define UTMIP_MISC_CFG1				0x828
124
+#define   UTMIP_PLL_ACTIVE_DLY_COUNT(x)		(((x) & 0x1f) << 18)
125
+#define   UTMIP_PLLU_STABLE_COUNT(x)		(((x) & 0xfff) << 6)
125126 
126
-#define UTMIP_DEBOUNCE_CFG0	0x82c
127
-#define   UTMIP_BIAS_DEBOUNCE_A(x)	(((x) & 0xffff) << 0)
127
+#define UTMIP_DEBOUNCE_CFG0			0x82c
128
+#define   UTMIP_BIAS_DEBOUNCE_A(x)		(((x) & 0xffff) << 0)
128129 
129
-#define UTMIP_BAT_CHRG_CFG0	0x830
130
-#define   UTMIP_PD_CHRG			(1 << 0)
130
+#define UTMIP_BAT_CHRG_CFG0			0x830
131
+#define   UTMIP_PD_CHRG				BIT(0)
131132 
132
-#define UTMIP_SPARE_CFG0	0x834
133
-#define   FUSE_SETUP_SEL		(1 << 3)
133
+#define UTMIP_SPARE_CFG0			0x834
134
+#define   FUSE_SETUP_SEL			BIT(3)
134135 
135
-#define UTMIP_XCVR_CFG1		0x838
136
-#define   UTMIP_FORCE_PDDISC_POWERDOWN	(1 << 0)
137
-#define   UTMIP_FORCE_PDCHRP_POWERDOWN	(1 << 2)
138
-#define   UTMIP_FORCE_PDDR_POWERDOWN	(1 << 4)
139
-#define   UTMIP_XCVR_TERM_RANGE_ADJ(x)	(((x) & 0xf) << 18)
136
+#define UTMIP_XCVR_CFG1				0x838
137
+#define   UTMIP_FORCE_PDDISC_POWERDOWN		BIT(0)
138
+#define   UTMIP_FORCE_PDCHRP_POWERDOWN		BIT(2)
139
+#define   UTMIP_FORCE_PDDR_POWERDOWN		BIT(4)
140
+#define   UTMIP_XCVR_TERM_RANGE_ADJ(x)		(((x) & 0xf) << 18)
140141 
141
-#define UTMIP_BIAS_CFG1		0x83c
142
-#define   UTMIP_BIAS_PDTRK_COUNT(x)	(((x) & 0x1f) << 3)
142
+#define UTMIP_BIAS_CFG1				0x83c
143
+#define   UTMIP_BIAS_PDTRK_COUNT(x)		(((x) & 0x1f) << 3)
143144 
144145 /* For Tegra30 and above only, the address is different in Tegra20 */
145
-#define USB_USBMODE		0x1f8
146
-#define   USB_USBMODE_MASK		(3 << 0)
147
-#define   USB_USBMODE_HOST		(3 << 0)
148
-#define   USB_USBMODE_DEVICE		(2 << 0)
146
+#define USB_USBMODE				0x1f8
147
+#define   USB_USBMODE_MASK			(3 << 0)
148
+#define   USB_USBMODE_HOST			(3 << 0)
149
+#define   USB_USBMODE_DEVICE			(2 << 0)
149150 
150151 static DEFINE_SPINLOCK(utmip_pad_lock);
151
-static int utmip_pad_count;
152
+static unsigned int utmip_pad_count;
152153 
153154 struct tegra_xtal_freq {
154
-	int freq;
155
+	unsigned int freq;
155156 	u8 enable_delay;
156157 	u8 stable_count;
157158 	u8 active_delay;
....@@ -194,66 +195,55 @@
194195 	},
195196 };
196197 
198
+static inline struct tegra_usb_phy *to_tegra_usb_phy(struct usb_phy *u_phy)
199
+{
200
+	return container_of(u_phy, struct tegra_usb_phy, u_phy);
201
+}
202
+
197203 static void set_pts(struct tegra_usb_phy *phy, u8 pts_val)
198204 {
199205 	void __iomem *base = phy->regs;
200
-	unsigned long val;
206
+	u32 val;
201207 
202208 	if (phy->soc_config->has_hostpc) {
203
-		val = readl(base + TEGRA_USB_HOSTPC1_DEVLC);
209
+		val = readl_relaxed(base + TEGRA_USB_HOSTPC1_DEVLC);
204210 		val &= ~TEGRA_USB_HOSTPC1_DEVLC_PTS(~0);
205211 		val |= TEGRA_USB_HOSTPC1_DEVLC_PTS(pts_val);
206
-		writel(val, base + TEGRA_USB_HOSTPC1_DEVLC);
212
+		writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC);
207213 	} else {
208
-		val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS;
214
+		val = readl_relaxed(base + TEGRA_USB_PORTSC1);
215
+		val &= ~TEGRA_PORTSC1_RWC_BITS;
209216 		val &= ~TEGRA_USB_PORTSC1_PTS(~0);
210217 		val |= TEGRA_USB_PORTSC1_PTS(pts_val);
211
-		writel(val, base + TEGRA_USB_PORTSC1);
218
+		writel_relaxed(val, base + TEGRA_USB_PORTSC1);
212219 	}
213220 }
214221 
215222 static void set_phcd(struct tegra_usb_phy *phy, bool enable)
216223 {
217224 	void __iomem *base = phy->regs;
218
-	unsigned long val;
225
+	u32 val;
219226 
220227 	if (phy->soc_config->has_hostpc) {
221
-		val = readl(base + TEGRA_USB_HOSTPC1_DEVLC);
228
+		val = readl_relaxed(base + TEGRA_USB_HOSTPC1_DEVLC);
222229 		if (enable)
223230 			val |= TEGRA_USB_HOSTPC1_DEVLC_PHCD;
224231 		else
225232 			val &= ~TEGRA_USB_HOSTPC1_DEVLC_PHCD;
226
-		writel(val, base + TEGRA_USB_HOSTPC1_DEVLC);
233
+		writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC);
227234 	} else {
228
-		val = readl(base + TEGRA_USB_PORTSC1) & ~PORT_RWC_BITS;
235
+		val = readl_relaxed(base + TEGRA_USB_PORTSC1) & ~PORT_RWC_BITS;
229236 		if (enable)
230237 			val |= TEGRA_USB_PORTSC1_PHCD;
231238 		else
232239 			val &= ~TEGRA_USB_PORTSC1_PHCD;
233
-		writel(val, base + TEGRA_USB_PORTSC1);
240
+		writel_relaxed(val, base + TEGRA_USB_PORTSC1);
234241 	}
235242 }
236243 
237244 static int utmip_pad_open(struct tegra_usb_phy *phy)
238245 {
239246 	int ret;
240
-
241
-	phy->pad_clk = devm_clk_get(phy->u_phy.dev, "utmi-pads");
242
-	if (IS_ERR(phy->pad_clk)) {
243
-		ret = PTR_ERR(phy->pad_clk);
244
-		dev_err(phy->u_phy.dev,
245
-			"Failed to get UTMIP pad clock: %d\n", ret);
246
-		return ret;
247
-	}
248
-
249
-	phy->pad_rst = devm_reset_control_get_optional_shared(
250
-						phy->u_phy.dev, "utmi-pads");
251
-	if (IS_ERR(phy->pad_rst)) {
252
-		ret = PTR_ERR(phy->pad_rst);
253
-		dev_err(phy->u_phy.dev,
254
-			"Failed to get UTMI-pads reset: %d\n", ret);
255
-		return ret;
256
-	}
257247 
258248 	ret = clk_prepare_enable(phy->pad_clk);
259249 	if (ret) {
....@@ -315,18 +305,21 @@
315305 	return ret;
316306 }
317307 
318
-static void utmip_pad_power_on(struct tegra_usb_phy *phy)
308
+static int utmip_pad_power_on(struct tegra_usb_phy *phy)
319309 {
320
-	unsigned long val, flags;
321
-	void __iomem *base = phy->pad_regs;
322310 	struct tegra_utmip_config *config = phy->config;
311
+	void __iomem *base = phy->pad_regs;
312
+	u32 val;
313
+	int err;
323314 
324
-	clk_prepare_enable(phy->pad_clk);
315
+	err = clk_prepare_enable(phy->pad_clk);
316
+	if (err)
317
+		return err;
325318 
326
-	spin_lock_irqsave(&utmip_pad_lock, flags);
319
+	spin_lock(&utmip_pad_lock);
327320 
328321 	if (utmip_pad_count++ == 0) {
329
-		val = readl(base + UTMIP_BIAS_CFG0);
322
+		val = readl_relaxed(base + UTMIP_BIAS_CFG0);
330323 		val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
331324 
332325 		if (phy->soc_config->requires_extra_tuning_parameters) {
....@@ -338,53 +331,59 @@
338331 			val |= UTMIP_HSDISCON_LEVEL(config->hsdiscon_level);
339332 			val |= UTMIP_HSDISCON_LEVEL_MSB(config->hsdiscon_level);
340333 		}
341
-		writel(val, base + UTMIP_BIAS_CFG0);
334
+		writel_relaxed(val, base + UTMIP_BIAS_CFG0);
342335 	}
343336 
344
-	spin_unlock_irqrestore(&utmip_pad_lock, flags);
345
-
346
-	clk_disable_unprepare(phy->pad_clk);
347
-}
348
-
349
-static int utmip_pad_power_off(struct tegra_usb_phy *phy)
350
-{
351
-	unsigned long val, flags;
352
-	void __iomem *base = phy->pad_regs;
353
-
354
-	if (!utmip_pad_count) {
355
-		dev_err(phy->u_phy.dev, "UTMIP pad already powered off\n");
356
-		return -EINVAL;
357
-	}
358
-
359
-	clk_prepare_enable(phy->pad_clk);
360
-
361
-	spin_lock_irqsave(&utmip_pad_lock, flags);
362
-
363
-	if (--utmip_pad_count == 0) {
364
-		val = readl(base + UTMIP_BIAS_CFG0);
365
-		val |= UTMIP_OTGPD | UTMIP_BIASPD;
366
-		writel(val, base + UTMIP_BIAS_CFG0);
367
-	}
368
-
369
-	spin_unlock_irqrestore(&utmip_pad_lock, flags);
337
+	spin_unlock(&utmip_pad_lock);
370338 
371339 	clk_disable_unprepare(phy->pad_clk);
372340 
373341 	return 0;
374342 }
375343 
344
+static int utmip_pad_power_off(struct tegra_usb_phy *phy)
345
+{
346
+	void __iomem *base = phy->pad_regs;
347
+	u32 val;
348
+	int ret;
349
+
350
+	ret = clk_prepare_enable(phy->pad_clk);
351
+	if (ret)
352
+		return ret;
353
+
354
+	spin_lock(&utmip_pad_lock);
355
+
356
+	if (!utmip_pad_count) {
357
+		dev_err(phy->u_phy.dev, "UTMIP pad already powered off\n");
358
+		ret = -EINVAL;
359
+		goto ulock;
360
+	}
361
+
362
+	if (--utmip_pad_count == 0) {
363
+		val = readl_relaxed(base + UTMIP_BIAS_CFG0);
364
+		val |= UTMIP_OTGPD | UTMIP_BIASPD;
365
+		writel_relaxed(val, base + UTMIP_BIAS_CFG0);
366
+	}
367
+ulock:
368
+	spin_unlock(&utmip_pad_lock);
369
+
370
+	clk_disable_unprepare(phy->pad_clk);
371
+
372
+	return ret;
373
+}
374
+
376375 static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result)
377376 {
378377 	u32 tmp;
379378 
380
-	return readl_poll_timeout(reg, tmp, (tmp & mask) == result,
381
-				  2000, 6000);
379
+	return readl_relaxed_poll_timeout(reg, tmp, (tmp & mask) == result,
380
+					  2000, 6000);
382381 }
383382 
384383 static void utmi_phy_clk_disable(struct tegra_usb_phy *phy)
385384 {
386
-	unsigned long val;
387385 	void __iomem *base = phy->regs;
386
+	u32 val;
388387 
389388 	/*
390389 	 * The USB driver may have already initiated the phy clock
....@@ -395,27 +394,28 @@
395394 		return;
396395 
397396 	if (phy->is_legacy_phy) {
398
-		val = readl(base + USB_SUSP_CTRL);
397
+		val = readl_relaxed(base + USB_SUSP_CTRL);
399398 		val |= USB_SUSP_SET;
400
-		writel(val, base + USB_SUSP_CTRL);
399
+		writel_relaxed(val, base + USB_SUSP_CTRL);
401400 
402
-		udelay(10);
401
+		usleep_range(10, 100);
403402 
404
-		val = readl(base + USB_SUSP_CTRL);
403
+		val = readl_relaxed(base + USB_SUSP_CTRL);
405404 		val &= ~USB_SUSP_SET;
406
-		writel(val, base + USB_SUSP_CTRL);
407
-	} else
405
+		writel_relaxed(val, base + USB_SUSP_CTRL);
406
+	} else {
408407 		set_phcd(phy, true);
408
+	}
409409 
410
-	if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0)
410
+	if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0))
411411 		dev_err(phy->u_phy.dev,
412412 			"Timeout waiting for PHY to stabilize on disable\n");
413413 }
414414 
415415 static void utmi_phy_clk_enable(struct tegra_usb_phy *phy)
416416 {
417
-	unsigned long val;
418417 	void __iomem *base = phy->regs;
418
+	u32 val;
419419 
420420 	/*
421421 	 * The USB driver may have already initiated the phy clock
....@@ -427,97 +427,101 @@
427427 		return;
428428 
429429 	if (phy->is_legacy_phy) {
430
-		val = readl(base + USB_SUSP_CTRL);
430
+		val = readl_relaxed(base + USB_SUSP_CTRL);
431431 		val |= USB_SUSP_CLR;
432
-		writel(val, base + USB_SUSP_CTRL);
432
+		writel_relaxed(val, base + USB_SUSP_CTRL);
433433 
434
-		udelay(10);
434
+		usleep_range(10, 100);
435435 
436
-		val = readl(base + USB_SUSP_CTRL);
436
+		val = readl_relaxed(base + USB_SUSP_CTRL);
437437 		val &= ~USB_SUSP_CLR;
438
-		writel(val, base + USB_SUSP_CTRL);
439
-	} else
438
+		writel_relaxed(val, base + USB_SUSP_CTRL);
439
+	} else {
440440 		set_phcd(phy, false);
441
+	}
441442 
442443 	if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
443
-						     USB_PHY_CLK_VALID))
444
+			       USB_PHY_CLK_VALID))
444445 		dev_err(phy->u_phy.dev,
445446 			"Timeout waiting for PHY to stabilize on enable\n");
446447 }
447448 
448449 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
449450 {
450
-	unsigned long val;
451
-	void __iomem *base = phy->regs;
452451 	struct tegra_utmip_config *config = phy->config;
452
+	void __iomem *base = phy->regs;
453
+	u32 val;
454
+	int err;
453455 
454
-	val = readl(base + USB_SUSP_CTRL);
456
+	val = readl_relaxed(base + USB_SUSP_CTRL);
455457 	val |= UTMIP_RESET;
456
-	writel(val, base + USB_SUSP_CTRL);
458
+	writel_relaxed(val, base + USB_SUSP_CTRL);
457459 
458460 	if (phy->is_legacy_phy) {
459
-		val = readl(base + USB1_LEGACY_CTRL);
461
+		val = readl_relaxed(base + USB1_LEGACY_CTRL);
460462 		val |= USB1_NO_LEGACY_MODE;
461
-		writel(val, base + USB1_LEGACY_CTRL);
463
+		writel_relaxed(val, base + USB1_LEGACY_CTRL);
462464 	}
463465 
464
-	val = readl(base + UTMIP_TX_CFG0);
466
+	val = readl_relaxed(base + UTMIP_TX_CFG0);
465467 	val |= UTMIP_FS_PREABMLE_J;
466
-	writel(val, base + UTMIP_TX_CFG0);
468
+	writel_relaxed(val, base + UTMIP_TX_CFG0);
467469 
468
-	val = readl(base + UTMIP_HSRX_CFG0);
470
+	val = readl_relaxed(base + UTMIP_HSRX_CFG0);
469471 	val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
470472 	val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
471473 	val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
472
-	writel(val, base + UTMIP_HSRX_CFG0);
474
+	writel_relaxed(val, base + UTMIP_HSRX_CFG0);
473475 
474
-	val = readl(base + UTMIP_HSRX_CFG1);
476
+	val = readl_relaxed(base + UTMIP_HSRX_CFG1);
475477 	val &= ~UTMIP_HS_SYNC_START_DLY(~0);
476478 	val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
477
-	writel(val, base + UTMIP_HSRX_CFG1);
479
+	writel_relaxed(val, base + UTMIP_HSRX_CFG1);
478480 
479
-	val = readl(base + UTMIP_DEBOUNCE_CFG0);
481
+	val = readl_relaxed(base + UTMIP_DEBOUNCE_CFG0);
480482 	val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
481483 	val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
482
-	writel(val, base + UTMIP_DEBOUNCE_CFG0);
484
+	writel_relaxed(val, base + UTMIP_DEBOUNCE_CFG0);
483485 
484
-	val = readl(base + UTMIP_MISC_CFG0);
486
+	val = readl_relaxed(base + UTMIP_MISC_CFG0);
485487 	val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
486
-	writel(val, base + UTMIP_MISC_CFG0);
488
+	writel_relaxed(val, base + UTMIP_MISC_CFG0);
487489 
488490 	if (!phy->soc_config->utmi_pll_config_in_car_module) {
489
-		val = readl(base + UTMIP_MISC_CFG1);
491
+		val = readl_relaxed(base + UTMIP_MISC_CFG1);
490492 		val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) |
491493 			UTMIP_PLLU_STABLE_COUNT(~0));
492494 		val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
493495 			UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
494
-		writel(val, base + UTMIP_MISC_CFG1);
496
+		writel_relaxed(val, base + UTMIP_MISC_CFG1);
495497 
496
-		val = readl(base + UTMIP_PLL_CFG1);
498
+		val = readl_relaxed(base + UTMIP_PLL_CFG1);
497499 		val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) |
498500 			UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
499501 		val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |
500502 			UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
501
-		writel(val, base + UTMIP_PLL_CFG1);
503
+		writel_relaxed(val, base + UTMIP_PLL_CFG1);
502504 	}
503505 
504506 	if (phy->mode == USB_DR_MODE_PERIPHERAL) {
505
-		val = readl(base + USB_SUSP_CTRL);
507
+		val = readl_relaxed(base + USB_SUSP_CTRL);
506508 		val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
507
-		writel(val, base + USB_SUSP_CTRL);
509
+		writel_relaxed(val, base + USB_SUSP_CTRL);
508510 
509
-		val = readl(base + UTMIP_BAT_CHRG_CFG0);
511
+		val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);
510512 		val &= ~UTMIP_PD_CHRG;
511
-		writel(val, base + UTMIP_BAT_CHRG_CFG0);
513
+		writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);
512514 	} else {
513
-		val = readl(base + UTMIP_BAT_CHRG_CFG0);
515
+		val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);
514516 		val |= UTMIP_PD_CHRG;
515
-		writel(val, base + UTMIP_BAT_CHRG_CFG0);
517
+		writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);
516518 	}
517519 
518
-	utmip_pad_power_on(phy);
520
+	err = utmip_pad_power_on(phy);
521
+	if (err)
522
+		return err;
519523 
520
-	val = readl(base + UTMIP_XCVR_CFG0);
524
+	val = readl_relaxed(base + UTMIP_XCVR_CFG0);
521525 	val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
522526 		 UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_LSBIAS_SEL |
523527 		 UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_SETUP_MSB(~0) |
....@@ -535,57 +539,57 @@
535539 		val |= UTMIP_XCVR_HSSLEW(config->xcvr_hsslew);
536540 		val |= UTMIP_XCVR_HSSLEW_MSB(config->xcvr_hsslew);
537541 	}
538
-	writel(val, base + UTMIP_XCVR_CFG0);
542
+	writel_relaxed(val, base + UTMIP_XCVR_CFG0);
539543 
540
-	val = readl(base + UTMIP_XCVR_CFG1);
544
+	val = readl_relaxed(base + UTMIP_XCVR_CFG1);
541545 	val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
542546 		 UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
543547 	val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
544
-	writel(val, base + UTMIP_XCVR_CFG1);
548
+	writel_relaxed(val, base + UTMIP_XCVR_CFG1);
545549 
546
-	val = readl(base + UTMIP_BIAS_CFG1);
550
+	val = readl_relaxed(base + UTMIP_BIAS_CFG1);
547551 	val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
548552 	val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
549
-	writel(val, base + UTMIP_BIAS_CFG1);
553
+	writel_relaxed(val, base + UTMIP_BIAS_CFG1);
550554 
551
-	val = readl(base + UTMIP_SPARE_CFG0);
555
+	val = readl_relaxed(base + UTMIP_SPARE_CFG0);
552556 	if (config->xcvr_setup_use_fuses)
553557 		val |= FUSE_SETUP_SEL;
554558 	else
555559 		val &= ~FUSE_SETUP_SEL;
556
-	writel(val, base + UTMIP_SPARE_CFG0);
560
+	writel_relaxed(val, base + UTMIP_SPARE_CFG0);
557561 
558562 	if (!phy->is_legacy_phy) {
559
-		val = readl(base + USB_SUSP_CTRL);
563
+		val = readl_relaxed(base + USB_SUSP_CTRL);
560564 		val |= UTMIP_PHY_ENABLE;
561
-		writel(val, base + USB_SUSP_CTRL);
565
+		writel_relaxed(val, base + USB_SUSP_CTRL);
562566 	}
563567 
564
-	val = readl(base + USB_SUSP_CTRL);
568
+	val = readl_relaxed(base + USB_SUSP_CTRL);
565569 	val &= ~UTMIP_RESET;
566
-	writel(val, base + USB_SUSP_CTRL);
570
+	writel_relaxed(val, base + USB_SUSP_CTRL);
567571 
568572 	if (phy->is_legacy_phy) {
569
-		val = readl(base + USB1_LEGACY_CTRL);
573
+		val = readl_relaxed(base + USB1_LEGACY_CTRL);
570574 		val &= ~USB1_VBUS_SENSE_CTL_MASK;
571575 		val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD;
572
-		writel(val, base + USB1_LEGACY_CTRL);
576
+		writel_relaxed(val, base + USB1_LEGACY_CTRL);
573577 
574
-		val = readl(base + USB_SUSP_CTRL);
578
+		val = readl_relaxed(base + USB_SUSP_CTRL);
575579 		val &= ~USB_SUSP_SET;
576
-		writel(val, base + USB_SUSP_CTRL);
580
+		writel_relaxed(val, base + USB_SUSP_CTRL);
577581 	}
578582 
579583 	utmi_phy_clk_enable(phy);
580584 
581585 	if (phy->soc_config->requires_usbmode_setup) {
582
-		val = readl(base + USB_USBMODE);
586
+		val = readl_relaxed(base + USB_USBMODE);
583587 		val &= ~USB_USBMODE_MASK;
584588 		if (phy->mode == USB_DR_MODE_HOST)
585589 			val |= USB_USBMODE_HOST;
586590 		else
587591 			val |= USB_USBMODE_DEVICE;
588
-		writel(val, base + USB_USBMODE);
592
+		writel_relaxed(val, base + USB_USBMODE);
589593 	}
590594 
591595 	if (!phy->is_legacy_phy)
....@@ -596,258 +600,252 @@
596600 
597601 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
598602 {
599
-	unsigned long val;
600603 	void __iomem *base = phy->regs;
604
+	u32 val;
601605 
602606 	utmi_phy_clk_disable(phy);
603607 
604608 	if (phy->mode == USB_DR_MODE_PERIPHERAL) {
605
-		val = readl(base + USB_SUSP_CTRL);
609
+		val = readl_relaxed(base + USB_SUSP_CTRL);
606610 		val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
607611 		val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
608
-		writel(val, base + USB_SUSP_CTRL);
612
+		writel_relaxed(val, base + USB_SUSP_CTRL);
609613 	}
610614 
611
-	val = readl(base + USB_SUSP_CTRL);
615
+	val = readl_relaxed(base + USB_SUSP_CTRL);
612616 	val |= UTMIP_RESET;
613
-	writel(val, base + USB_SUSP_CTRL);
617
+	writel_relaxed(val, base + USB_SUSP_CTRL);
614618 
615
-	val = readl(base + UTMIP_BAT_CHRG_CFG0);
619
+	val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);
616620 	val |= UTMIP_PD_CHRG;
617
-	writel(val, base + UTMIP_BAT_CHRG_CFG0);
621
+	writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);
618622 
619
-	val = readl(base + UTMIP_XCVR_CFG0);
623
+	val = readl_relaxed(base + UTMIP_XCVR_CFG0);
620624 	val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
621625 	       UTMIP_FORCE_PDZI_POWERDOWN;
622
-	writel(val, base + UTMIP_XCVR_CFG0);
626
+	writel_relaxed(val, base + UTMIP_XCVR_CFG0);
623627 
624
-	val = readl(base + UTMIP_XCVR_CFG1);
628
+	val = readl_relaxed(base + UTMIP_XCVR_CFG1);
625629 	val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
626630 	       UTMIP_FORCE_PDDR_POWERDOWN;
627
-	writel(val, base + UTMIP_XCVR_CFG1);
631
+	writel_relaxed(val, base + UTMIP_XCVR_CFG1);
628632 
629633 	return utmip_pad_power_off(phy);
630634 }
631635 
632636 static void utmi_phy_preresume(struct tegra_usb_phy *phy)
633637 {
634
-	unsigned long val;
635638 	void __iomem *base = phy->regs;
639
+	u32 val;
636640 
637
-	val = readl(base + UTMIP_TX_CFG0);
641
+	val = readl_relaxed(base + UTMIP_TX_CFG0);
638642 	val |= UTMIP_HS_DISCON_DISABLE;
639
-	writel(val, base + UTMIP_TX_CFG0);
643
+	writel_relaxed(val, base + UTMIP_TX_CFG0);
640644 }
641645 
642646 static void utmi_phy_postresume(struct tegra_usb_phy *phy)
643647 {
644
-	unsigned long val;
645648 	void __iomem *base = phy->regs;
649
+	u32 val;
646650 
647
-	val = readl(base + UTMIP_TX_CFG0);
651
+	val = readl_relaxed(base + UTMIP_TX_CFG0);
648652 	val &= ~UTMIP_HS_DISCON_DISABLE;
649
-	writel(val, base + UTMIP_TX_CFG0);
653
+	writel_relaxed(val, base + UTMIP_TX_CFG0);
650654 }
651655 
652656 static void utmi_phy_restore_start(struct tegra_usb_phy *phy,
653657 				   enum tegra_usb_phy_port_speed port_speed)
654658 {
655
-	unsigned long val;
656659 	void __iomem *base = phy->regs;
660
+	u32 val;
657661 
658
-	val = readl(base + UTMIP_MISC_CFG0);
662
+	val = readl_relaxed(base + UTMIP_MISC_CFG0);
659663 	val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
660664 	if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
661665 		val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
662666 	else
663667 		val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
664
-	writel(val, base + UTMIP_MISC_CFG0);
665
-	udelay(1);
668
+	writel_relaxed(val, base + UTMIP_MISC_CFG0);
669
+	usleep_range(1, 10);
666670 
667
-	val = readl(base + UTMIP_MISC_CFG0);
671
+	val = readl_relaxed(base + UTMIP_MISC_CFG0);
668672 	val |= UTMIP_DPDM_OBSERVE;
669
-	writel(val, base + UTMIP_MISC_CFG0);
670
-	udelay(10);
673
+	writel_relaxed(val, base + UTMIP_MISC_CFG0);
674
+	usleep_range(10, 100);
671675 }
672676 
673677 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
674678 {
675
-	unsigned long val;
676679 	void __iomem *base = phy->regs;
680
+	u32 val;
677681 
678
-	val = readl(base + UTMIP_MISC_CFG0);
682
+	val = readl_relaxed(base + UTMIP_MISC_CFG0);
679683 	val &= ~UTMIP_DPDM_OBSERVE;
680
-	writel(val, base + UTMIP_MISC_CFG0);
681
-	udelay(10);
684
+	writel_relaxed(val, base + UTMIP_MISC_CFG0);
685
+	usleep_range(10, 100);
682686 }
683687 
684688 static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
685689 {
686
-	int ret;
687
-	unsigned long val;
688690 	void __iomem *base = phy->regs;
691
+	u32 val;
692
+	int err;
689693 
690
-	ret = gpio_direction_output(phy->reset_gpio, 0);
691
-	if (ret < 0) {
692
-		dev_err(phy->u_phy.dev, "GPIO %d not set to 0: %d\n",
693
-			phy->reset_gpio, ret);
694
-		return ret;
695
-	}
696
-	msleep(5);
697
-	ret = gpio_direction_output(phy->reset_gpio, 1);
698
-	if (ret < 0) {
699
-		dev_err(phy->u_phy.dev, "GPIO %d not set to 1: %d\n",
700
-			phy->reset_gpio, ret);
701
-		return ret;
702
-	}
694
+	gpiod_set_value_cansleep(phy->reset_gpio, 1);
703695 
704
-	clk_prepare_enable(phy->clk);
705
-	msleep(1);
696
+	err = clk_prepare_enable(phy->clk);
697
+	if (err)
698
+		return err;
706699 
707
-	val = readl(base + USB_SUSP_CTRL);
700
+	usleep_range(5000, 6000);
701
+
702
+	gpiod_set_value_cansleep(phy->reset_gpio, 0);
703
+
704
+	usleep_range(1000, 2000);
705
+
706
+	val = readl_relaxed(base + USB_SUSP_CTRL);
708707 	val |= UHSIC_RESET;
709
-	writel(val, base + USB_SUSP_CTRL);
708
+	writel_relaxed(val, base + USB_SUSP_CTRL);
710709 
711
-	val = readl(base + ULPI_TIMING_CTRL_0);
710
+	val = readl_relaxed(base + ULPI_TIMING_CTRL_0);
712711 	val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
713
-	writel(val, base + ULPI_TIMING_CTRL_0);
712
+	writel_relaxed(val, base + ULPI_TIMING_CTRL_0);
714713 
715
-	val = readl(base + USB_SUSP_CTRL);
714
+	val = readl_relaxed(base + USB_SUSP_CTRL);
716715 	val |= ULPI_PHY_ENABLE;
717
-	writel(val, base + USB_SUSP_CTRL);
716
+	writel_relaxed(val, base + USB_SUSP_CTRL);
718717 
719718 	val = 0;
720
-	writel(val, base + ULPI_TIMING_CTRL_1);
719
+	writel_relaxed(val, base + ULPI_TIMING_CTRL_1);
721720 
722721 	val |= ULPI_DATA_TRIMMER_SEL(4);
723722 	val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
724723 	val |= ULPI_DIR_TRIMMER_SEL(4);
725
-	writel(val, base + ULPI_TIMING_CTRL_1);
726
-	udelay(10);
724
+	writel_relaxed(val, base + ULPI_TIMING_CTRL_1);
725
+	usleep_range(10, 100);
727726 
728727 	val |= ULPI_DATA_TRIMMER_LOAD;
729728 	val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
730729 	val |= ULPI_DIR_TRIMMER_LOAD;
731
-	writel(val, base + ULPI_TIMING_CTRL_1);
730
+	writel_relaxed(val, base + ULPI_TIMING_CTRL_1);
732731 
733732 	/* Fix VbusInvalid due to floating VBUS */
734
-	ret = usb_phy_io_write(phy->ulpi, 0x40, 0x08);
735
-	if (ret) {
736
-		dev_err(phy->u_phy.dev, "ULPI write failed: %d\n", ret);
737
-		return ret;
733
+	err = usb_phy_io_write(phy->ulpi, 0x40, 0x08);
734
+	if (err) {
735
+		dev_err(phy->u_phy.dev, "ULPI write failed: %d\n", err);
736
+		goto disable_clk;
738737 	}
739738 
740
-	ret = usb_phy_io_write(phy->ulpi, 0x80, 0x0B);
741
-	if (ret) {
742
-		dev_err(phy->u_phy.dev, "ULPI write failed: %d\n", ret);
743
-		return ret;
739
+	err = usb_phy_io_write(phy->ulpi, 0x80, 0x0B);
740
+	if (err) {
741
+		dev_err(phy->u_phy.dev, "ULPI write failed: %d\n", err);
742
+		goto disable_clk;
744743 	}
745744 
746
-	val = readl(base + USB_SUSP_CTRL);
745
+	val = readl_relaxed(base + USB_SUSP_CTRL);
747746 	val |= USB_SUSP_CLR;
748
-	writel(val, base + USB_SUSP_CTRL);
749
-	udelay(100);
747
+	writel_relaxed(val, base + USB_SUSP_CTRL);
748
+	usleep_range(100, 1000);
750749 
751
-	val = readl(base + USB_SUSP_CTRL);
750
+	val = readl_relaxed(base + USB_SUSP_CTRL);
752751 	val &= ~USB_SUSP_CLR;
753
-	writel(val, base + USB_SUSP_CTRL);
752
+	writel_relaxed(val, base + USB_SUSP_CTRL);
754753 
755754 	return 0;
755
+
756
+disable_clk:
757
+	clk_disable_unprepare(phy->clk);
758
+
759
+	return err;
756760 }
757761 
758762 static int ulpi_phy_power_off(struct tegra_usb_phy *phy)
759763 {
760
-	clk_disable(phy->clk);
761
-	return gpio_direction_output(phy->reset_gpio, 0);
762
-}
764
+	gpiod_set_value_cansleep(phy->reset_gpio, 1);
765
+	usleep_range(5000, 6000);
766
+	clk_disable_unprepare(phy->clk);
763767 
764
-static void tegra_usb_phy_close(struct tegra_usb_phy *phy)
765
-{
766
-	if (!IS_ERR(phy->vbus))
767
-		regulator_disable(phy->vbus);
768
-
769
-	if (!phy->is_ulpi_phy)
770
-		utmip_pad_close(phy);
771
-
772
-	clk_disable_unprepare(phy->pll_u);
768
+	return 0;
773769 }
774770 
775771 static int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
776772 {
773
+	int err;
774
+
775
+	if (phy->powered_on)
776
+		return 0;
777
+
777778 	if (phy->is_ulpi_phy)
778
-		return ulpi_phy_power_on(phy);
779
+		err = ulpi_phy_power_on(phy);
779780 	else
780
-		return utmi_phy_power_on(phy);
781
+		err = utmi_phy_power_on(phy);
782
+	if (err)
783
+		return err;
784
+
785
+	phy->powered_on = true;
786
+
787
+	return 0;
781788 }
782789 
783790 static int tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
784791 {
792
+	int err;
793
+
794
+	if (!phy->powered_on)
795
+		return 0;
796
+
785797 	if (phy->is_ulpi_phy)
786
-		return ulpi_phy_power_off(phy);
798
+		err = ulpi_phy_power_off(phy);
787799 	else
788
-		return utmi_phy_power_off(phy);
800
+		err = utmi_phy_power_off(phy);
801
+	if (err)
802
+		return err;
803
+
804
+	phy->powered_on = false;
805
+
806
+	return 0;
789807 }
790808 
791
-static int	tegra_usb_phy_suspend(struct usb_phy *x, int suspend)
809
+static void tegra_usb_phy_shutdown(struct usb_phy *u_phy)
792810 {
793
-	struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
811
+	struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
812
+
813
+	if (WARN_ON(!phy->freq))
814
+		return;
815
+
816
+	tegra_usb_phy_power_off(phy);
817
+
818
+	if (!phy->is_ulpi_phy)
819
+		utmip_pad_close(phy);
820
+
821
+	regulator_disable(phy->vbus);
822
+	clk_disable_unprepare(phy->pll_u);
823
+
824
+	phy->freq = NULL;
825
+}
826
+
827
+static int tegra_usb_phy_set_suspend(struct usb_phy *u_phy, int suspend)
828
+{
829
+	struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
830
+
831
+	if (WARN_ON(!phy->freq))
832
+		return -EINVAL;
833
+
794834 	if (suspend)
795835 		return tegra_usb_phy_power_off(phy);
796836 	else
797837 		return tegra_usb_phy_power_on(phy);
798838 }
799839 
800
-static int ulpi_open(struct tegra_usb_phy *phy)
840
+static int tegra_usb_phy_init(struct usb_phy *u_phy)
801841 {
802
-	int err;
803
-
804
-	phy->clk = devm_clk_get(phy->u_phy.dev, "ulpi-link");
805
-	if (IS_ERR(phy->clk)) {
806
-		err = PTR_ERR(phy->clk);
807
-		dev_err(phy->u_phy.dev, "Failed to get ULPI clock: %d\n", err);
808
-		return err;
809
-	}
810
-
811
-	err = devm_gpio_request(phy->u_phy.dev, phy->reset_gpio,
812
-		"ulpi_phy_reset_b");
813
-	if (err < 0) {
814
-		dev_err(phy->u_phy.dev, "Request failed for GPIO %d: %d\n",
815
-			phy->reset_gpio, err);
816
-		return err;
817
-	}
818
-
819
-	err = gpio_direction_output(phy->reset_gpio, 0);
820
-	if (err < 0) {
821
-		dev_err(phy->u_phy.dev,
822
-			"GPIO %d direction not set to output: %d\n",
823
-			phy->reset_gpio, err);
824
-		return err;
825
-	}
826
-
827
-	phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
828
-	if (!phy->ulpi) {
829
-		dev_err(phy->u_phy.dev, "Failed to create ULPI OTG\n");
830
-		err = -ENOMEM;
831
-		return err;
832
-	}
833
-
834
-	phy->ulpi->io_priv = phy->regs + ULPI_VIEWPORT;
835
-	return 0;
836
-}
837
-
838
-static int tegra_usb_phy_init(struct tegra_usb_phy *phy)
839
-{
842
+	struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
840843 	unsigned long parent_rate;
841
-	int i;
844
+	unsigned int i;
842845 	int err;
843846 
844
-	phy->pll_u = devm_clk_get(phy->u_phy.dev, "pll_u");
845
-	if (IS_ERR(phy->pll_u)) {
846
-		err = PTR_ERR(phy->pll_u);
847
-		dev_err(phy->u_phy.dev,
848
-			"Failed to get pll_u clock: %d\n", err);
849
-		return err;
850
-	}
847
+	if (WARN_ON(phy->freq))
848
+		return 0;
851849 
852850 	err = clk_prepare_enable(phy->pll_u);
853851 	if (err)
....@@ -864,64 +862,74 @@
864862 		dev_err(phy->u_phy.dev, "Invalid pll_u parent rate %ld\n",
865863 			parent_rate);
866864 		err = -EINVAL;
867
-		goto fail;
865
+		goto disable_clk;
868866 	}
869867 
870
-	if (!IS_ERR(phy->vbus)) {
871
-		err = regulator_enable(phy->vbus);
872
-		if (err) {
873
-			dev_err(phy->u_phy.dev,
874
-				"Failed to enable USB VBUS regulator: %d\n",
875
-				err);
876
-			goto fail;
877
-		}
868
+	err = regulator_enable(phy->vbus);
869
+	if (err) {
870
+		dev_err(phy->u_phy.dev,
871
+			"Failed to enable USB VBUS regulator: %d\n", err);
872
+		goto disable_clk;
878873 	}
879874 
880
-	if (phy->is_ulpi_phy)
881
-		err = ulpi_open(phy);
882
-	else
875
+	if (!phy->is_ulpi_phy) {
883876 		err = utmip_pad_open(phy);
884
-	if (err < 0)
885
-		goto fail;
877
+		if (err)
878
+			goto disable_vbus;
879
+	}
880
+
881
+	err = tegra_usb_phy_power_on(phy);
882
+	if (err)
883
+		goto close_phy;
886884 
887885 	return 0;
888886 
889
-fail:
887
+close_phy:
888
+	if (!phy->is_ulpi_phy)
889
+		utmip_pad_close(phy);
890
+
891
+disable_vbus:
892
+	regulator_disable(phy->vbus);
893
+
894
+disable_clk:
890895 	clk_disable_unprepare(phy->pll_u);
896
+
897
+	phy->freq = NULL;
898
+
891899 	return err;
892900 }
893901 
894
-void tegra_usb_phy_preresume(struct usb_phy *x)
902
+void tegra_usb_phy_preresume(struct usb_phy *u_phy)
895903 {
896
-	struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
904
+	struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
897905 
898906 	if (!phy->is_ulpi_phy)
899907 		utmi_phy_preresume(phy);
900908 }
901909 EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume);
902910 
903
-void tegra_usb_phy_postresume(struct usb_phy *x)
911
+void tegra_usb_phy_postresume(struct usb_phy *u_phy)
904912 {
905
-	struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
913
+	struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
906914 
907915 	if (!phy->is_ulpi_phy)
908916 		utmi_phy_postresume(phy);
909917 }
910918 EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume);
911919 
912
-void tegra_ehci_phy_restore_start(struct usb_phy *x,
913
-				 enum tegra_usb_phy_port_speed port_speed)
920
+void tegra_ehci_phy_restore_start(struct usb_phy *u_phy,
921
+				  enum tegra_usb_phy_port_speed port_speed)
914922 {
915
-	struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
923
+	struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
916924 
917925 	if (!phy->is_ulpi_phy)
918926 		utmi_phy_restore_start(phy, port_speed);
919927 }
920928 EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start);
921929 
922
-void tegra_ehci_phy_restore_end(struct usb_phy *x)
930
+void tegra_ehci_phy_restore_end(struct usb_phy *u_phy)
923931 {
924
-	struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
932
+	struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
925933 
926934 	if (!phy->is_ulpi_phy)
927935 		utmi_phy_restore_end(phy);
....@@ -932,21 +940,25 @@
932940 			   u8 *dest)
933941 {
934942 	u32 value;
935
-	int err = of_property_read_u32(pdev->dev.of_node, param, &value);
936
-	*dest = (u8)value;
937
-	if (err < 0)
943
+	int err;
944
+
945
+	err = of_property_read_u32(pdev->dev.of_node, param, &value);
946
+	if (err)
938947 		dev_err(&pdev->dev,
939948 			"Failed to read USB UTMI parameter %s: %d\n",
940949 			param, err);
950
+	else
951
+		*dest = value;
952
+
941953 	return err;
942954 }
943955 
944956 static int utmi_phy_probe(struct tegra_usb_phy *tegra_phy,
945957 			  struct platform_device *pdev)
946958 {
959
+	struct tegra_utmip_config *config;
947960 	struct resource *res;
948961 	int err;
949
-	struct tegra_utmip_config *config;
950962 
951963 	tegra_phy->is_ulpi_phy = false;
952964 
....@@ -956,8 +968,12 @@
956968 		return  -ENXIO;
957969 	}
958970 
971
+	/*
972
+	 * Note that UTMI pad registers are shared by all PHYs, therefore
973
+	 * devm_platform_ioremap_resource() can't be used here.
974
+	 */
959975 	tegra_phy->pad_regs = devm_ioremap(&pdev->dev, res->start,
960
-		resource_size(res));
976
+					   resource_size(res));
961977 	if (!tegra_phy->pad_regs) {
962978 		dev_err(&pdev->dev, "Failed to remap UTMI pad regs\n");
963979 		return -ENOMEM;
....@@ -971,49 +987,49 @@
971987 	config = tegra_phy->config;
972988 
973989 	err = read_utmi_param(pdev, "nvidia,hssync-start-delay",
974
-		&config->hssync_start_delay);
975
-	if (err < 0)
990
+			      &config->hssync_start_delay);
991
+	if (err)
976992 		return err;
977993 
978994 	err = read_utmi_param(pdev, "nvidia,elastic-limit",
979
-		&config->elastic_limit);
980
-	if (err < 0)
995
+			      &config->elastic_limit);
996
+	if (err)
981997 		return err;
982998 
983999 	err = read_utmi_param(pdev, "nvidia,idle-wait-delay",
984
-		&config->idle_wait_delay);
985
-	if (err < 0)
1000
+			      &config->idle_wait_delay);
1001
+	if (err)
9861002 		return err;
9871003 
9881004 	err = read_utmi_param(pdev, "nvidia,term-range-adj",
989
-		&config->term_range_adj);
990
-	if (err < 0)
1005
+			      &config->term_range_adj);
1006
+	if (err)
9911007 		return err;
9921008 
9931009 	err = read_utmi_param(pdev, "nvidia,xcvr-lsfslew",
994
-		&config->xcvr_lsfslew);
995
-	if (err < 0)
1010
+			      &config->xcvr_lsfslew);
1011
+	if (err)
9961012 		return err;
9971013 
9981014 	err = read_utmi_param(pdev, "nvidia,xcvr-lsrslew",
999
-		&config->xcvr_lsrslew);
1000
-	if (err < 0)
1015
+			      &config->xcvr_lsrslew);
1016
+	if (err)
10011017 		return err;
10021018 
10031019 	if (tegra_phy->soc_config->requires_extra_tuning_parameters) {
10041020 		err = read_utmi_param(pdev, "nvidia,xcvr-hsslew",
1005
-			&config->xcvr_hsslew);
1006
-		if (err < 0)
1021
+				      &config->xcvr_hsslew);
1022
+		if (err)
10071023 			return err;
10081024 
10091025 		err = read_utmi_param(pdev, "nvidia,hssquelch-level",
1010
-			&config->hssquelch_level);
1011
-		if (err < 0)
1026
+				      &config->hssquelch_level);
1027
+		if (err)
10121028 			return err;
10131029 
10141030 		err = read_utmi_param(pdev, "nvidia,hsdiscon-level",
1015
-			&config->hsdiscon_level);
1016
-		if (err < 0)
1031
+				      &config->hsdiscon_level);
1032
+		if (err)
10171033 			return err;
10181034 	}
10191035 
....@@ -1022,8 +1038,8 @@
10221038 
10231039 	if (!config->xcvr_setup_use_fuses) {
10241040 		err = read_utmi_param(pdev, "nvidia,xcvr-setup",
1025
-			&config->xcvr_setup);
1026
-		if (err < 0)
1041
+				      &config->xcvr_setup);
1042
+		if (err)
10271043 			return err;
10281044 	}
10291045 
....@@ -1053,23 +1069,20 @@
10531069 
10541070 static int tegra_usb_phy_probe(struct platform_device *pdev)
10551071 {
1056
-	const struct of_device_id *match;
1057
-	struct resource *res;
1058
-	struct tegra_usb_phy *tegra_phy = NULL;
10591072 	struct device_node *np = pdev->dev.of_node;
1073
+	struct tegra_usb_phy *tegra_phy;
10601074 	enum usb_phy_interface phy_type;
1075
+	struct reset_control *reset;
1076
+	struct gpio_desc *gpiod;
1077
+	struct resource *res;
1078
+	struct usb_phy *phy;
10611079 	int err;
10621080 
10631081 	tegra_phy = devm_kzalloc(&pdev->dev, sizeof(*tegra_phy), GFP_KERNEL);
10641082 	if (!tegra_phy)
10651083 		return -ENOMEM;
10661084 
1067
-	match = of_match_device(tegra_usb_phy_id_table, &pdev->dev);
1068
-	if (!match) {
1069
-		dev_err(&pdev->dev, "Error: No device match found\n");
1070
-		return -ENODEV;
1071
-	}
1072
-	tegra_phy->soc_config = match->data;
1085
+	tegra_phy->soc_config = of_device_get_match_data(&pdev->dev);
10731086 
10741087 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
10751088 	if (!res) {
....@@ -1077,8 +1090,12 @@
10771090 		return  -ENXIO;
10781091 	}
10791092 
1093
+	/*
1094
+	 * Note that PHY and USB controller are using shared registers,
1095
+	 * therefore devm_platform_ioremap_resource() can't be used here.
1096
+	 */
10801097 	tegra_phy->regs = devm_ioremap(&pdev->dev, res->start,
1081
-		resource_size(res));
1098
+				       resource_size(res));
10821099 	if (!tegra_phy->regs) {
10831100 		dev_err(&pdev->dev, "Failed to remap I/O memory\n");
10841101 		return -ENOMEM;
....@@ -1086,33 +1103,6 @@
10861103 
10871104 	tegra_phy->is_legacy_phy =
10881105 		of_property_read_bool(np, "nvidia,has-legacy-mode");
1089
-
1090
-	phy_type = of_usb_get_phy_mode(np);
1091
-	switch (phy_type) {
1092
-	case USBPHY_INTERFACE_MODE_UTMI:
1093
-		err = utmi_phy_probe(tegra_phy, pdev);
1094
-		if (err < 0)
1095
-			return err;
1096
-		break;
1097
-
1098
-	case USBPHY_INTERFACE_MODE_ULPI:
1099
-		tegra_phy->is_ulpi_phy = true;
1100
-
1101
-		tegra_phy->reset_gpio =
1102
-			of_get_named_gpio(np, "nvidia,phy-reset-gpio", 0);
1103
-		if (!gpio_is_valid(tegra_phy->reset_gpio)) {
1104
-			dev_err(&pdev->dev,
1105
-				"Invalid GPIO: %d\n", tegra_phy->reset_gpio);
1106
-			return tegra_phy->reset_gpio;
1107
-		}
1108
-		tegra_phy->config = NULL;
1109
-		break;
1110
-
1111
-	default:
1112
-		dev_err(&pdev->dev, "phy_type %u is invalid or unsupported\n",
1113
-			phy_type);
1114
-		return -EINVAL;
1115
-	}
11161106 
11171107 	if (of_find_property(np, "dr_mode", NULL))
11181108 		tegra_phy->mode = usb_get_dr_mode(&pdev->dev);
....@@ -1125,31 +1115,91 @@
11251115 	}
11261116 
11271117 	/* On some boards, the VBUS regulator doesn't need to be controlled */
1128
-	if (of_find_property(np, "vbus-supply", NULL)) {
1129
-		tegra_phy->vbus = devm_regulator_get(&pdev->dev, "vbus");
1130
-		if (IS_ERR(tegra_phy->vbus))
1131
-			return PTR_ERR(tegra_phy->vbus);
1132
-	} else {
1133
-		dev_notice(&pdev->dev, "no vbus regulator");
1134
-		tegra_phy->vbus = ERR_PTR(-ENODEV);
1118
+	tegra_phy->vbus = devm_regulator_get(&pdev->dev, "vbus");
1119
+	if (IS_ERR(tegra_phy->vbus))
1120
+		return PTR_ERR(tegra_phy->vbus);
1121
+
1122
+	tegra_phy->pll_u = devm_clk_get(&pdev->dev, "pll_u");
1123
+	err = PTR_ERR_OR_ZERO(tegra_phy->pll_u);
1124
+	if (err) {
1125
+		dev_err(&pdev->dev, "Failed to get pll_u clock: %d\n", err);
1126
+		return err;
1127
+	}
1128
+
1129
+	phy_type = of_usb_get_phy_mode(np);
1130
+	switch (phy_type) {
1131
+	case USBPHY_INTERFACE_MODE_UTMI:
1132
+		err = utmi_phy_probe(tegra_phy, pdev);
1133
+		if (err)
1134
+			return err;
1135
+
1136
+		tegra_phy->pad_clk = devm_clk_get(&pdev->dev, "utmi-pads");
1137
+		err = PTR_ERR_OR_ZERO(tegra_phy->pad_clk);
1138
+		if (err) {
1139
+			dev_err(&pdev->dev,
1140
+				"Failed to get UTMIP pad clock: %d\n", err);
1141
+			return err;
1142
+		}
1143
+
1144
+		reset = devm_reset_control_get_optional_shared(&pdev->dev,
1145
+							       "utmi-pads");
1146
+		err = PTR_ERR_OR_ZERO(reset);
1147
+		if (err) {
1148
+			dev_err(&pdev->dev,
1149
+				"Failed to get UTMI-pads reset: %d\n", err);
1150
+			return err;
1151
+		}
1152
+		tegra_phy->pad_rst = reset;
1153
+		break;
1154
+
1155
+	case USBPHY_INTERFACE_MODE_ULPI:
1156
+		tegra_phy->is_ulpi_phy = true;
1157
+
1158
+		tegra_phy->clk = devm_clk_get(&pdev->dev, "ulpi-link");
1159
+		err = PTR_ERR_OR_ZERO(tegra_phy->clk);
1160
+		if (err) {
1161
+			dev_err(&pdev->dev,
1162
+				"Failed to get ULPI clock: %d\n", err);
1163
+			return err;
1164
+		}
1165
+
1166
+		gpiod = devm_gpiod_get_from_of_node(&pdev->dev, np,
1167
+						    "nvidia,phy-reset-gpio",
1168
+						    0, GPIOD_OUT_HIGH,
1169
+						    "ulpi_phy_reset_b");
1170
+		err = PTR_ERR_OR_ZERO(gpiod);
1171
+		if (err) {
1172
+			dev_err(&pdev->dev,
1173
+				"Request failed for reset GPIO: %d\n", err);
1174
+			return err;
1175
+		}
1176
+		tegra_phy->reset_gpio = gpiod;
1177
+
1178
+		phy = devm_otg_ulpi_create(&pdev->dev,
1179
+					   &ulpi_viewport_access_ops, 0);
1180
+		if (!phy) {
1181
+			dev_err(&pdev->dev, "Failed to create ULPI OTG\n");
1182
+			return -ENOMEM;
1183
+		}
1184
+
1185
+		tegra_phy->ulpi = phy;
1186
+		tegra_phy->ulpi->io_priv = tegra_phy->regs + ULPI_VIEWPORT;
1187
+		break;
1188
+
1189
+	default:
1190
+		dev_err(&pdev->dev, "phy_type %u is invalid or unsupported\n",
1191
+			phy_type);
1192
+		return -EINVAL;
11351193 	}
11361194 
11371195 	tegra_phy->u_phy.dev = &pdev->dev;
1138
-	err = tegra_usb_phy_init(tegra_phy);
1139
-	if (err < 0)
1140
-		return err;
1141
-
1142
-	tegra_phy->u_phy.set_suspend = tegra_usb_phy_suspend;
1196
+	tegra_phy->u_phy.init = tegra_usb_phy_init;
1197
+	tegra_phy->u_phy.shutdown = tegra_usb_phy_shutdown;
1198
+	tegra_phy->u_phy.set_suspend = tegra_usb_phy_set_suspend;
11431199 
11441200 	platform_set_drvdata(pdev, tegra_phy);
11451201 
1146
-	err = usb_add_phy_dev(&tegra_phy->u_phy);
1147
-	if (err < 0) {
1148
-		tegra_usb_phy_close(tegra_phy);
1149
-		return err;
1150
-	}
1151
-
1152
-	return 0;
1202
+	return usb_add_phy_dev(&tegra_phy->u_phy);
11531203 }
11541204 
11551205 static int tegra_usb_phy_remove(struct platform_device *pdev)
....@@ -1157,7 +1207,6 @@
11571207 	struct tegra_usb_phy *tegra_phy = platform_get_drvdata(pdev);
11581208 
11591209 	usb_remove_phy(&tegra_phy->u_phy);
1160
-	tegra_usb_phy_close(tegra_phy);
11611210 
11621211 	return 0;
11631212 }