.. | .. |
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266 | 266 | int i; |
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267 | 267 | void *next_uncached; |
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268 | 268 | struct esas2r_request *first_request, *last_request; |
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| 269 | + bool dma64 = false; |
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269 | 270 | |
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270 | 271 | if (index >= MAX_ADAPTERS) { |
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271 | 272 | esas2r_log(ESAS2R_LOG_CRIT, |
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.. | .. |
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286 | 287 | a->pcid = pcid; |
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287 | 288 | a->host = host; |
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288 | 289 | |
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289 | | - if (sizeof(dma_addr_t) > 4) { |
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290 | | - const uint64_t required_mask = dma_get_required_mask |
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291 | | - (&pcid->dev); |
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292 | | - if (required_mask > DMA_BIT_MASK(32) |
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293 | | - && !pci_set_dma_mask(pcid, DMA_BIT_MASK(64)) |
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294 | | - && !pci_set_consistent_dma_mask(pcid, |
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295 | | - DMA_BIT_MASK(64))) { |
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296 | | - esas2r_log_dev(ESAS2R_LOG_INFO, |
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297 | | - &(a->pcid->dev), |
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298 | | - "64-bit PCI addressing enabled\n"); |
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299 | | - } else if (!pci_set_dma_mask(pcid, DMA_BIT_MASK(32)) |
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300 | | - && !pci_set_consistent_dma_mask(pcid, |
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301 | | - DMA_BIT_MASK(32))) { |
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302 | | - esas2r_log_dev(ESAS2R_LOG_INFO, |
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303 | | - &(a->pcid->dev), |
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304 | | - "32-bit PCI addressing enabled\n"); |
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305 | | - } else { |
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306 | | - esas2r_log(ESAS2R_LOG_CRIT, |
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307 | | - "failed to set DMA mask"); |
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308 | | - esas2r_kill_adapter(index); |
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309 | | - return 0; |
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310 | | - } |
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311 | | - } else { |
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312 | | - if (!pci_set_dma_mask(pcid, DMA_BIT_MASK(32)) |
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313 | | - && !pci_set_consistent_dma_mask(pcid, |
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314 | | - DMA_BIT_MASK(32))) { |
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315 | | - esas2r_log_dev(ESAS2R_LOG_INFO, |
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316 | | - &(a->pcid->dev), |
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317 | | - "32-bit PCI addressing enabled\n"); |
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318 | | - } else { |
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319 | | - esas2r_log(ESAS2R_LOG_CRIT, |
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320 | | - "failed to set DMA mask"); |
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321 | | - esas2r_kill_adapter(index); |
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322 | | - return 0; |
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323 | | - } |
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| 290 | + if (sizeof(dma_addr_t) > 4 && |
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| 291 | + dma_get_required_mask(&pcid->dev) > DMA_BIT_MASK(32) && |
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| 292 | + !dma_set_mask_and_coherent(&pcid->dev, DMA_BIT_MASK(64))) |
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| 293 | + dma64 = true; |
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| 294 | + |
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| 295 | + if (!dma64 && dma_set_mask_and_coherent(&pcid->dev, DMA_BIT_MASK(32))) { |
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| 296 | + esas2r_log(ESAS2R_LOG_CRIT, "failed to set DMA mask"); |
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| 297 | + esas2r_kill_adapter(index); |
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| 298 | + return 0; |
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324 | 299 | } |
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| 300 | + |
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| 301 | + esas2r_log_dev(ESAS2R_LOG_INFO, &pcid->dev, |
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| 302 | + "%s-bit PCI addressing enabled\n", dma64 ? "64" : "32"); |
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| 303 | + |
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325 | 304 | esas2r_adapters[index] = a; |
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326 | 305 | sprintf(a->name, ESAS2R_DRVR_NAME "_%02d", index); |
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327 | 306 | esas2r_debug("new adapter %p, name %s", a, a->name); |
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.. | .. |
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783 | 762 | |
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784 | 763 | static void esas2r_init_pci_cfg_space(struct esas2r_adapter *a) |
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785 | 764 | { |
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786 | | - int pcie_cap_reg; |
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787 | | - |
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788 | | - pcie_cap_reg = pci_find_capability(a->pcid, PCI_CAP_ID_EXP); |
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789 | | - if (pcie_cap_reg) { |
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| 765 | + if (pci_is_pcie(a->pcid)) { |
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790 | 766 | u16 devcontrol; |
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791 | 767 | |
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792 | | - pci_read_config_word(a->pcid, pcie_cap_reg + PCI_EXP_DEVCTL, |
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793 | | - &devcontrol); |
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| 768 | + pcie_capability_read_word(a->pcid, PCI_EXP_DEVCTL, &devcontrol); |
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794 | 769 | |
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795 | 770 | if ((devcontrol & PCI_EXP_DEVCTL_READRQ) > |
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796 | 771 | PCI_EXP_DEVCTL_READRQ_512B) { |
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.. | .. |
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799 | 774 | |
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800 | 775 | devcontrol &= ~PCI_EXP_DEVCTL_READRQ; |
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801 | 776 | devcontrol |= PCI_EXP_DEVCTL_READRQ_512B; |
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802 | | - pci_write_config_word(a->pcid, |
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803 | | - pcie_cap_reg + PCI_EXP_DEVCTL, |
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804 | | - devcontrol); |
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| 777 | + pcie_capability_write_word(a->pcid, PCI_EXP_DEVCTL, |
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| 778 | + devcontrol); |
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805 | 779 | } |
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806 | 780 | } |
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807 | 781 | } |
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.. | .. |
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1262 | 1236 | a->init_msg = ESAS2R_INIT_MSG_GET_INIT; |
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1263 | 1237 | break; |
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1264 | 1238 | } |
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| 1239 | + fallthrough; |
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1265 | 1240 | |
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1266 | 1241 | case ESAS2R_INIT_MSG_GET_INIT: |
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1267 | 1242 | if (msg == ESAS2R_INIT_MSG_GET_INIT) { |
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.. | .. |
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1275 | 1250 | esas2r_hdebug("FAILED"); |
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1276 | 1251 | } |
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1277 | 1252 | } |
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1278 | | - /* fall through */ |
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| 1253 | + fallthrough; |
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1279 | 1254 | |
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1280 | 1255 | default: |
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1281 | 1256 | rq->req_stat = RS_SUCCESS; |
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