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2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390 
 kernel/drivers/rtc/rtc-tegra.c
....@@ -1,21 +1,8 @@
1
+// SPDX-License-Identifier: GPL-2.0+
12 /*
23  * An RTC driver for the NVIDIA Tegra 200 series internal RTC.
34  *
4
- * Copyright (c) 2010, NVIDIA Corporation.
5
- *
6
- * This program is free software; you can redistribute it and/or modify
7
- * it under the terms of the GNU General Public License as published by
8
- * the Free Software Foundation; either version 2 of the License, or
9
- * (at your option) any later version.
10
- *
11
- * This program is distributed in the hope that it will be useful, but WITHOUT
12
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14
- * more details.
15
- *
16
- * You should have received a copy of the GNU General Public License along
17
- * with this program; if not, write to the Free Software Foundation, Inc.,
18
- * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
5
+ * Copyright (c) 2010-2019, NVIDIA Corporation.
196  */
207 
218 #include <linux/clk.h>
....@@ -31,10 +18,10 @@
3118 #include <linux/rtc.h>
3219 #include <linux/slab.h>
3320 
34
-/* set to 1 = busy every eight 32kHz clocks during copy of sec+msec to AHB */
21
+/* Set to 1 = busy every eight 32 kHz clocks during copy of sec+msec to AHB. */
3522 #define TEGRA_RTC_REG_BUSY			0x004
3623 #define TEGRA_RTC_REG_SECONDS			0x008
37
-/* when msec is read, the seconds are buffered into shadow seconds. */
24
+/* When msec is read, the seconds are buffered into shadow seconds. */
3825 #define TEGRA_RTC_REG_SHADOW_SECONDS		0x00c
3926 #define TEGRA_RTC_REG_MILLI_SECONDS		0x010
4027 #define TEGRA_RTC_REG_SECONDS_ALARM0		0x014
....@@ -59,44 +46,48 @@
5946 #define TEGRA_RTC_INTR_STATUS_SEC_ALARM0	(1<<0)
6047 
6148 struct tegra_rtc_info {
62
-	struct platform_device	*pdev;
63
-	struct rtc_device	*rtc_dev;
64
-	void __iomem		*rtc_base; /* NULL if not initialized. */
65
-	struct clk		*clk;
66
-	int			tegra_rtc_irq; /* alarm and periodic irq */
67
-	spinlock_t		tegra_rtc_lock;
49
+	struct platform_device *pdev;
50
+	struct rtc_device *rtc;
51
+	void __iomem *base; /* NULL if not initialized */
52
+	struct clk *clk;
53
+	int irq; /* alarm and periodic IRQ */
54
+	spinlock_t lock;
6855 };
6956 
70
-/* RTC hardware is busy when it is updating its values over AHB once
71
- * every eight 32kHz clocks (~250uS).
72
- * outside of these updates the CPU is free to write.
73
- * CPU is always free to read.
57
+/*
58
+ * RTC hardware is busy when it is updating its values over AHB once every
59
+ * eight 32 kHz clocks (~250 us). Outside of these updates the CPU is free to
60
+ * write. CPU is always free to read.
7461  */
7562 static inline u32 tegra_rtc_check_busy(struct tegra_rtc_info *info)
7663 {
77
-	return readl(info->rtc_base + TEGRA_RTC_REG_BUSY) & 1;
64
+	return readl(info->base + TEGRA_RTC_REG_BUSY) & 1;
7865 }
7966 
80
-/* Wait for hardware to be ready for writing.
81
- * This function tries to maximize the amount of time before the next update.
82
- * It does this by waiting for the RTC to become busy with its periodic update,
83
- * then returning once the RTC first becomes not busy.
67
+/*
68
+ * Wait for hardware to be ready for writing. This function tries to maximize
69
+ * the amount of time before the next update. It does this by waiting for the
70
+ * RTC to become busy with its periodic update, then returning once the RTC
71
+ * first becomes not busy.
72
+ *
8473  * This periodic update (where the seconds and milliseconds are copied to the
85
- * AHB side) occurs every eight 32kHz clocks (~250uS).
86
- * The behavior of this function allows us to make some assumptions without
87
- * introducing a race, because 250uS is plenty of time to read/write a value.
74
+ * AHB side) occurs every eight 32 kHz clocks (~250 us). The behavior of this
75
+ * function allows us to make some assumptions without introducing a race,
76
+ * because 250 us is plenty of time to read/write a value.
8877  */
8978 static int tegra_rtc_wait_while_busy(struct device *dev)
9079 {
9180 	struct tegra_rtc_info *info = dev_get_drvdata(dev);
81
+	int retries = 500; /* ~490 us is the worst case, ~250 us is best */
9282 
93
-	int retries = 500; /* ~490 us is the worst case, ~250 us is best. */
94
-
95
-	/* first wait for the RTC to become busy. this is when it
96
-	 * posts its updated seconds+msec registers to AHB side. */
83
+	/*
84
+	 * First wait for the RTC to become busy. This is when it posts its
85
+	 * updated seconds+msec registers to AHB side.
86
+	 */
9787 	while (tegra_rtc_check_busy(info)) {
9888 		if (!retries--)
9989 			goto retry_failed;
90
+
10091 		udelay(1);
10192 	}
10293 
....@@ -104,36 +95,30 @@
10495 	return 0;
10596 
10697 retry_failed:
107
-	dev_err(dev, "write failed:retry count exceeded.\n");
98
+	dev_err(dev, "write failed: retry count exceeded\n");
10899 	return -ETIMEDOUT;
109100 }
110101 
111102 static int tegra_rtc_read_time(struct device *dev, struct rtc_time *tm)
112103 {
113104 	struct tegra_rtc_info *info = dev_get_drvdata(dev);
114
-	unsigned long sec, msec;
115
-	unsigned long sl_irq_flags;
105
+	unsigned long flags;
106
+	u32 sec;
116107 
117
-	/* RTC hardware copies seconds to shadow seconds when a read
118
-	 * of milliseconds occurs. use a lock to keep other threads out. */
119
-	spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
108
+	/*
109
+	 * RTC hardware copies seconds to shadow seconds when a read of
110
+	 * milliseconds occurs. use a lock to keep other threads out.
111
+	 */
112
+	spin_lock_irqsave(&info->lock, flags);
120113 
121
-	msec = readl(info->rtc_base + TEGRA_RTC_REG_MILLI_SECONDS);
122
-	sec = readl(info->rtc_base + TEGRA_RTC_REG_SHADOW_SECONDS);
114
+	readl(info->base + TEGRA_RTC_REG_MILLI_SECONDS);
115
+	sec = readl(info->base + TEGRA_RTC_REG_SHADOW_SECONDS);
123116 
124
-	spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
117
+	spin_unlock_irqrestore(&info->lock, flags);
125118 
126
-	rtc_time_to_tm(sec, tm);
119
+	rtc_time64_to_tm(sec, tm);
127120 
128
-	dev_vdbg(dev, "time read as %lu. %d/%d/%d %d:%02u:%02u\n",
129
-		sec,
130
-		tm->tm_mon + 1,
131
-		tm->tm_mday,
132
-		tm->tm_year + 1900,
133
-		tm->tm_hour,
134
-		tm->tm_min,
135
-		tm->tm_sec
136
-	);
121
+	dev_vdbg(dev, "time read as %u, %ptR\n", sec, tm);
137122 
138123 	return 0;
139124 }
....@@ -141,29 +126,21 @@
141126 static int tegra_rtc_set_time(struct device *dev, struct rtc_time *tm)
142127 {
143128 	struct tegra_rtc_info *info = dev_get_drvdata(dev);
144
-	unsigned long sec;
129
+	u32 sec;
145130 	int ret;
146131 
147
-	/* convert tm to seconds. */
148
-	rtc_tm_to_time(tm, &sec);
132
+	/* convert tm to seconds */
133
+	sec = rtc_tm_to_time64(tm);
149134 
150
-	dev_vdbg(dev, "time set to %lu. %d/%d/%d %d:%02u:%02u\n",
151
-		sec,
152
-		tm->tm_mon+1,
153
-		tm->tm_mday,
154
-		tm->tm_year+1900,
155
-		tm->tm_hour,
156
-		tm->tm_min,
157
-		tm->tm_sec
158
-	);
135
+	dev_vdbg(dev, "time set to %u, %ptR\n", sec, tm);
159136 
160
-	/* seconds only written if wait succeeded. */
137
+	/* seconds only written if wait succeeded */
161138 	ret = tegra_rtc_wait_while_busy(dev);
162139 	if (!ret)
163
-		writel(sec, info->rtc_base + TEGRA_RTC_REG_SECONDS);
140
+		writel(sec, info->base + TEGRA_RTC_REG_SECONDS);
164141 
165142 	dev_vdbg(dev, "time read back as %d\n",
166
-		readl(info->rtc_base + TEGRA_RTC_REG_SECONDS));
143
+		 readl(info->base + TEGRA_RTC_REG_SECONDS));
167144 
168145 	return ret;
169146 }
....@@ -171,22 +148,21 @@
171148 static int tegra_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
172149 {
173150 	struct tegra_rtc_info *info = dev_get_drvdata(dev);
174
-	unsigned long sec;
175
-	unsigned tmp;
151
+	u32 sec, value;
176152 
177
-	sec = readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
153
+	sec = readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0);
178154 
179155 	if (sec == 0) {
180
-		/* alarm is disabled. */
156
+		/* alarm is disabled */
181157 		alarm->enabled = 0;
182158 	} else {
183
-		/* alarm is enabled. */
159
+		/* alarm is enabled */
184160 		alarm->enabled = 1;
185
-		rtc_time_to_tm(sec, &alarm->time);
161
+		rtc_time64_to_tm(sec, &alarm->time);
186162 	}
187163 
188
-	tmp = readl(info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
189
-	alarm->pending = (tmp & TEGRA_RTC_INTR_STATUS_SEC_ALARM0) != 0;
164
+	value = readl(info->base + TEGRA_RTC_REG_INTR_STATUS);
165
+	alarm->pending = (value & TEGRA_RTC_INTR_STATUS_SEC_ALARM0) != 0;
190166 
191167 	return 0;
192168 }
....@@ -194,22 +170,22 @@
194170 static int tegra_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
195171 {
196172 	struct tegra_rtc_info *info = dev_get_drvdata(dev);
197
-	unsigned status;
198
-	unsigned long sl_irq_flags;
173
+	unsigned long flags;
174
+	u32 status;
199175 
200176 	tegra_rtc_wait_while_busy(dev);
201
-	spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
177
+	spin_lock_irqsave(&info->lock, flags);
202178 
203
-	/* read the original value, and OR in the flag. */
204
-	status = readl(info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
179
+	/* read the original value, and OR in the flag */
180
+	status = readl(info->base + TEGRA_RTC_REG_INTR_MASK);
205181 	if (enabled)
206182 		status |= TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* set it */
207183 	else
208184 		status &= ~TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* clear it */
209185 
210
-	writel(status, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
186
+	writel(status, info->base + TEGRA_RTC_REG_INTR_MASK);
211187 
212
-	spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
188
+	spin_unlock_irqrestore(&info->lock, flags);
213189 
214190 	return 0;
215191 }
....@@ -217,32 +193,24 @@
217193 static int tegra_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
218194 {
219195 	struct tegra_rtc_info *info = dev_get_drvdata(dev);
220
-	unsigned long sec;
196
+	u32 sec;
221197 
222198 	if (alarm->enabled)
223
-		rtc_tm_to_time(&alarm->time, &sec);
199
+		sec = rtc_tm_to_time64(&alarm->time);
224200 	else
225201 		sec = 0;
226202 
227203 	tegra_rtc_wait_while_busy(dev);
228
-	writel(sec, info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
204
+	writel(sec, info->base + TEGRA_RTC_REG_SECONDS_ALARM0);
229205 	dev_vdbg(dev, "alarm read back as %d\n",
230
-		readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0));
206
+		 readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0));
231207 
232208 	/* if successfully written and alarm is enabled ... */
233209 	if (sec) {
234210 		tegra_rtc_alarm_irq_enable(dev, 1);
235
-
236
-		dev_vdbg(dev, "alarm set as %lu. %d/%d/%d %d:%02u:%02u\n",
237
-			sec,
238
-			alarm->time.tm_mon+1,
239
-			alarm->time.tm_mday,
240
-			alarm->time.tm_year+1900,
241
-			alarm->time.tm_hour,
242
-			alarm->time.tm_min,
243
-			alarm->time.tm_sec);
211
+		dev_vdbg(dev, "alarm set as %u, %ptR\n", sec, &alarm->time);
244212 	} else {
245
-		/* disable alarm if 0 or write error. */
213
+		/* disable alarm if 0 or write error */
246214 		dev_vdbg(dev, "alarm disabled\n");
247215 		tegra_rtc_alarm_irq_enable(dev, 0);
248216 	}
....@@ -264,39 +232,39 @@
264232 {
265233 	struct device *dev = data;
266234 	struct tegra_rtc_info *info = dev_get_drvdata(dev);
267
-	unsigned long events = 0;
268
-	unsigned status;
269
-	unsigned long sl_irq_flags;
235
+	unsigned long events = 0, flags;
236
+	u32 status;
270237 
271
-	status = readl(info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
238
+	status = readl(info->base + TEGRA_RTC_REG_INTR_STATUS);
272239 	if (status) {
273
-		/* clear the interrupt masks and status on any irq. */
240
+		/* clear the interrupt masks and status on any IRQ */
274241 		tegra_rtc_wait_while_busy(dev);
275
-		spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
276
-		writel(0, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
277
-		writel(status, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
278
-		spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
242
+
243
+		spin_lock_irqsave(&info->lock, flags);
244
+		writel(0, info->base + TEGRA_RTC_REG_INTR_MASK);
245
+		writel(status, info->base + TEGRA_RTC_REG_INTR_STATUS);
246
+		spin_unlock_irqrestore(&info->lock, flags);
279247 	}
280248 
281
-	/* check if Alarm */
282
-	if ((status & TEGRA_RTC_INTR_STATUS_SEC_ALARM0))
249
+	/* check if alarm */
250
+	if (status & TEGRA_RTC_INTR_STATUS_SEC_ALARM0)
283251 		events |= RTC_IRQF | RTC_AF;
284252 
285
-	/* check if Periodic */
286
-	if ((status & TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM))
253
+	/* check if periodic */
254
+	if (status & TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM)
287255 		events |= RTC_IRQF | RTC_PF;
288256 
289
-	rtc_update_irq(info->rtc_dev, 1, events);
257
+	rtc_update_irq(info->rtc, 1, events);
290258 
291259 	return IRQ_HANDLED;
292260 }
293261 
294262 static const struct rtc_class_ops tegra_rtc_ops = {
295
-	.read_time	= tegra_rtc_read_time,
296
-	.set_time	= tegra_rtc_set_time,
297
-	.read_alarm	= tegra_rtc_read_alarm,
298
-	.set_alarm	= tegra_rtc_set_alarm,
299
-	.proc		= tegra_rtc_proc,
263
+	.read_time = tegra_rtc_read_time,
264
+	.set_time = tegra_rtc_set_time,
265
+	.read_alarm = tegra_rtc_read_alarm,
266
+	.set_alarm = tegra_rtc_set_alarm,
267
+	.proc = tegra_rtc_proc,
300268 	.alarm_irq_enable = tegra_rtc_alarm_irq_enable,
301269 };
302270 
....@@ -306,25 +274,31 @@
306274 };
307275 MODULE_DEVICE_TABLE(of, tegra_rtc_dt_match);
308276 
309
-static int __init tegra_rtc_probe(struct platform_device *pdev)
277
+static int tegra_rtc_probe(struct platform_device *pdev)
310278 {
311279 	struct tegra_rtc_info *info;
312
-	struct resource *res;
313280 	int ret;
314281 
315
-	info = devm_kzalloc(&pdev->dev, sizeof(struct tegra_rtc_info),
316
-		GFP_KERNEL);
282
+	info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
317283 	if (!info)
318284 		return -ENOMEM;
319285 
320
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
321
-	info->rtc_base = devm_ioremap_resource(&pdev->dev, res);
322
-	if (IS_ERR(info->rtc_base))
323
-		return PTR_ERR(info->rtc_base);
286
+	info->base = devm_platform_ioremap_resource(pdev, 0);
287
+	if (IS_ERR(info->base))
288
+		return PTR_ERR(info->base);
324289 
325
-	info->tegra_rtc_irq = platform_get_irq(pdev, 0);
326
-	if (info->tegra_rtc_irq <= 0)
327
-		return -EBUSY;
290
+	ret = platform_get_irq(pdev, 0);
291
+	if (ret <= 0)
292
+		return ret;
293
+
294
+	info->irq = ret;
295
+
296
+	info->rtc = devm_rtc_allocate_device(&pdev->dev);
297
+	if (IS_ERR(info->rtc))
298
+		return PTR_ERR(info->rtc);
299
+
300
+	info->rtc->ops = &tegra_rtc_ops;
301
+	info->rtc->range_max = U32_MAX;
328302 
329303 	info->clk = devm_clk_get(&pdev->dev, NULL);
330304 	if (IS_ERR(info->clk))
....@@ -334,38 +308,30 @@
334308 	if (ret < 0)
335309 		return ret;
336310 
337
-	/* set context info. */
311
+	/* set context info */
338312 	info->pdev = pdev;
339
-	spin_lock_init(&info->tegra_rtc_lock);
313
+	spin_lock_init(&info->lock);
340314 
341315 	platform_set_drvdata(pdev, info);
342316 
343
-	/* clear out the hardware. */
344
-	writel(0, info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
345
-	writel(0xffffffff, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
346
-	writel(0, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
317
+	/* clear out the hardware */
318
+	writel(0, info->base + TEGRA_RTC_REG_SECONDS_ALARM0);
319
+	writel(0xffffffff, info->base + TEGRA_RTC_REG_INTR_STATUS);
320
+	writel(0, info->base + TEGRA_RTC_REG_INTR_MASK);
347321 
348322 	device_init_wakeup(&pdev->dev, 1);
349323 
350
-	info->rtc_dev = devm_rtc_device_register(&pdev->dev,
351
-				dev_name(&pdev->dev), &tegra_rtc_ops,
352
-				THIS_MODULE);
353
-	if (IS_ERR(info->rtc_dev)) {
354
-		ret = PTR_ERR(info->rtc_dev);
355
-		dev_err(&pdev->dev, "Unable to register device (err=%d).\n",
356
-			ret);
324
+	ret = devm_request_irq(&pdev->dev, info->irq, tegra_rtc_irq_handler,
325
+			       IRQF_TRIGGER_HIGH, dev_name(&pdev->dev),
326
+			       &pdev->dev);
327
+	if (ret) {
328
+		dev_err(&pdev->dev, "failed to request interrupt: %d\n", ret);
357329 		goto disable_clk;
358330 	}
359331 
360
-	ret = devm_request_irq(&pdev->dev, info->tegra_rtc_irq,
361
-			tegra_rtc_irq_handler, IRQF_TRIGGER_HIGH,
362
-			dev_name(&pdev->dev), &pdev->dev);
363
-	if (ret) {
364
-		dev_err(&pdev->dev,
365
-			"Unable to request interrupt for device (err=%d).\n",
366
-			ret);
332
+	ret = rtc_register_device(info->rtc);
333
+	if (ret)
367334 		goto disable_clk;
368
-	}
369335 
370336 	dev_notice(&pdev->dev, "Tegra internal Real Time Clock\n");
371337 
....@@ -392,20 +358,20 @@
392358 
393359 	tegra_rtc_wait_while_busy(dev);
394360 
395
-	/* only use ALARM0 as a wake source. */
396
-	writel(0xffffffff, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
361
+	/* only use ALARM0 as a wake source */
362
+	writel(0xffffffff, info->base + TEGRA_RTC_REG_INTR_STATUS);
397363 	writel(TEGRA_RTC_INTR_STATUS_SEC_ALARM0,
398
-		info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
364
+	       info->base + TEGRA_RTC_REG_INTR_MASK);
399365 
400366 	dev_vdbg(dev, "alarm sec = %d\n",
401
-		readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0));
367
+		 readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0));
402368 
403
-	dev_vdbg(dev, "Suspend (device_may_wakeup=%d) irq:%d\n",
404
-		device_may_wakeup(dev), info->tegra_rtc_irq);
369
+	dev_vdbg(dev, "Suspend (device_may_wakeup=%d) IRQ:%d\n",
370
+		 device_may_wakeup(dev), info->irq);
405371 
406
-	/* leave the alarms on as a wake source. */
372
+	/* leave the alarms on as a wake source */
407373 	if (device_may_wakeup(dev))
408
-		enable_irq_wake(info->tegra_rtc_irq);
374
+		enable_irq_wake(info->irq);
409375 
410376 	return 0;
411377 }
....@@ -415,10 +381,11 @@
415381 	struct tegra_rtc_info *info = dev_get_drvdata(dev);
416382 
417383 	dev_vdbg(dev, "Resume (device_may_wakeup=%d)\n",
418
-		device_may_wakeup(dev));
419
-	/* alarms were left on as a wake source, turn them off. */
384
+		 device_may_wakeup(dev));
385
+
386
+	/* alarms were left on as a wake source, turn them off */
420387 	if (device_may_wakeup(dev))
421
-		disable_irq_wake(info->tegra_rtc_irq);
388
+		disable_irq_wake(info->irq);
422389 
423390 	return 0;
424391 }
....@@ -428,22 +395,21 @@
428395 
429396 static void tegra_rtc_shutdown(struct platform_device *pdev)
430397 {
431
-	dev_vdbg(&pdev->dev, "disabling interrupts.\n");
398
+	dev_vdbg(&pdev->dev, "disabling interrupts\n");
432399 	tegra_rtc_alarm_irq_enable(&pdev->dev, 0);
433400 }
434401 
435
-MODULE_ALIAS("platform:tegra_rtc");
436402 static struct platform_driver tegra_rtc_driver = {
437
-	.remove		= tegra_rtc_remove,
438
-	.shutdown	= tegra_rtc_shutdown,
439
-	.driver		= {
440
-		.name	= "tegra_rtc",
403
+	.probe = tegra_rtc_probe,
404
+	.remove = tegra_rtc_remove,
405
+	.shutdown = tegra_rtc_shutdown,
406
+	.driver = {
407
+		.name = "tegra_rtc",
441408 		.of_match_table = tegra_rtc_dt_match,
442
-		.pm	= &tegra_rtc_pm_ops,
409
+		.pm = &tegra_rtc_pm_ops,
443410 	},
444411 };
445
-
446
-module_platform_driver_probe(tegra_rtc_driver, tegra_rtc_probe);
412
+module_platform_driver(tegra_rtc_driver);
447413 
448414 MODULE_AUTHOR("Jon Mayo <jmayo@nvidia.com>");
449415 MODULE_DESCRIPTION("driver for Tegra internal RTC");