~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,3 +1,4 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
1	2	/*
2	3	* rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
3	4	*
..	..	@@ -5,10 +6,6 @@
5	6	* Copyright (C) 2006 David Brownell
6	7	* Copyright (C) 2009 Matthias Fuchs (rx8025 support)
7	8	* Copyright (C) 2012 Bertrand Achard (nvram access fixes)
8		- *
9		- * This program is free software; you can redistribute it and/or modify
10		- * it under the terms of the GNU General Public License version 2 as
11		- * published by the Free Software Foundation.
12	9	*/
13	10
14	11	#include <linux/acpi.h>
..	..	@@ -25,6 +22,7 @@
25	22	#include <linux/hwmon-sysfs.h>
26	23	#include <linux/clk-provider.h>
27	24	#include <linux/regmap.h>
	25	+#include <linux/watchdog.h>
28	26
29	27	/*
30	28	* We can't determine type by probing, but if we expect pre-Linux code
..	..	@@ -114,6 +112,60 @@
114	112	# define RX8025_BIT_VDET 0x40
115	113	# define RX8025_BIT_XST 0x20
116	114
	115	+#define RX8130_REG_ALARM_MIN 0x17
	116	+#define RX8130_REG_ALARM_HOUR 0x18
	117	+#define RX8130_REG_ALARM_WEEK_OR_DAY 0x19
	118	+#define RX8130_REG_EXTENSION 0x1c
	119	+#define RX8130_REG_EXTENSION_WADA BIT(3)
	120	+#define RX8130_REG_FLAG 0x1d
	121	+#define RX8130_REG_FLAG_VLF BIT(1)
	122	+#define RX8130_REG_FLAG_AF BIT(3)
	123	+#define RX8130_REG_CONTROL0 0x1e
	124	+#define RX8130_REG_CONTROL0_AIE BIT(3)
	125	+#define RX8130_REG_CONTROL1 0x1f
	126	+#define RX8130_REG_CONTROL1_INIEN BIT(4)
	127	+#define RX8130_REG_CONTROL1_CHGEN BIT(5)
	128	+
	129	+#define MCP794XX_REG_CONTROL 0x07
	130	+# define MCP794XX_BIT_ALM0_EN 0x10
	131	+# define MCP794XX_BIT_ALM1_EN 0x20
	132	+#define MCP794XX_REG_ALARM0_BASE 0x0a
	133	+#define MCP794XX_REG_ALARM0_CTRL 0x0d
	134	+#define MCP794XX_REG_ALARM1_BASE 0x11
	135	+#define MCP794XX_REG_ALARM1_CTRL 0x14
	136	+# define MCP794XX_BIT_ALMX_IF BIT(3)
	137	+# define MCP794XX_BIT_ALMX_C0 BIT(4)
	138	+# define MCP794XX_BIT_ALMX_C1 BIT(5)
	139	+# define MCP794XX_BIT_ALMX_C2 BIT(6)
	140	+# define MCP794XX_BIT_ALMX_POL BIT(7)
	141	+# define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 \| \
	142	+ MCP794XX_BIT_ALMX_C1 \| \
	143	+ MCP794XX_BIT_ALMX_C2)
	144	+
	145	+#define M41TXX_REG_CONTROL 0x07
	146	+# define M41TXX_BIT_OUT BIT(7)
	147	+# define M41TXX_BIT_FT BIT(6)
	148	+# define M41TXX_BIT_CALIB_SIGN BIT(5)
	149	+# define M41TXX_M_CALIBRATION GENMASK(4, 0)
	150	+
	151	+#define DS1388_REG_WDOG_HUN_SECS 0x08
	152	+#define DS1388_REG_WDOG_SECS 0x09
	153	+#define DS1388_REG_FLAG 0x0b
	154	+# define DS1388_BIT_WF BIT(6)
	155	+# define DS1388_BIT_OSF BIT(7)
	156	+#define DS1388_REG_CONTROL 0x0c
	157	+# define DS1388_BIT_RST BIT(0)
	158	+# define DS1388_BIT_WDE BIT(1)
	159	+# define DS1388_BIT_nEOSC BIT(7)
	160	+
	161	+/* negative offset step is -2.034ppm */
	162	+#define M41TXX_NEG_OFFSET_STEP_PPB 2034
	163	+/* positive offset step is +4.068ppm */
	164	+#define M41TXX_POS_OFFSET_STEP_PPB 4068
	165	+/* Min and max values supported with 'offset' interface by M41TXX */
	166	+#define M41TXX_MIN_OFFSET ((-31) * M41TXX_NEG_OFFSET_STEP_PPB)
	167	+#define M41TXX_MAX_OFFSET ((31) * M41TXX_POS_OFFSET_STEP_PPB)
	168	+
117	169	struct ds1307 {
118	170	enum ds_type type;
119	171	unsigned long flags;
..	..	@@ -142,19 +194,776 @@
142	194	u16 trickle_charger_reg;
143	195	u8 (do_trickle_setup)(struct ds1307 , u32,
144	196	bool);
	197	+ /* Does the RTC require trickle-resistor-ohms to select the value of
	198	+ * the resistor between Vcc and Vbackup?
	199	+ */
	200	+ bool requires_trickle_resistor;
	201	+ /* Some RTC's batteries and supercaps were charged by default, others
	202	+ * allow charging but were not configured previously to do so.
	203	+ * Remember this behavior to stay backwards compatible.
	204	+ */
	205	+ bool charge_default;
145	206	};
146	207
147		-static int ds1307_get_time(struct device dev, struct rtc_time t);
148		-static int ds1307_set_time(struct device dev, struct rtc_time t);
149		-static u8 do_trickle_setup_ds1339(struct ds1307 *, u32 ohms, bool diode);
150		-static irqreturn_t rx8130_irq(int irq, void *dev_id);
151		-static int rx8130_read_alarm(struct device dev, struct rtc_wkalrm t);
152		-static int rx8130_set_alarm(struct device dev, struct rtc_wkalrm t);
153		-static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled);
154		-static irqreturn_t mcp794xx_irq(int irq, void *dev_id);
155		-static int mcp794xx_read_alarm(struct device dev, struct rtc_wkalrm t);
156		-static int mcp794xx_set_alarm(struct device dev, struct rtc_wkalrm t);
157		-static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled);
	208	+static const struct chip_desc chips[last_ds_type];
	209	+
	210	+static int ds1307_get_time(struct device dev, struct rtc_time t)
	211	+{
	212	+ struct ds1307 *ds1307 = dev_get_drvdata(dev);
	213	+ int tmp, ret;
	214	+ const struct chip_desc *chip = &chips[ds1307->type];
	215	+ u8 regs[7];
	216	+
	217	+ if (ds1307->type == rx_8130) {
	218	+ unsigned int regflag;
	219	+ ret = regmap_read(ds1307->regmap, RX8130_REG_FLAG, &regflag);
	220	+ if (ret) {
	221	+ dev_err(dev, "%s error %d\n", "read", ret);
	222	+ return ret;
	223	+ }
	224	+
	225	+ if (regflag & RX8130_REG_FLAG_VLF) {
	226	+ dev_warn_once(dev, "oscillator failed, set time!\n");
	227	+ return -EINVAL;
	228	+ }
	229	+ }
	230	+
	231	+ /* read the RTC date and time registers all at once */
	232	+ ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
	233	+ sizeof(regs));
	234	+ if (ret) {
	235	+ dev_err(dev, "%s error %d\n", "read", ret);
	236	+ return ret;
	237	+ }
	238	+
	239	+ dev_dbg(dev, "%s: %7ph\n", "read", regs);
	240	+
	241	+ /* if oscillator fail bit is set, no data can be trusted */
	242	+ if (ds1307->type == m41t0 &&
	243	+ regs[DS1307_REG_MIN] & M41T0_BIT_OF) {
	244	+ dev_warn_once(dev, "oscillator failed, set time!\n");
	245	+ return -EINVAL;
	246	+ }
	247	+
	248	+ tmp = regs[DS1307_REG_SECS];
	249	+ switch (ds1307->type) {
	250	+ case ds_1307:
	251	+ case m41t0:
	252	+ case m41t00:
	253	+ case m41t11:
	254	+ if (tmp & DS1307_BIT_CH)
	255	+ return -EINVAL;
	256	+ break;
	257	+ case ds_1308:
	258	+ case ds_1338:
	259	+ if (tmp & DS1307_BIT_CH)
	260	+ return -EINVAL;
	261	+
	262	+ ret = regmap_read(ds1307->regmap, DS1307_REG_CONTROL, &tmp);
	263	+ if (ret)
	264	+ return ret;
	265	+ if (tmp & DS1338_BIT_OSF)
	266	+ return -EINVAL;
	267	+ break;
	268	+ case ds_1340:
	269	+ if (tmp & DS1340_BIT_nEOSC)
	270	+ return -EINVAL;
	271	+
	272	+ ret = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp);
	273	+ if (ret)
	274	+ return ret;
	275	+ if (tmp & DS1340_BIT_OSF)
	276	+ return -EINVAL;
	277	+ break;
	278	+ case ds_1388:
	279	+ ret = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &tmp);
	280	+ if (ret)
	281	+ return ret;
	282	+ if (tmp & DS1388_BIT_OSF)
	283	+ return -EINVAL;
	284	+ break;
	285	+ case mcp794xx:
	286	+ if (!(tmp & MCP794XX_BIT_ST))
	287	+ return -EINVAL;
	288	+
	289	+ break;
	290	+ default:
	291	+ break;
	292	+ }
	293	+
	294	+ t->tm_sec = bcd2bin(regs[DS1307_REG_SECS] & 0x7f);
	295	+ t->tm_min = bcd2bin(regs[DS1307_REG_MIN] & 0x7f);
	296	+ tmp = regs[DS1307_REG_HOUR] & 0x3f;
	297	+ t->tm_hour = bcd2bin(tmp);
	298	+ /* rx8130 is bit position, not BCD */
	299	+ if (ds1307->type == rx_8130)
	300	+ t->tm_wday = fls(regs[DS1307_REG_WDAY] & 0x7f);
	301	+ else
	302	+ t->tm_wday = bcd2bin(regs[DS1307_REG_WDAY] & 0x07) - 1;
	303	+ t->tm_mday = bcd2bin(regs[DS1307_REG_MDAY] & 0x3f);
	304	+ tmp = regs[DS1307_REG_MONTH] & 0x1f;
	305	+ t->tm_mon = bcd2bin(tmp) - 1;
	306	+ t->tm_year = bcd2bin(regs[DS1307_REG_YEAR]) + 100;
	307	+
	308	+ if (regs[chip->century_reg] & chip->century_bit &&
	309	+ IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY))
	310	+ t->tm_year += 100;
	311	+
	312	+ dev_dbg(dev, "%s secs=%d, mins=%d, "
	313	+ "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
	314	+ "read", t->tm_sec, t->tm_min,
	315	+ t->tm_hour, t->tm_mday,
	316	+ t->tm_mon, t->tm_year, t->tm_wday);
	317	+
	318	+ return 0;
	319	+}
	320	+
	321	+static int ds1307_set_time(struct device dev, struct rtc_time t)
	322	+{
	323	+ struct ds1307 *ds1307 = dev_get_drvdata(dev);
	324	+ const struct chip_desc *chip = &chips[ds1307->type];
	325	+ int result;
	326	+ int tmp;
	327	+ u8 regs[7];
	328	+
	329	+ dev_dbg(dev, "%s secs=%d, mins=%d, "
	330	+ "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
	331	+ "write", t->tm_sec, t->tm_min,
	332	+ t->tm_hour, t->tm_mday,
	333	+ t->tm_mon, t->tm_year, t->tm_wday);
	334	+
	335	+ if (t->tm_year < 100)
	336	+ return -EINVAL;
	337	+
	338	+#ifdef CONFIG_RTC_DRV_DS1307_CENTURY
	339	+ if (t->tm_year > (chip->century_bit ? 299 : 199))
	340	+ return -EINVAL;
	341	+#else
	342	+ if (t->tm_year > 199)
	343	+ return -EINVAL;
	344	+#endif
	345	+
	346	+ regs[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
	347	+ regs[DS1307_REG_MIN] = bin2bcd(t->tm_min);
	348	+ regs[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
	349	+ /* rx8130 is bit position, not BCD */
	350	+ if (ds1307->type == rx_8130)
	351	+ regs[DS1307_REG_WDAY] = 1 << t->tm_wday;
	352	+ else
	353	+ regs[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
	354	+ regs[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
	355	+ regs[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
	356	+
	357	+ /* assume 20YY not 19YY */
	358	+ tmp = t->tm_year - 100;
	359	+ regs[DS1307_REG_YEAR] = bin2bcd(tmp);
	360	+
	361	+ if (chip->century_enable_bit)
	362	+ regs[chip->century_reg] \|= chip->century_enable_bit;
	363	+ if (t->tm_year > 199 && chip->century_bit)
	364	+ regs[chip->century_reg] \|= chip->century_bit;
	365	+
	366	+ switch (ds1307->type) {
	367	+ case ds_1308:
	368	+ case ds_1338:
	369	+ regmap_update_bits(ds1307->regmap, DS1307_REG_CONTROL,
	370	+ DS1338_BIT_OSF, 0);
	371	+ break;
	372	+ case ds_1340:
	373	+ regmap_update_bits(ds1307->regmap, DS1340_REG_FLAG,
	374	+ DS1340_BIT_OSF, 0);
	375	+ break;
	376	+ case ds_1388:
	377	+ regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG,
	378	+ DS1388_BIT_OSF, 0);
	379	+ break;
	380	+ case mcp794xx:
	381	+ /*
	382	+ * these bits were cleared when preparing the date/time
	383	+ * values and need to be set again before writing the
	384	+ * regsfer out to the device.
	385	+ */
	386	+ regs[DS1307_REG_SECS] \|= MCP794XX_BIT_ST;
	387	+ regs[DS1307_REG_WDAY] \|= MCP794XX_BIT_VBATEN;
	388	+ break;
	389	+ default:
	390	+ break;
	391	+ }
	392	+
	393	+ dev_dbg(dev, "%s: %7ph\n", "write", regs);
	394	+
	395	+ result = regmap_bulk_write(ds1307->regmap, chip->offset, regs,
	396	+ sizeof(regs));
	397	+ if (result) {
	398	+ dev_err(dev, "%s error %d\n", "write", result);
	399	+ return result;
	400	+ }
	401	+
	402	+ if (ds1307->type == rx_8130) {
	403	+ /* clear Voltage Loss Flag as data is available now */
	404	+ result = regmap_write(ds1307->regmap, RX8130_REG_FLAG,
	405	+ ~(u8)RX8130_REG_FLAG_VLF);
	406	+ if (result) {
	407	+ dev_err(dev, "%s error %d\n", "write", result);
	408	+ return result;
	409	+ }
	410	+ }
	411	+
	412	+ return 0;
	413	+}
	414	+
	415	+static int ds1337_read_alarm(struct device dev, struct rtc_wkalrm t)
	416	+{
	417	+ struct ds1307 *ds1307 = dev_get_drvdata(dev);
	418	+ int ret;
	419	+ u8 regs[9];
	420	+
	421	+ if (!test_bit(HAS_ALARM, &ds1307->flags))
	422	+ return -EINVAL;
	423	+
	424	+ /* read all ALARM1, ALARM2, and status registers at once */
	425	+ ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS,
	426	+ regs, sizeof(regs));
	427	+ if (ret) {
	428	+ dev_err(dev, "%s error %d\n", "alarm read", ret);
	429	+ return ret;
	430	+ }
	431	+
	432	+ dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read",
	433	+ &regs[0], &regs[4], &regs[7]);
	434	+
	435	+ /*
	436	+ * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
	437	+ * and that all four fields are checked matches
	438	+ */
	439	+ t->time.tm_sec = bcd2bin(regs[0] & 0x7f);
	440	+ t->time.tm_min = bcd2bin(regs[1] & 0x7f);
	441	+ t->time.tm_hour = bcd2bin(regs[2] & 0x3f);
	442	+ t->time.tm_mday = bcd2bin(regs[3] & 0x3f);
	443	+
	444	+ /* ... and status */
	445	+ t->enabled = !!(regs[7] & DS1337_BIT_A1IE);
	446	+ t->pending = !!(regs[8] & DS1337_BIT_A1I);
	447	+
	448	+ dev_dbg(dev, "%s secs=%d, mins=%d, "
	449	+ "hours=%d, mday=%d, enabled=%d, pending=%d\n",
	450	+ "alarm read", t->time.tm_sec, t->time.tm_min,
	451	+ t->time.tm_hour, t->time.tm_mday,
	452	+ t->enabled, t->pending);
	453	+
	454	+ return 0;
	455	+}
	456	+
	457	+static int ds1337_set_alarm(struct device dev, struct rtc_wkalrm t)
	458	+{
	459	+ struct ds1307 *ds1307 = dev_get_drvdata(dev);
	460	+ unsigned char regs[9];
	461	+ u8 control, status;
	462	+ int ret;
	463	+
	464	+ if (!test_bit(HAS_ALARM, &ds1307->flags))
	465	+ return -EINVAL;
	466	+
	467	+ dev_dbg(dev, "%s secs=%d, mins=%d, "
	468	+ "hours=%d, mday=%d, enabled=%d, pending=%d\n",
	469	+ "alarm set", t->time.tm_sec, t->time.tm_min,
	470	+ t->time.tm_hour, t->time.tm_mday,
	471	+ t->enabled, t->pending);
	472	+
	473	+ /* read current status of both alarms and the chip */
	474	+ ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
	475	+ sizeof(regs));
	476	+ if (ret) {
	477	+ dev_err(dev, "%s error %d\n", "alarm write", ret);
	478	+ return ret;
	479	+ }
	480	+ control = regs[7];
	481	+ status = regs[8];
	482	+
	483	+ dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)",
	484	+ &regs[0], &regs[4], control, status);
	485	+
	486	+ /* set ALARM1, using 24 hour and day-of-month modes */
	487	+ regs[0] = bin2bcd(t->time.tm_sec);
	488	+ regs[1] = bin2bcd(t->time.tm_min);
	489	+ regs[2] = bin2bcd(t->time.tm_hour);
	490	+ regs[3] = bin2bcd(t->time.tm_mday);
	491	+
	492	+ /* set ALARM2 to non-garbage */
	493	+ regs[4] = 0;
	494	+ regs[5] = 0;
	495	+ regs[6] = 0;
	496	+
	497	+ /* disable alarms */
	498	+ regs[7] = control & ~(DS1337_BIT_A1IE \| DS1337_BIT_A2IE);
	499	+ regs[8] = status & ~(DS1337_BIT_A1I \| DS1337_BIT_A2I);
	500	+
	501	+ ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
	502	+ sizeof(regs));
	503	+ if (ret) {
	504	+ dev_err(dev, "can't set alarm time\n");
	505	+ return ret;
	506	+ }
	507	+
	508	+ /* optionally enable ALARM1 */
	509	+ if (t->enabled) {
	510	+ dev_dbg(dev, "alarm IRQ armed\n");
	511	+ regs[7] \|= DS1337_BIT_A1IE; /* only ALARM1 is used */
	512	+ regmap_write(ds1307->regmap, DS1337_REG_CONTROL, regs[7]);
	513	+ }
	514	+
	515	+ return 0;
	516	+}
	517	+
	518	+static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
	519	+{
	520	+ struct ds1307 *ds1307 = dev_get_drvdata(dev);
	521	+
	522	+ if (!test_bit(HAS_ALARM, &ds1307->flags))
	523	+ return -ENOTTY;
	524	+
	525	+ return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
	526	+ DS1337_BIT_A1IE,
	527	+ enabled ? DS1337_BIT_A1IE : 0);
	528	+}
	529	+
	530	+static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307, u32 ohms, bool diode)
	531	+{
	532	+ u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
	533	+ DS1307_TRICKLE_CHARGER_NO_DIODE;
	534	+
	535	+ setup \|= DS13XX_TRICKLE_CHARGER_MAGIC;
	536	+
	537	+ switch (ohms) {
	538	+ case 250:
	539	+ setup \|= DS1307_TRICKLE_CHARGER_250_OHM;
	540	+ break;
	541	+ case 2000:
	542	+ setup \|= DS1307_TRICKLE_CHARGER_2K_OHM;
	543	+ break;
	544	+ case 4000:
	545	+ setup \|= DS1307_TRICKLE_CHARGER_4K_OHM;
	546	+ break;
	547	+ default:
	548	+ dev_warn(ds1307->dev,
	549	+ "Unsupported ohm value %u in dt\n", ohms);
	550	+ return 0;
	551	+ }
	552	+ return setup;
	553	+}
	554	+
	555	+static u8 do_trickle_setup_rx8130(struct ds1307 *ds1307, u32 ohms, bool diode)
	556	+{
	557	+ /* make sure that the backup battery is enabled */
	558	+ u8 setup = RX8130_REG_CONTROL1_INIEN;
	559	+ if (diode)
	560	+ setup \|= RX8130_REG_CONTROL1_CHGEN;
	561	+
	562	+ return setup;
	563	+}
	564	+
	565	+static irqreturn_t rx8130_irq(int irq, void *dev_id)
	566	+{
	567	+ struct ds1307 *ds1307 = dev_id;
	568	+ struct mutex *lock = &ds1307->rtc->ops_lock;
	569	+ u8 ctl[3];
	570	+ int ret;
	571	+
	572	+ mutex_lock(lock);
	573	+
	574	+ /* Read control registers. */
	575	+ ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
	576	+ sizeof(ctl));
	577	+ if (ret < 0)
	578	+ goto out;
	579	+ if (!(ctl[1] & RX8130_REG_FLAG_AF))
	580	+ goto out;
	581	+ ctl[1] &= ~RX8130_REG_FLAG_AF;
	582	+ ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
	583	+
	584	+ ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
	585	+ sizeof(ctl));
	586	+ if (ret < 0)
	587	+ goto out;
	588	+
	589	+ rtc_update_irq(ds1307->rtc, 1, RTC_AF \| RTC_IRQF);
	590	+
	591	+out:
	592	+ mutex_unlock(lock);
	593	+
	594	+ return IRQ_HANDLED;
	595	+}
	596	+
	597	+static int rx8130_read_alarm(struct device dev, struct rtc_wkalrm t)
	598	+{
	599	+ struct ds1307 *ds1307 = dev_get_drvdata(dev);
	600	+ u8 ald[3], ctl[3];
	601	+ int ret;
	602	+
	603	+ if (!test_bit(HAS_ALARM, &ds1307->flags))
	604	+ return -EINVAL;
	605	+
	606	+ /* Read alarm registers. */
	607	+ ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
	608	+ sizeof(ald));
	609	+ if (ret < 0)
	610	+ return ret;
	611	+
	612	+ /* Read control registers. */
	613	+ ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
	614	+ sizeof(ctl));
	615	+ if (ret < 0)
	616	+ return ret;
	617	+
	618	+ t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE);
	619	+ t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF);
	620	+
	621	+ /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
	622	+ t->time.tm_sec = -1;
	623	+ t->time.tm_min = bcd2bin(ald[0] & 0x7f);
	624	+ t->time.tm_hour = bcd2bin(ald[1] & 0x7f);
	625	+ t->time.tm_wday = -1;
	626	+ t->time.tm_mday = bcd2bin(ald[2] & 0x7f);
	627	+ t->time.tm_mon = -1;
	628	+ t->time.tm_year = -1;
	629	+ t->time.tm_yday = -1;
	630	+ t->time.tm_isdst = -1;
	631	+
	632	+ dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n",
	633	+ __func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
	634	+ t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled);
	635	+
	636	+ return 0;
	637	+}
	638	+
	639	+static int rx8130_set_alarm(struct device dev, struct rtc_wkalrm t)
	640	+{
	641	+ struct ds1307 *ds1307 = dev_get_drvdata(dev);
	642	+ u8 ald[3], ctl[3];
	643	+ int ret;
	644	+
	645	+ if (!test_bit(HAS_ALARM, &ds1307->flags))
	646	+ return -EINVAL;
	647	+
	648	+ dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
	649	+ "enabled=%d pending=%d\n", __func__,
	650	+ t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
	651	+ t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
	652	+ t->enabled, t->pending);
	653	+
	654	+ /* Read control registers. */
	655	+ ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
	656	+ sizeof(ctl));
	657	+ if (ret < 0)
	658	+ return ret;
	659	+
	660	+ ctl[0] &= RX8130_REG_EXTENSION_WADA;
	661	+ ctl[1] &= ~RX8130_REG_FLAG_AF;
	662	+ ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
	663	+
	664	+ ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
	665	+ sizeof(ctl));
	666	+ if (ret < 0)
	667	+ return ret;
	668	+
	669	+ /* Hardware alarm precision is 1 minute! */
	670	+ ald[0] = bin2bcd(t->time.tm_min);
	671	+ ald[1] = bin2bcd(t->time.tm_hour);
	672	+ ald[2] = bin2bcd(t->time.tm_mday);
	673	+
	674	+ ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
	675	+ sizeof(ald));
	676	+ if (ret < 0)
	677	+ return ret;
	678	+
	679	+ if (!t->enabled)
	680	+ return 0;
	681	+
	682	+ ctl[2] \|= RX8130_REG_CONTROL0_AIE;
	683	+
	684	+ return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, ctl[2]);
	685	+}
	686	+
	687	+static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled)
	688	+{
	689	+ struct ds1307 *ds1307 = dev_get_drvdata(dev);
	690	+ int ret, reg;
	691	+
	692	+ if (!test_bit(HAS_ALARM, &ds1307->flags))
	693	+ return -EINVAL;
	694	+
	695	+ ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, &reg);
	696	+ if (ret < 0)
	697	+ return ret;
	698	+
	699	+ if (enabled)
	700	+ reg \|= RX8130_REG_CONTROL0_AIE;
	701	+ else
	702	+ reg &= ~RX8130_REG_CONTROL0_AIE;
	703	+
	704	+ return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg);
	705	+}
	706	+
	707	+static irqreturn_t mcp794xx_irq(int irq, void *dev_id)
	708	+{
	709	+ struct ds1307 *ds1307 = dev_id;
	710	+ struct mutex *lock = &ds1307->rtc->ops_lock;
	711	+ int reg, ret;
	712	+
	713	+ mutex_lock(lock);
	714	+
	715	+ /* Check and clear alarm 0 interrupt flag. */
	716	+ ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, &reg);
	717	+ if (ret)
	718	+ goto out;
	719	+ if (!(reg & MCP794XX_BIT_ALMX_IF))
	720	+ goto out;
	721	+ reg &= ~MCP794XX_BIT_ALMX_IF;
	722	+ ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg);
	723	+ if (ret)
	724	+ goto out;
	725	+
	726	+ /* Disable alarm 0. */
	727	+ ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
	728	+ MCP794XX_BIT_ALM0_EN, 0);
	729	+ if (ret)
	730	+ goto out;
	731	+
	732	+ rtc_update_irq(ds1307->rtc, 1, RTC_AF \| RTC_IRQF);
	733	+
	734	+out:
	735	+ mutex_unlock(lock);
	736	+
	737	+ return IRQ_HANDLED;
	738	+}
	739	+
	740	+static int mcp794xx_read_alarm(struct device dev, struct rtc_wkalrm t)
	741	+{
	742	+ struct ds1307 *ds1307 = dev_get_drvdata(dev);
	743	+ u8 regs[10];
	744	+ int ret;
	745	+
	746	+ if (!test_bit(HAS_ALARM, &ds1307->flags))
	747	+ return -EINVAL;
	748	+
	749	+ /* Read control and alarm 0 registers. */
	750	+ ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
	751	+ sizeof(regs));
	752	+ if (ret)
	753	+ return ret;
	754	+
	755	+ t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN);
	756	+
	757	+ /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
	758	+ t->time.tm_sec = bcd2bin(regs[3] & 0x7f);
	759	+ t->time.tm_min = bcd2bin(regs[4] & 0x7f);
	760	+ t->time.tm_hour = bcd2bin(regs[5] & 0x3f);
	761	+ t->time.tm_wday = bcd2bin(regs[6] & 0x7) - 1;
	762	+ t->time.tm_mday = bcd2bin(regs[7] & 0x3f);
	763	+ t->time.tm_mon = bcd2bin(regs[8] & 0x1f) - 1;
	764	+ t->time.tm_year = -1;
	765	+ t->time.tm_yday = -1;
	766	+ t->time.tm_isdst = -1;
	767	+
	768	+ dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
	769	+ "enabled=%d polarity=%d irq=%d match=%lu\n", __func__,
	770	+ t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
	771	+ t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
	772	+ !!(regs[6] & MCP794XX_BIT_ALMX_POL),
	773	+ !!(regs[6] & MCP794XX_BIT_ALMX_IF),
	774	+ (regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4);
	775	+
	776	+ return 0;
	777	+}
	778	+
	779	+/*
	780	+ * We may have a random RTC weekday, therefore calculate alarm weekday based
	781	+ * on current weekday we read from the RTC timekeeping regs
	782	+ */
	783	+static int mcp794xx_alm_weekday(struct device dev, struct rtc_time tm_alarm)
	784	+{
	785	+ struct rtc_time tm_now;
	786	+ int days_now, days_alarm, ret;
	787	+
	788	+ ret = ds1307_get_time(dev, &tm_now);
	789	+ if (ret)
	790	+ return ret;
	791	+
	792	+ days_now = div_s64(rtc_tm_to_time64(&tm_now), 24 * 60 * 60);
	793	+ days_alarm = div_s64(rtc_tm_to_time64(tm_alarm), 24 * 60 * 60);
	794	+
	795	+ return (tm_now.tm_wday + days_alarm - days_now) % 7 + 1;
	796	+}
	797	+
	798	+static int mcp794xx_set_alarm(struct device dev, struct rtc_wkalrm t)
	799	+{
	800	+ struct ds1307 *ds1307 = dev_get_drvdata(dev);
	801	+ unsigned char regs[10];
	802	+ int wday, ret;
	803	+
	804	+ if (!test_bit(HAS_ALARM, &ds1307->flags))
	805	+ return -EINVAL;
	806	+
	807	+ wday = mcp794xx_alm_weekday(dev, &t->time);
	808	+ if (wday < 0)
	809	+ return wday;
	810	+
	811	+ dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
	812	+ "enabled=%d pending=%d\n", __func__,
	813	+ t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
	814	+ t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
	815	+ t->enabled, t->pending);
	816	+
	817	+ /* Read control and alarm 0 registers. */
	818	+ ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
	819	+ sizeof(regs));
	820	+ if (ret)
	821	+ return ret;
	822	+
	823	+ /* Set alarm 0, using 24-hour and day-of-month modes. */
	824	+ regs[3] = bin2bcd(t->time.tm_sec);
	825	+ regs[4] = bin2bcd(t->time.tm_min);
	826	+ regs[5] = bin2bcd(t->time.tm_hour);
	827	+ regs[6] = wday;
	828	+ regs[7] = bin2bcd(t->time.tm_mday);
	829	+ regs[8] = bin2bcd(t->time.tm_mon + 1);
	830	+
	831	+ /* Clear the alarm 0 interrupt flag. */
	832	+ regs[6] &= ~MCP794XX_BIT_ALMX_IF;
	833	+ /* Set alarm match: second, minute, hour, day, date, month. */
	834	+ regs[6] \|= MCP794XX_MSK_ALMX_MATCH;
	835	+ /* Disable interrupt. We will not enable until completely programmed */
	836	+ regs[0] &= ~MCP794XX_BIT_ALM0_EN;
	837	+
	838	+ ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
	839	+ sizeof(regs));
	840	+ if (ret)
	841	+ return ret;
	842	+
	843	+ if (!t->enabled)
	844	+ return 0;
	845	+ regs[0] \|= MCP794XX_BIT_ALM0_EN;
	846	+ return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]);
	847	+}
	848	+
	849	+static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)
	850	+{
	851	+ struct ds1307 *ds1307 = dev_get_drvdata(dev);
	852	+
	853	+ if (!test_bit(HAS_ALARM, &ds1307->flags))
	854	+ return -EINVAL;
	855	+
	856	+ return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
	857	+ MCP794XX_BIT_ALM0_EN,
	858	+ enabled ? MCP794XX_BIT_ALM0_EN : 0);
	859	+}
	860	+
	861	+static int m41txx_rtc_read_offset(struct device dev, long offset)
	862	+{
	863	+ struct ds1307 *ds1307 = dev_get_drvdata(dev);
	864	+ unsigned int ctrl_reg;
	865	+ u8 val;
	866	+
	867	+ regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
	868	+
	869	+ val = ctrl_reg & M41TXX_M_CALIBRATION;
	870	+
	871	+ /* check if positive */
	872	+ if (ctrl_reg & M41TXX_BIT_CALIB_SIGN)
	873	+ offset = (val M41TXX_POS_OFFSET_STEP_PPB);
	874	+ else
	875	+ offset = -(val M41TXX_NEG_OFFSET_STEP_PPB);
	876	+
	877	+ return 0;
	878	+}
	879	+
	880	+static int m41txx_rtc_set_offset(struct device *dev, long offset)
	881	+{
	882	+ struct ds1307 *ds1307 = dev_get_drvdata(dev);
	883	+ unsigned int ctrl_reg;
	884	+
	885	+ if ((offset < M41TXX_MIN_OFFSET) \|\| (offset > M41TXX_MAX_OFFSET))
	886	+ return -ERANGE;
	887	+
	888	+ if (offset >= 0) {
	889	+ ctrl_reg = DIV_ROUND_CLOSEST(offset,
	890	+ M41TXX_POS_OFFSET_STEP_PPB);
	891	+ ctrl_reg \|= M41TXX_BIT_CALIB_SIGN;
	892	+ } else {
	893	+ ctrl_reg = DIV_ROUND_CLOSEST(abs(offset),
	894	+ M41TXX_NEG_OFFSET_STEP_PPB);
	895	+ }
	896	+
	897	+ return regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL,
	898	+ M41TXX_M_CALIBRATION \| M41TXX_BIT_CALIB_SIGN,
	899	+ ctrl_reg);
	900	+}
	901	+
	902	+#ifdef CONFIG_WATCHDOG_CORE
	903	+static int ds1388_wdt_start(struct watchdog_device *wdt_dev)
	904	+{
	905	+ struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
	906	+ u8 regs[2];
	907	+ int ret;
	908	+
	909	+ ret = regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG,
	910	+ DS1388_BIT_WF, 0);
	911	+ if (ret)
	912	+ return ret;
	913	+
	914	+ ret = regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
	915	+ DS1388_BIT_WDE \| DS1388_BIT_RST, 0);
	916	+ if (ret)
	917	+ return ret;
	918	+
	919	+ /*
	920	+ * watchdog timeouts are measured in seconds. So ignore hundredths of
	921	+ * seconds field.
	922	+ */
	923	+ regs[0] = 0;
	924	+ regs[1] = bin2bcd(wdt_dev->timeout);
	925	+
	926	+ ret = regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
	927	+ sizeof(regs));
	928	+ if (ret)
	929	+ return ret;
	930	+
	931	+ return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
	932	+ DS1388_BIT_WDE \| DS1388_BIT_RST,
	933	+ DS1388_BIT_WDE \| DS1388_BIT_RST);
	934	+}
	935	+
	936	+static int ds1388_wdt_stop(struct watchdog_device *wdt_dev)
	937	+{
	938	+ struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
	939	+
	940	+ return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
	941	+ DS1388_BIT_WDE \| DS1388_BIT_RST, 0);
	942	+}
	943	+
	944	+static int ds1388_wdt_ping(struct watchdog_device *wdt_dev)
	945	+{
	946	+ struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
	947	+ u8 regs[2];
	948	+
	949	+ return regmap_bulk_read(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
	950	+ sizeof(regs));
	951	+}
	952	+
	953	+static int ds1388_wdt_set_timeout(struct watchdog_device *wdt_dev,
	954	+ unsigned int val)
	955	+{
	956	+ struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
	957	+ u8 regs[2];
	958	+
	959	+ wdt_dev->timeout = val;
	960	+ regs[0] = 0;
	961	+ regs[1] = bin2bcd(wdt_dev->timeout);
	962	+
	963	+ return regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
	964	+ sizeof(regs));
	965	+}
	966	+#endif
158	967
159	968	static const struct rtc_class_ops rx8130_rtc_ops = {
160	969	.read_time = ds1307_get_time,
..	..	@@ -170,6 +979,16 @@
170	979	.read_alarm = mcp794xx_read_alarm,
171	980	.set_alarm = mcp794xx_set_alarm,
172	981	.alarm_irq_enable = mcp794xx_alarm_irq_enable,
	982	+};
	983	+
	984	+static const struct rtc_class_ops m41txx_rtc_ops = {
	985	+ .read_time = ds1307_get_time,
	986	+ .set_time = ds1307_set_time,
	987	+ .read_alarm = ds1337_read_alarm,
	988	+ .set_alarm = ds1337_set_alarm,
	989	+ .alarm_irq_enable = ds1307_alarm_irq_enable,
	990	+ .read_offset = m41txx_rtc_read_offset,
	991	+ .set_offset = m41txx_rtc_set_offset,
173	992	};
174	993
175	994	static const struct chip_desc chips[last_ds_type] = {
..	..	@@ -197,6 +1016,8 @@
197	1016	.bbsqi_bit = DS1339_BIT_BBSQI,
198	1017	.trickle_charger_reg = 0x10,
199	1018	.do_trickle_setup = &do_trickle_setup_ds1339,
	1019	+ .requires_trickle_resistor = true,
	1020	+ .charge_default = true,
200	1021	},
201	1022	[ds_1340] = {
202	1023	.century_reg = DS1307_REG_HOUR,
..	..	@@ -204,6 +1025,8 @@
204	1025	.century_bit = DS1340_BIT_CENTURY,
205	1026	.do_trickle_setup = &do_trickle_setup_ds1339,
206	1027	.trickle_charger_reg = 0x08,
	1028	+ .requires_trickle_resistor = true,
	1029	+ .charge_default = true,
207	1030	},
208	1031	[ds_1341] = {
209	1032	.century_reg = DS1307_REG_MONTH,
..	..	@@ -227,11 +1050,20 @@
227	1050	.offset = 0x10,
228	1051	.irq_handler = rx8130_irq,
229	1052	.rtc_ops = &rx8130_rtc_ops,
	1053	+ .trickle_charger_reg = RX8130_REG_CONTROL1,
	1054	+ .do_trickle_setup = &do_trickle_setup_rx8130,
	1055	+ },
	1056	+ [m41t0] = {
	1057	+ .rtc_ops = &m41txx_rtc_ops,
	1058	+ },
	1059	+ [m41t00] = {
	1060	+ .rtc_ops = &m41txx_rtc_ops,
230	1061	},
231	1062	[m41t11] = {
232	1063	/* this is battery backed SRAM */
233	1064	.nvram_offset = 8,
234	1065	.nvram_size = 56,
	1066	+ .rtc_ops = &m41txx_rtc_ops,
235	1067	},
236	1068	[mcp794xx] = {
237	1069	.alarm = 1,
..	..	@@ -406,238 +1238,6 @@
406	1238
407	1239	/----------------------------------------------------------------------/
408	1240
409		-static int ds1307_get_time(struct device dev, struct rtc_time t)
410		-{
411		- struct ds1307 *ds1307 = dev_get_drvdata(dev);
412		- int tmp, ret;
413		- const struct chip_desc *chip = &chips[ds1307->type];
414		- u8 regs[7];
415		-
416		- /* read the RTC date and time registers all at once */
417		- ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
418		- sizeof(regs));
419		- if (ret) {
420		- dev_err(dev, "%s error %d\n", "read", ret);
421		- return ret;
422		- }
423		-
424		- dev_dbg(dev, "%s: %7ph\n", "read", regs);
425		-
426		- /* if oscillator fail bit is set, no data can be trusted */
427		- if (ds1307->type == m41t0 &&
428		- regs[DS1307_REG_MIN] & M41T0_BIT_OF) {
429		- dev_warn_once(dev, "oscillator failed, set time!\n");
430		- return -EINVAL;
431		- }
432		-
433		- t->tm_sec = bcd2bin(regs[DS1307_REG_SECS] & 0x7f);
434		- t->tm_min = bcd2bin(regs[DS1307_REG_MIN] & 0x7f);
435		- tmp = regs[DS1307_REG_HOUR] & 0x3f;
436		- t->tm_hour = bcd2bin(tmp);
437		- /* rx8130 is bit position, not BCD */
438		- if (ds1307->type == rx_8130)
439		- t->tm_wday = fls(regs[DS1307_REG_WDAY] & 0x7f);
440		- else
441		- t->tm_wday = bcd2bin(regs[DS1307_REG_WDAY] & 0x07) - 1;
442		- t->tm_mday = bcd2bin(regs[DS1307_REG_MDAY] & 0x3f);
443		- tmp = regs[DS1307_REG_MONTH] & 0x1f;
444		- t->tm_mon = bcd2bin(tmp) - 1;
445		- t->tm_year = bcd2bin(regs[DS1307_REG_YEAR]) + 100;
446		-
447		- if (regs[chip->century_reg] & chip->century_bit &&
448		- IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY))
449		- t->tm_year += 100;
450		-
451		- dev_dbg(dev, "%s secs=%d, mins=%d, "
452		- "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
453		- "read", t->tm_sec, t->tm_min,
454		- t->tm_hour, t->tm_mday,
455		- t->tm_mon, t->tm_year, t->tm_wday);
456		-
457		- return 0;
458		-}
459		-
460		-static int ds1307_set_time(struct device dev, struct rtc_time t)
461		-{
462		- struct ds1307 *ds1307 = dev_get_drvdata(dev);
463		- const struct chip_desc *chip = &chips[ds1307->type];
464		- int result;
465		- int tmp;
466		- u8 regs[7];
467		-
468		- dev_dbg(dev, "%s secs=%d, mins=%d, "
469		- "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
470		- "write", t->tm_sec, t->tm_min,
471		- t->tm_hour, t->tm_mday,
472		- t->tm_mon, t->tm_year, t->tm_wday);
473		-
474		- if (t->tm_year < 100)
475		- return -EINVAL;
476		-
477		-#ifdef CONFIG_RTC_DRV_DS1307_CENTURY
478		- if (t->tm_year > (chip->century_bit ? 299 : 199))
479		- return -EINVAL;
480		-#else
481		- if (t->tm_year > 199)
482		- return -EINVAL;
483		-#endif
484		-
485		- regs[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
486		- regs[DS1307_REG_MIN] = bin2bcd(t->tm_min);
487		- regs[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
488		- /* rx8130 is bit position, not BCD */
489		- if (ds1307->type == rx_8130)
490		- regs[DS1307_REG_WDAY] = 1 << t->tm_wday;
491		- else
492		- regs[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
493		- regs[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
494		- regs[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
495		-
496		- /* assume 20YY not 19YY */
497		- tmp = t->tm_year - 100;
498		- regs[DS1307_REG_YEAR] = bin2bcd(tmp);
499		-
500		- if (chip->century_enable_bit)
501		- regs[chip->century_reg] \|= chip->century_enable_bit;
502		- if (t->tm_year > 199 && chip->century_bit)
503		- regs[chip->century_reg] \|= chip->century_bit;
504		-
505		- if (ds1307->type == mcp794xx) {
506		- /*
507		- * these bits were cleared when preparing the date/time
508		- * values and need to be set again before writing the
509		- * regsfer out to the device.
510		- */
511		- regs[DS1307_REG_SECS] \|= MCP794XX_BIT_ST;
512		- regs[DS1307_REG_WDAY] \|= MCP794XX_BIT_VBATEN;
513		- }
514		-
515		- dev_dbg(dev, "%s: %7ph\n", "write", regs);
516		-
517		- result = regmap_bulk_write(ds1307->regmap, chip->offset, regs,
518		- sizeof(regs));
519		- if (result) {
520		- dev_err(dev, "%s error %d\n", "write", result);
521		- return result;
522		- }
523		- return 0;
524		-}
525		-
526		-static int ds1337_read_alarm(struct device dev, struct rtc_wkalrm t)
527		-{
528		- struct ds1307 *ds1307 = dev_get_drvdata(dev);
529		- int ret;
530		- u8 regs[9];
531		-
532		- if (!test_bit(HAS_ALARM, &ds1307->flags))
533		- return -EINVAL;
534		-
535		- /* read all ALARM1, ALARM2, and status registers at once */
536		- ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS,
537		- regs, sizeof(regs));
538		- if (ret) {
539		- dev_err(dev, "%s error %d\n", "alarm read", ret);
540		- return ret;
541		- }
542		-
543		- dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read",
544		- &regs[0], &regs[4], &regs[7]);
545		-
546		- /*
547		- * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
548		- * and that all four fields are checked matches
549		- */
550		- t->time.tm_sec = bcd2bin(regs[0] & 0x7f);
551		- t->time.tm_min = bcd2bin(regs[1] & 0x7f);
552		- t->time.tm_hour = bcd2bin(regs[2] & 0x3f);
553		- t->time.tm_mday = bcd2bin(regs[3] & 0x3f);
554		-
555		- /* ... and status */
556		- t->enabled = !!(regs[7] & DS1337_BIT_A1IE);
557		- t->pending = !!(regs[8] & DS1337_BIT_A1I);
558		-
559		- dev_dbg(dev, "%s secs=%d, mins=%d, "
560		- "hours=%d, mday=%d, enabled=%d, pending=%d\n",
561		- "alarm read", t->time.tm_sec, t->time.tm_min,
562		- t->time.tm_hour, t->time.tm_mday,
563		- t->enabled, t->pending);
564		-
565		- return 0;
566		-}
567		-
568		-static int ds1337_set_alarm(struct device dev, struct rtc_wkalrm t)
569		-{
570		- struct ds1307 *ds1307 = dev_get_drvdata(dev);
571		- unsigned char regs[9];
572		- u8 control, status;
573		- int ret;
574		-
575		- if (!test_bit(HAS_ALARM, &ds1307->flags))
576		- return -EINVAL;
577		-
578		- dev_dbg(dev, "%s secs=%d, mins=%d, "
579		- "hours=%d, mday=%d, enabled=%d, pending=%d\n",
580		- "alarm set", t->time.tm_sec, t->time.tm_min,
581		- t->time.tm_hour, t->time.tm_mday,
582		- t->enabled, t->pending);
583		-
584		- /* read current status of both alarms and the chip */
585		- ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
586		- sizeof(regs));
587		- if (ret) {
588		- dev_err(dev, "%s error %d\n", "alarm write", ret);
589		- return ret;
590		- }
591		- control = regs[7];
592		- status = regs[8];
593		-
594		- dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)",
595		- &regs[0], &regs[4], control, status);
596		-
597		- /* set ALARM1, using 24 hour and day-of-month modes */
598		- regs[0] = bin2bcd(t->time.tm_sec);
599		- regs[1] = bin2bcd(t->time.tm_min);
600		- regs[2] = bin2bcd(t->time.tm_hour);
601		- regs[3] = bin2bcd(t->time.tm_mday);
602		-
603		- /* set ALARM2 to non-garbage */
604		- regs[4] = 0;
605		- regs[5] = 0;
606		- regs[6] = 0;
607		-
608		- /* disable alarms */
609		- regs[7] = control & ~(DS1337_BIT_A1IE \| DS1337_BIT_A2IE);
610		- regs[8] = status & ~(DS1337_BIT_A1I \| DS1337_BIT_A2I);
611		-
612		- ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
613		- sizeof(regs));
614		- if (ret) {
615		- dev_err(dev, "can't set alarm time\n");
616		- return ret;
617		- }
618		-
619		- /* optionally enable ALARM1 */
620		- if (t->enabled) {
621		- dev_dbg(dev, "alarm IRQ armed\n");
622		- regs[7] \|= DS1337_BIT_A1IE; /* only ALARM1 is used */
623		- regmap_write(ds1307->regmap, DS1337_REG_CONTROL, regs[7]);
624		- }
625		-
626		- return 0;
627		-}
628		-
629		-static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
630		-{
631		- struct ds1307 *ds1307 = dev_get_drvdata(dev);
632		-
633		- if (!test_bit(HAS_ALARM, &ds1307->flags))
634		- return -ENOTTY;
635		-
636		- return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
637		- DS1337_BIT_A1IE,
638		- enabled ? DS1337_BIT_A1IE : 0);
639		-}
640		-
641	1241	static const struct rtc_class_ops ds13xx_rtc_ops = {
642	1242	.read_time = ds1307_get_time,
643	1243	.set_time = ds1307_set_time,
..	..	@@ -646,338 +1246,67 @@
646	1246	.alarm_irq_enable = ds1307_alarm_irq_enable,
647	1247	};
648	1248
649		-/----------------------------------------------------------------------/
650		-
651		-/*
652		- * Alarm support for rx8130 devices.
653		- */
654		-
655		-#define RX8130_REG_ALARM_MIN 0x07
656		-#define RX8130_REG_ALARM_HOUR 0x08
657		-#define RX8130_REG_ALARM_WEEK_OR_DAY 0x09
658		-#define RX8130_REG_EXTENSION 0x0c
659		-#define RX8130_REG_EXTENSION_WADA BIT(3)
660		-#define RX8130_REG_FLAG 0x0d
661		-#define RX8130_REG_FLAG_AF BIT(3)
662		-#define RX8130_REG_CONTROL0 0x0e
663		-#define RX8130_REG_CONTROL0_AIE BIT(3)
664		-
665		-static irqreturn_t rx8130_irq(int irq, void *dev_id)
	1249	+static ssize_t frequency_test_store(struct device *dev,
	1250	+ struct device_attribute *attr,
	1251	+ const char *buf, size_t count)
666	1252	{
667		- struct ds1307 *ds1307 = dev_id;
668		- struct mutex *lock = &ds1307->rtc->ops_lock;
669		- u8 ctl[3];
	1253	+ struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
	1254	+ bool freq_test_en;
670	1255	int ret;
671	1256
672		- mutex_lock(lock);
	1257	+ ret = kstrtobool(buf, &freq_test_en);
	1258	+ if (ret) {
	1259	+ dev_err(dev, "Failed to store RTC Frequency Test attribute\n");
	1260	+ return ret;
	1261	+ }
673	1262
674		- /* Read control registers. */
675		- ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
676		- sizeof(ctl));
677		- if (ret < 0)
678		- goto out;
679		- if (!(ctl[1] & RX8130_REG_FLAG_AF))
680		- goto out;
681		- ctl[1] &= ~RX8130_REG_FLAG_AF;
682		- ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
	1263	+ regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL, M41TXX_BIT_FT,
	1264	+ freq_test_en ? M41TXX_BIT_FT : 0);
683	1265
684		- ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
685		- sizeof(ctl));
686		- if (ret < 0)
687		- goto out;
688		-
689		- rtc_update_irq(ds1307->rtc, 1, RTC_AF \| RTC_IRQF);
690		-
691		-out:
692		- mutex_unlock(lock);
693		-
694		- return IRQ_HANDLED;
	1266	+ return count;
695	1267	}
696	1268
697		-static int rx8130_read_alarm(struct device dev, struct rtc_wkalrm t)
	1269	+static ssize_t frequency_test_show(struct device *dev,
	1270	+ struct device_attribute *attr,
	1271	+ char *buf)
698	1272	{
699		- struct ds1307 *ds1307 = dev_get_drvdata(dev);
700		- u8 ald[3], ctl[3];
701		- int ret;
	1273	+ struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
	1274	+ unsigned int ctrl_reg;
702	1275
703		- if (!test_bit(HAS_ALARM, &ds1307->flags))
704		- return -EINVAL;
	1276	+ regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
705	1277
706		- /* Read alarm registers. */
707		- ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
708		- sizeof(ald));
709		- if (ret < 0)
710		- return ret;
	1278	+ return scnprintf(buf, PAGE_SIZE, (ctrl_reg & M41TXX_BIT_FT) ? "on\n" :
	1279	+ "off\n");
	1280	+}
711	1281
712		- /* Read control registers. */
713		- ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
714		- sizeof(ctl));
715		- if (ret < 0)
716		- return ret;
	1282	+static DEVICE_ATTR_RW(frequency_test);
717	1283
718		- t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE);
719		- t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF);
	1284	+static struct attribute *rtc_freq_test_attrs[] = {
	1285	+ &dev_attr_frequency_test.attr,
	1286	+ NULL,
	1287	+};
720	1288
721		- /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
722		- t->time.tm_sec = -1;
723		- t->time.tm_min = bcd2bin(ald[0] & 0x7f);
724		- t->time.tm_hour = bcd2bin(ald[1] & 0x7f);
725		- t->time.tm_wday = -1;
726		- t->time.tm_mday = bcd2bin(ald[2] & 0x7f);
727		- t->time.tm_mon = -1;
728		- t->time.tm_year = -1;
729		- t->time.tm_yday = -1;
730		- t->time.tm_isdst = -1;
	1289	+static const struct attribute_group rtc_freq_test_attr_group = {
	1290	+ .attrs = rtc_freq_test_attrs,
	1291	+};
731	1292
732		- dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n",
733		- __func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
734		- t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled);
	1293	+static int ds1307_add_frequency_test(struct ds1307 *ds1307)
	1294	+{
	1295	+ int err;
	1296	+
	1297	+ switch (ds1307->type) {
	1298	+ case m41t0:
	1299	+ case m41t00:
	1300	+ case m41t11:
	1301	+ err = rtc_add_group(ds1307->rtc, &rtc_freq_test_attr_group);
	1302	+ if (err)
	1303	+ return err;
	1304	+ break;
	1305	+ default:
	1306	+ break;
	1307	+ }
735	1308
736	1309	return 0;
737		-}
738		-
739		-static int rx8130_set_alarm(struct device dev, struct rtc_wkalrm t)
740		-{
741		- struct ds1307 *ds1307 = dev_get_drvdata(dev);
742		- u8 ald[3], ctl[3];
743		- int ret;
744		-
745		- if (!test_bit(HAS_ALARM, &ds1307->flags))
746		- return -EINVAL;
747		-
748		- dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
749		- "enabled=%d pending=%d\n", __func__,
750		- t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
751		- t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
752		- t->enabled, t->pending);
753		-
754		- /* Read control registers. */
755		- ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
756		- sizeof(ctl));
757		- if (ret < 0)
758		- return ret;
759		-
760		- ctl[0] &= RX8130_REG_EXTENSION_WADA;
761		- ctl[1] &= ~RX8130_REG_FLAG_AF;
762		- ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
763		-
764		- ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
765		- sizeof(ctl));
766		- if (ret < 0)
767		- return ret;
768		-
769		- /* Hardware alarm precision is 1 minute! */
770		- ald[0] = bin2bcd(t->time.tm_min);
771		- ald[1] = bin2bcd(t->time.tm_hour);
772		- ald[2] = bin2bcd(t->time.tm_mday);
773		-
774		- ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
775		- sizeof(ald));
776		- if (ret < 0)
777		- return ret;
778		-
779		- if (!t->enabled)
780		- return 0;
781		-
782		- ctl[2] \|= RX8130_REG_CONTROL0_AIE;
783		-
784		- return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, ctl[2]);
785		-}
786		-
787		-static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled)
788		-{
789		- struct ds1307 *ds1307 = dev_get_drvdata(dev);
790		- int ret, reg;
791		-
792		- if (!test_bit(HAS_ALARM, &ds1307->flags))
793		- return -EINVAL;
794		-
795		- ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, &reg);
796		- if (ret < 0)
797		- return ret;
798		-
799		- if (enabled)
800		- reg \|= RX8130_REG_CONTROL0_AIE;
801		- else
802		- reg &= ~RX8130_REG_CONTROL0_AIE;
803		-
804		- return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg);
805		-}
806		-
807		-/----------------------------------------------------------------------/
808		-
809		-/*
810		- * Alarm support for mcp794xx devices.
811		- */
812		-
813		-#define MCP794XX_REG_CONTROL 0x07
814		-# define MCP794XX_BIT_ALM0_EN 0x10
815		-# define MCP794XX_BIT_ALM1_EN 0x20
816		-#define MCP794XX_REG_ALARM0_BASE 0x0a
817		-#define MCP794XX_REG_ALARM0_CTRL 0x0d
818		-#define MCP794XX_REG_ALARM1_BASE 0x11
819		-#define MCP794XX_REG_ALARM1_CTRL 0x14
820		-# define MCP794XX_BIT_ALMX_IF BIT(3)
821		-# define MCP794XX_BIT_ALMX_C0 BIT(4)
822		-# define MCP794XX_BIT_ALMX_C1 BIT(5)
823		-# define MCP794XX_BIT_ALMX_C2 BIT(6)
824		-# define MCP794XX_BIT_ALMX_POL BIT(7)
825		-# define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 \| \
826		- MCP794XX_BIT_ALMX_C1 \| \
827		- MCP794XX_BIT_ALMX_C2)
828		-
829		-static irqreturn_t mcp794xx_irq(int irq, void *dev_id)
830		-{
831		- struct ds1307 *ds1307 = dev_id;
832		- struct mutex *lock = &ds1307->rtc->ops_lock;
833		- int reg, ret;
834		-
835		- mutex_lock(lock);
836		-
837		- /* Check and clear alarm 0 interrupt flag. */
838		- ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, &reg);
839		- if (ret)
840		- goto out;
841		- if (!(reg & MCP794XX_BIT_ALMX_IF))
842		- goto out;
843		- reg &= ~MCP794XX_BIT_ALMX_IF;
844		- ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg);
845		- if (ret)
846		- goto out;
847		-
848		- /* Disable alarm 0. */
849		- ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
850		- MCP794XX_BIT_ALM0_EN, 0);
851		- if (ret)
852		- goto out;
853		-
854		- rtc_update_irq(ds1307->rtc, 1, RTC_AF \| RTC_IRQF);
855		-
856		-out:
857		- mutex_unlock(lock);
858		-
859		- return IRQ_HANDLED;
860		-}
861		-
862		-static int mcp794xx_read_alarm(struct device dev, struct rtc_wkalrm t)
863		-{
864		- struct ds1307 *ds1307 = dev_get_drvdata(dev);
865		- u8 regs[10];
866		- int ret;
867		-
868		- if (!test_bit(HAS_ALARM, &ds1307->flags))
869		- return -EINVAL;
870		-
871		- /* Read control and alarm 0 registers. */
872		- ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
873		- sizeof(regs));
874		- if (ret)
875		- return ret;
876		-
877		- t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN);
878		-
879		- /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
880		- t->time.tm_sec = bcd2bin(regs[3] & 0x7f);
881		- t->time.tm_min = bcd2bin(regs[4] & 0x7f);
882		- t->time.tm_hour = bcd2bin(regs[5] & 0x3f);
883		- t->time.tm_wday = bcd2bin(regs[6] & 0x7) - 1;
884		- t->time.tm_mday = bcd2bin(regs[7] & 0x3f);
885		- t->time.tm_mon = bcd2bin(regs[8] & 0x1f) - 1;
886		- t->time.tm_year = -1;
887		- t->time.tm_yday = -1;
888		- t->time.tm_isdst = -1;
889		-
890		- dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
891		- "enabled=%d polarity=%d irq=%d match=%lu\n", __func__,
892		- t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
893		- t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
894		- !!(regs[6] & MCP794XX_BIT_ALMX_POL),
895		- !!(regs[6] & MCP794XX_BIT_ALMX_IF),
896		- (regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4);
897		-
898		- return 0;
899		-}
900		-
901		-/*
902		- * We may have a random RTC weekday, therefore calculate alarm weekday based
903		- * on current weekday we read from the RTC timekeeping regs
904		- */
905		-static int mcp794xx_alm_weekday(struct device dev, struct rtc_time tm_alarm)
906		-{
907		- struct rtc_time tm_now;
908		- int days_now, days_alarm, ret;
909		-
910		- ret = ds1307_get_time(dev, &tm_now);
911		- if (ret)
912		- return ret;
913		-
914		- days_now = div_s64(rtc_tm_to_time64(&tm_now), 24 * 60 * 60);
915		- days_alarm = div_s64(rtc_tm_to_time64(tm_alarm), 24 * 60 * 60);
916		-
917		- return (tm_now.tm_wday + days_alarm - days_now) % 7 + 1;
918		-}
919		-
920		-static int mcp794xx_set_alarm(struct device dev, struct rtc_wkalrm t)
921		-{
922		- struct ds1307 *ds1307 = dev_get_drvdata(dev);
923		- unsigned char regs[10];
924		- int wday, ret;
925		-
926		- if (!test_bit(HAS_ALARM, &ds1307->flags))
927		- return -EINVAL;
928		-
929		- wday = mcp794xx_alm_weekday(dev, &t->time);
930		- if (wday < 0)
931		- return wday;
932		-
933		- dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
934		- "enabled=%d pending=%d\n", __func__,
935		- t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
936		- t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
937		- t->enabled, t->pending);
938		-
939		- /* Read control and alarm 0 registers. */
940		- ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
941		- sizeof(regs));
942		- if (ret)
943		- return ret;
944		-
945		- /* Set alarm 0, using 24-hour and day-of-month modes. */
946		- regs[3] = bin2bcd(t->time.tm_sec);
947		- regs[4] = bin2bcd(t->time.tm_min);
948		- regs[5] = bin2bcd(t->time.tm_hour);
949		- regs[6] = wday;
950		- regs[7] = bin2bcd(t->time.tm_mday);
951		- regs[8] = bin2bcd(t->time.tm_mon + 1);
952		-
953		- /* Clear the alarm 0 interrupt flag. */
954		- regs[6] &= ~MCP794XX_BIT_ALMX_IF;
955		- /* Set alarm match: second, minute, hour, day, date, month. */
956		- regs[6] \|= MCP794XX_MSK_ALMX_MATCH;
957		- /* Disable interrupt. We will not enable until completely programmed */
958		- regs[0] &= ~MCP794XX_BIT_ALM0_EN;
959		-
960		- ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
961		- sizeof(regs));
962		- if (ret)
963		- return ret;
964		-
965		- if (!t->enabled)
966		- return 0;
967		- regs[0] \|= MCP794XX_BIT_ALM0_EN;
968		- return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]);
969		-}
970		-
971		-static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)
972		-{
973		- struct ds1307 *ds1307 = dev_get_drvdata(dev);
974		-
975		- if (!test_bit(HAS_ALARM, &ds1307->flags))
976		- return -EINVAL;
977		-
978		- return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
979		- MCP794XX_BIT_ALM0_EN,
980		- enabled ? MCP794XX_BIT_ALM0_EN : 0);
981	1310	}
982	1311
983	1312	/----------------------------------------------------------------------/
..	..	@@ -1004,45 +1333,40 @@
1004	1333
1005	1334	/----------------------------------------------------------------------/
1006	1335
1007		-static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307,
1008		- u32 ohms, bool diode)
1009		-{
1010		- u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
1011		- DS1307_TRICKLE_CHARGER_NO_DIODE;
1012		-
1013		- switch (ohms) {
1014		- case 250:
1015		- setup \|= DS1307_TRICKLE_CHARGER_250_OHM;
1016		- break;
1017		- case 2000:
1018		- setup \|= DS1307_TRICKLE_CHARGER_2K_OHM;
1019		- break;
1020		- case 4000:
1021		- setup \|= DS1307_TRICKLE_CHARGER_4K_OHM;
1022		- break;
1023		- default:
1024		- dev_warn(ds1307->dev,
1025		- "Unsupported ohm value %u in dt\n", ohms);
1026		- return 0;
1027		- }
1028		- return setup;
1029		-}
1030		-
1031	1336	static u8 ds1307_trickle_init(struct ds1307 *ds1307,
1032	1337	const struct chip_desc *chip)
1033	1338	{
1034		- u32 ohms;
1035		- bool diode = true;
	1339	+ u32 ohms, chargeable;
	1340	+ bool diode = chip->charge_default;
1036	1341
1037	1342	if (!chip->do_trickle_setup)
1038	1343	return 0;
1039	1344
1040	1345	if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms",
1041		- &ohms))
	1346	+ &ohms) && chip->requires_trickle_resistor)
1042	1347	return 0;
1043	1348
1044		- if (device_property_read_bool(ds1307->dev, "trickle-diode-disable"))
	1349	+ /* aux-voltage-chargeable takes precedence over the deprecated
	1350	+ * trickle-diode-disable
	1351	+ */
	1352	+ if (!device_property_read_u32(ds1307->dev, "aux-voltage-chargeable",
	1353	+ &chargeable)) {
	1354	+ switch (chargeable) {
	1355	+ case 0:
	1356	+ diode = false;
	1357	+ break;
	1358	+ case 1:
	1359	+ diode = true;
	1360	+ break;
	1361	+ default:
	1362	+ dev_warn(ds1307->dev,
	1363	+ "unsupported aux-voltage-chargeable value\n");
	1364	+ break;
	1365	+ }
	1366	+ } else if (device_property_read_bool(ds1307->dev,
	1367	+ "trickle-diode-disable")) {
1045	1368	diode = false;
	1369	+ }
1046	1370
1047	1371	return chip->do_trickle_setup(ds1307, ohms, diode);
1048	1372	}
..	..	@@ -1388,6 +1712,54 @@
1388	1712
1389	1713	#endif /* CONFIG_COMMON_CLK */
1390	1714
	1715	+#ifdef CONFIG_WATCHDOG_CORE
	1716	+static const struct watchdog_info ds1388_wdt_info = {
	1717	+ .options = WDIOF_SETTIMEOUT \| WDIOF_KEEPALIVEPING \| WDIOF_MAGICCLOSE,
	1718	+ .identity = "DS1388 watchdog",
	1719	+};
	1720	+
	1721	+static const struct watchdog_ops ds1388_wdt_ops = {
	1722	+ .owner = THIS_MODULE,
	1723	+ .start = ds1388_wdt_start,
	1724	+ .stop = ds1388_wdt_stop,
	1725	+ .ping = ds1388_wdt_ping,
	1726	+ .set_timeout = ds1388_wdt_set_timeout,
	1727	+
	1728	+};
	1729	+
	1730	+static void ds1307_wdt_register(struct ds1307 *ds1307)
	1731	+{
	1732	+ struct watchdog_device *wdt;
	1733	+ int err;
	1734	+ int val;
	1735	+
	1736	+ if (ds1307->type != ds_1388)
	1737	+ return;
	1738	+
	1739	+ wdt = devm_kzalloc(ds1307->dev, sizeof(*wdt), GFP_KERNEL);
	1740	+ if (!wdt)
	1741	+ return;
	1742	+
	1743	+ err = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &val);
	1744	+ if (!err && val & DS1388_BIT_WF)
	1745	+ wdt->bootstatus = WDIOF_CARDRESET;
	1746	+
	1747	+ wdt->info = &ds1388_wdt_info;
	1748	+ wdt->ops = &ds1388_wdt_ops;
	1749	+ wdt->timeout = 99;
	1750	+ wdt->max_timeout = 99;
	1751	+ wdt->min_timeout = 1;
	1752	+
	1753	+ watchdog_init_timeout(wdt, 0, ds1307->dev);
	1754	+ watchdog_set_drvdata(wdt, ds1307);
	1755	+ devm_watchdog_register_device(ds1307->dev, wdt);
	1756	+}
	1757	+#else
	1758	+static void ds1307_wdt_register(struct ds1307 *ds1307)
	1759	+{
	1760	+}
	1761	+#endif /* CONFIG_WATCHDOG_CORE */
	1762	+
1391	1763	static const struct regmap_config regmap_config = {
1392	1764	.reg_bits = 8,
1393	1765	.val_bits = 8,
..	..	@@ -1448,7 +1820,6 @@
1448	1820	trickle_charger_setup = pdata->trickle_charger_setup;
1449	1821
1450	1822	if (trickle_charger_setup && chip->trickle_charger_reg) {
1451		- trickle_charger_setup \|= DS13XX_TRICKLE_CHARGER_MAGIC;
1452	1823	dev_dbg(ds1307->dev,
1453	1824	"writing trickle charger info 0x%x to 0x%x\n",
1454	1825	trickle_charger_setup, chip->trickle_charger_reg);
..	..	@@ -1571,11 +1942,23 @@
1571	1942	DS1307_REG_HOUR << 4 \| 0x08, hour);
1572	1943	}
1573	1944	break;
	1945	+ case ds_1388:
	1946	+ err = regmap_read(ds1307->regmap, DS1388_REG_CONTROL, &tmp);
	1947	+ if (err) {
	1948	+ dev_dbg(ds1307->dev, "read error %d\n", err);
	1949	+ goto exit;
	1950	+ }
	1951	+
	1952	+ /* oscillator off? turn it on, so clock can tick. */
	1953	+ if (tmp & DS1388_BIT_nEOSC) {
	1954	+ tmp &= ~DS1388_BIT_nEOSC;
	1955	+ regmap_write(ds1307->regmap, DS1388_REG_CONTROL, tmp);
	1956	+ }
	1957	+ break;
1574	1958	default:
1575	1959	break;
1576	1960	}
1577	1961
1578		-read_rtc:
1579	1962	/* read RTC registers */
1580	1963	err = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
1581	1964	sizeof(regs));
..	..	@@ -1584,75 +1967,11 @@
1584	1967	goto exit;
1585	1968	}
1586	1969
1587		- /*
1588		- * minimal sanity checking; some chips (like DS1340) don't
1589		- * specify the extra bits as must-be-zero, but there are
1590		- * still a few values that are clearly out-of-range.
1591		- */
1592		- tmp = regs[DS1307_REG_SECS];
1593		- switch (ds1307->type) {
1594		- case ds_1307:
1595		- case m41t0:
1596		- case m41t00:
1597		- case m41t11:
1598		- /* clock halted? turn it on, so clock can tick. */
1599		- if (tmp & DS1307_BIT_CH) {
1600		- regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
1601		- dev_warn(ds1307->dev, "SET TIME!\n");
1602		- goto read_rtc;
1603		- }
1604		- break;
1605		- case ds_1308:
1606		- case ds_1338:
1607		- /* clock halted? turn it on, so clock can tick. */
1608		- if (tmp & DS1307_BIT_CH)
1609		- regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
1610		-
1611		- /* oscillator fault? clear flag, and warn */
1612		- if (regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) {
1613		- regmap_write(ds1307->regmap, DS1307_REG_CONTROL,
1614		- regs[DS1307_REG_CONTROL] &
1615		- ~DS1338_BIT_OSF);
1616		- dev_warn(ds1307->dev, "SET TIME!\n");
1617		- goto read_rtc;
1618		- }
1619		- break;
1620		- case ds_1340:
1621		- /* clock halted? turn it on, so clock can tick. */
1622		- if (tmp & DS1340_BIT_nEOSC)
1623		- regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
1624		-
1625		- err = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp);
1626		- if (err) {
1627		- dev_dbg(ds1307->dev, "read error %d\n", err);
1628		- goto exit;
1629		- }
1630		-
1631		- /* oscillator fault? clear flag, and warn */
1632		- if (tmp & DS1340_BIT_OSF) {
1633		- regmap_write(ds1307->regmap, DS1340_REG_FLAG, 0);
1634		- dev_warn(ds1307->dev, "SET TIME!\n");
1635		- }
1636		- break;
1637		- case mcp794xx:
1638		- /* make sure that the backup battery is enabled */
1639		- if (!(regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) {
1640		- regmap_write(ds1307->regmap, DS1307_REG_WDAY,
1641		- regs[DS1307_REG_WDAY] \|
1642		- MCP794XX_BIT_VBATEN);
1643		- }
1644		-
1645		- /* clock halted? turn it on, so clock can tick. */
1646		- if (!(tmp & MCP794XX_BIT_ST)) {
1647		- regmap_write(ds1307->regmap, DS1307_REG_SECS,
1648		- MCP794XX_BIT_ST);
1649		- dev_warn(ds1307->dev, "SET TIME!\n");
1650		- goto read_rtc;
1651		- }
1652		-
1653		- break;
1654		- default:
1655		- break;
	1970	+ if (ds1307->type == mcp794xx &&
	1971	+ !(regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) {
	1972	+ regmap_write(ds1307->regmap, DS1307_REG_WDAY,
	1973	+ regs[DS1307_REG_WDAY] \|
	1974	+ MCP794XX_BIT_VBATEN);
1656	1975	}
1657	1976
1658	1977	tmp = regs[DS1307_REG_HOUR];
..	..	@@ -1717,6 +2036,10 @@
1717	2036	}
1718	2037
1719	2038	ds1307->rtc->ops = chip->rtc_ops ?: &ds13xx_rtc_ops;
	2039	+ err = ds1307_add_frequency_test(ds1307);
	2040	+ if (err)
	2041	+ return err;
	2042	+
1720	2043	err = rtc_register_device(ds1307->rtc);
1721	2044	if (err)
1722	2045	return err;
..	..	@@ -1738,6 +2061,7 @@
1738	2061
1739	2062	ds1307_hwmon_register(ds1307);
1740	2063	ds1307_clks_register(ds1307);
	2064	+ ds1307_wdt_register(ds1307);
1741	2065
1742	2066	return 0;
1743	2067