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2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390 
 kernel/drivers/pinctrl/pinctrl-oxnas.c
....@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Oxford Semiconductor OXNAS SoC Family pinctrl driver
34  *
....@@ -6,15 +7,6 @@
67  * Based on pinctrl-pic32.c
78  * Joshua Henderson, <joshua.henderson@microchip.com>
89  * Copyright (C) 2015 Microchip Technology Inc.  All rights reserved.
9
- *
10
- * This program is free software; you can distribute it and/or modify it
11
- * under the terms of the GNU General Public License (Version 2) as
12
- * published by the Free Software Foundation.
13
- *
14
- * This program is distributed in the hope it will be useful, but WITHOUT
15
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
17
- * for more details.
1810  */
1911 #include <linux/gpio/driver.h>
2012 #include <linux/interrupt.h>
....@@ -764,7 +756,10 @@
764756 	struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
765757 	u32 mask = BIT(offset);
766758 
767
-	return !(readl_relaxed(bank->reg_base + OUTPUT_EN) & mask);
759
+	if (readl_relaxed(bank->reg_base + OUTPUT_EN) & mask)
760
+		return GPIO_LINE_DIRECTION_OUT;
761
+
762
+	return GPIO_LINE_DIRECTION_IN;
768763 }
769764 
770765 static int oxnas_gpio_direction_input(struct gpio_chip *chip,
....@@ -910,7 +905,6 @@
910905 	struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
911906 	struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);
912907 	unsigned int param;
913
-	u32 arg;
914908 	unsigned int i;
915909 	u32 offset = pin - bank->gpio_chip.base;
916910 	u32 mask = BIT(offset);
....@@ -920,7 +914,6 @@
920914 
921915 	for (i = 0; i < num_configs; i++) {
922916 		param = pinconf_to_config_param(configs[i]);
923
-		arg = pinconf_to_config_argument(configs[i]);
924917 
925918 		switch (param) {
926919 		case PIN_CONFIG_BIAS_PULL_UP:
....@@ -949,7 +942,6 @@
949942 	struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);
950943 	unsigned int bank_offset = (bank->id ? PINMUX_820_BANK_OFFSET : 0);
951944 	unsigned int param;
952
-	u32 arg;
953945 	unsigned int i;
954946 	u32 offset = pin - bank->gpio_chip.base;
955947 	u32 mask = BIT(offset);
....@@ -959,7 +951,6 @@
959951 
960952 	for (i = 0; i < num_configs; i++) {
961953 		param = pinconf_to_config_param(configs[i]);
962
-		arg = pinconf_to_config_argument(configs[i]);
963954 
964955 		switch (param) {
965956 		case PIN_CONFIG_BIAS_PULL_UP:
....@@ -1208,7 +1199,7 @@
12081199 	struct oxnas_gpio_bank *bank;
12091200 	unsigned int id, ngpios;
12101201 	int irq, ret;
1211
-	struct resource *res;
1202
+	struct gpio_irq_chip *girq;
12121203 
12131204 	if (of_parse_phandle_with_fixed_args(np, "gpio-ranges",
12141205 					     3, 0, &pinspec)) {
....@@ -1231,39 +1222,36 @@
12311222 
12321223 	bank = &oxnas_gpio_banks[id];
12331224 
1234
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1235
-	bank->reg_base = devm_ioremap_resource(&pdev->dev, res);
1225
+	bank->reg_base = devm_platform_ioremap_resource(pdev, 0);
12361226 	if (IS_ERR(bank->reg_base))
12371227 		return PTR_ERR(bank->reg_base);
12381228 
12391229 	irq = platform_get_irq(pdev, 0);
1240
-	if (irq < 0) {
1241
-		dev_err(&pdev->dev, "irq get failed\n");
1230
+	if (irq < 0)
12421231 		return irq;
1243
-	}
12441232 
12451233 	bank->id = id;
12461234 	bank->gpio_chip.parent = &pdev->dev;
12471235 	bank->gpio_chip.of_node = np;
12481236 	bank->gpio_chip.ngpio = ngpios;
1237
+	girq = &bank->gpio_chip.irq;
1238
+	girq->chip = &bank->irq_chip;
1239
+	girq->parent_handler = oxnas_gpio_irq_handler;
1240
+	girq->num_parents = 1;
1241
+	girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents),
1242
+				     GFP_KERNEL);
1243
+	if (!girq->parents)
1244
+		return -ENOMEM;
1245
+	girq->parents[0] = irq;
1246
+	girq->default_type = IRQ_TYPE_NONE;
1247
+	girq->handler = handle_level_irq;
1248
+
12491249 	ret = gpiochip_add_data(&bank->gpio_chip, bank);
12501250 	if (ret < 0) {
12511251 		dev_err(&pdev->dev, "Failed to add GPIO chip %u: %d\n",
12521252 			id, ret);
12531253 		return ret;
12541254 	}
1255
-
1256
-	ret = gpiochip_irqchip_add(&bank->gpio_chip, &bank->irq_chip,
1257
-				0, handle_level_irq, IRQ_TYPE_NONE);
1258
-	if (ret < 0) {
1259
-		dev_err(&pdev->dev, "Failed to add IRQ chip %u: %d\n",
1260
-			id, ret);
1261
-		gpiochip_remove(&bank->gpio_chip);
1262
-		return ret;
1263
-	}
1264
-
1265
-	gpiochip_set_chained_irqchip(&bank->gpio_chip, &bank->irq_chip,
1266
-				     irq, oxnas_gpio_irq_handler);
12671255 
12681256 	return 0;
12691257 }