hc
2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390
kernel/drivers/pinctrl/intel/pinctrl-cannonlake.c
....@@ -7,10 +7,10 @@
77 * Mika Westerberg <mika.westerberg@linux.intel.com>
88 */
99
10
-#include <linux/acpi.h>
10
+#include <linux/mod_devicetable.h>
1111 #include <linux/module.h>
1212 #include <linux/platform_device.h>
13
-#include <linux/pm.h>
13
+
1414 #include <linux/pinctrl/pinctrl.h>
1515
1616 #include "pinctrl-intel.h"
....@@ -19,6 +19,7 @@
1919 #define CNL_PADCFGLOCK 0x080
2020 #define CNL_LP_HOSTSW_OWN 0x0b0
2121 #define CNL_H_HOSTSW_OWN 0x0c0
22
+#define CNL_GPI_IS 0x100
2223 #define CNL_GPI_IE 0x120
2324
2425 #define CNL_GPP(r, s, e, g) \
....@@ -29,14 +30,13 @@
2930 .gpio_base = (g), \
3031 }
3132
32
-#define CNL_NO_GPIO -1
33
-
34
-#define CNL_COMMUNITY(b, s, e, o, g) \
33
+#define CNL_COMMUNITY(b, s, e, ho, g) \
3534 { \
3635 .barno = (b), \
3736 .padown_offset = CNL_PAD_OWN, \
3837 .padcfglock_offset = CNL_PADCFGLOCK, \
39
- .hostown_offset = (o), \
38
+ .hostown_offset = (ho), \
39
+ .is_offset = CNL_GPI_IS, \
4040 .ie_offset = CNL_GPI_IE, \
4141 .pin_base = (s), \
4242 .npins = ((e) - (s) + 1), \
....@@ -44,10 +44,10 @@
4444 .ngpps = ARRAY_SIZE(g), \
4545 }
4646
47
-#define CNLLP_COMMUNITY(b, s, e, g) \
47
+#define CNL_LP_COMMUNITY(b, s, e, g) \
4848 CNL_COMMUNITY(b, s, e, CNL_LP_HOSTSW_OWN, g)
4949
50
-#define CNLH_COMMUNITY(b, s, e, g) \
50
+#define CNL_H_COMMUNITY(b, s, e, g) \
5151 CNL_COMMUNITY(b, s, e, CNL_H_HOSTSW_OWN, g)
5252
5353 /* Cannon Lake-H */
....@@ -375,27 +375,27 @@
375375 };
376376
377377 static const struct intel_padgroup cnlh_community1_gpps[] = {
378
- CNL_GPP(0, 51, 74, 64), /* GPP_C */
379
- CNL_GPP(1, 75, 98, 96), /* GPP_D */
380
- CNL_GPP(2, 99, 106, 128), /* GPP_G */
381
- CNL_GPP(3, 107, 114, CNL_NO_GPIO), /* AZA */
382
- CNL_GPP(4, 115, 146, 160), /* vGPIO_0 */
383
- CNL_GPP(5, 147, 154, CNL_NO_GPIO), /* vGPIO_1 */
378
+ CNL_GPP(0, 51, 74, 64), /* GPP_C */
379
+ CNL_GPP(1, 75, 98, 96), /* GPP_D */
380
+ CNL_GPP(2, 99, 106, 128), /* GPP_G */
381
+ CNL_GPP(3, 107, 114, INTEL_GPIO_BASE_NOMAP), /* AZA */
382
+ CNL_GPP(4, 115, 146, 160), /* vGPIO_0 */
383
+ CNL_GPP(5, 147, 154, INTEL_GPIO_BASE_NOMAP), /* vGPIO_1 */
384384 };
385385
386386 static const struct intel_padgroup cnlh_community3_gpps[] = {
387
- CNL_GPP(0, 155, 178, 192), /* GPP_K */
388
- CNL_GPP(1, 179, 202, 224), /* GPP_H */
389
- CNL_GPP(2, 203, 215, 256), /* GPP_E */
390
- CNL_GPP(3, 216, 239, 288), /* GPP_F */
391
- CNL_GPP(4, 240, 248, CNL_NO_GPIO), /* SPI */
387
+ CNL_GPP(0, 155, 178, 192), /* GPP_K */
388
+ CNL_GPP(1, 179, 202, 224), /* GPP_H */
389
+ CNL_GPP(2, 203, 215, 256), /* GPP_E */
390
+ CNL_GPP(3, 216, 239, 288), /* GPP_F */
391
+ CNL_GPP(4, 240, 248, INTEL_GPIO_BASE_NOMAP), /* SPI */
392392 };
393393
394394 static const struct intel_padgroup cnlh_community4_gpps[] = {
395
- CNL_GPP(0, 249, 259, CNL_NO_GPIO), /* CPU */
396
- CNL_GPP(1, 260, 268, CNL_NO_GPIO), /* JTAG */
397
- CNL_GPP(2, 269, 286, 320), /* GPP_I */
398
- CNL_GPP(3, 287, 298, 352), /* GPP_J */
395
+ CNL_GPP(0, 249, 259, INTEL_GPIO_BASE_NOMAP), /* CPU */
396
+ CNL_GPP(1, 260, 268, INTEL_GPIO_BASE_NOMAP), /* JTAG */
397
+ CNL_GPP(2, 269, 286, 320), /* GPP_I */
398
+ CNL_GPP(3, 287, 298, 352), /* GPP_J */
399399 };
400400
401401 static const unsigned int cnlh_spi0_pins[] = { 40, 41, 42, 43 };
....@@ -449,10 +449,10 @@
449449 };
450450
451451 static const struct intel_community cnlh_communities[] = {
452
- CNLH_COMMUNITY(0, 0, 50, cnlh_community0_gpps),
453
- CNLH_COMMUNITY(1, 51, 154, cnlh_community1_gpps),
454
- CNLH_COMMUNITY(2, 155, 248, cnlh_community3_gpps),
455
- CNLH_COMMUNITY(3, 249, 298, cnlh_community4_gpps),
452
+ CNL_H_COMMUNITY(0, 0, 50, cnlh_community0_gpps),
453
+ CNL_H_COMMUNITY(1, 51, 154, cnlh_community1_gpps),
454
+ CNL_H_COMMUNITY(2, 155, 248, cnlh_community3_gpps),
455
+ CNL_H_COMMUNITY(3, 249, 298, cnlh_community4_gpps),
456456 };
457457
458458 static const struct intel_pinctrl_soc_data cnlh_soc_data = {
....@@ -788,31 +788,31 @@
788788 };
789789
790790 static const struct intel_padgroup cnllp_community0_gpps[] = {
791
- CNL_GPP(0, 0, 24, 0), /* GPP_A */
792
- CNL_GPP(1, 25, 50, 32), /* GPP_B */
793
- CNL_GPP(2, 51, 58, 64), /* GPP_G */
794
- CNL_GPP(3, 59, 67, CNL_NO_GPIO), /* SPI */
791
+ CNL_GPP(0, 0, 24, 0), /* GPP_A */
792
+ CNL_GPP(1, 25, 50, 32), /* GPP_B */
793
+ CNL_GPP(2, 51, 58, 64), /* GPP_G */
794
+ CNL_GPP(3, 59, 67, INTEL_GPIO_BASE_NOMAP), /* SPI */
795795 };
796796
797797 static const struct intel_padgroup cnllp_community1_gpps[] = {
798
- CNL_GPP(0, 68, 92, 96), /* GPP_D */
799
- CNL_GPP(1, 93, 116, 128), /* GPP_F */
800
- CNL_GPP(2, 117, 140, 160), /* GPP_H */
801
- CNL_GPP(3, 141, 172, 192), /* vGPIO */
802
- CNL_GPP(4, 173, 180, 224), /* vGPIO */
798
+ CNL_GPP(0, 68, 92, 96), /* GPP_D */
799
+ CNL_GPP(1, 93, 116, 128), /* GPP_F */
800
+ CNL_GPP(2, 117, 140, 160), /* GPP_H */
801
+ CNL_GPP(3, 141, 172, 192), /* vGPIO */
802
+ CNL_GPP(4, 173, 180, 224), /* vGPIO */
803803 };
804804
805805 static const struct intel_padgroup cnllp_community4_gpps[] = {
806
- CNL_GPP(0, 181, 204, 256), /* GPP_C */
807
- CNL_GPP(1, 205, 228, 288), /* GPP_E */
808
- CNL_GPP(2, 229, 237, CNL_NO_GPIO), /* JTAG */
809
- CNL_GPP(3, 238, 243, CNL_NO_GPIO), /* HVCMOS */
806
+ CNL_GPP(0, 181, 204, 256), /* GPP_C */
807
+ CNL_GPP(1, 205, 228, 288), /* GPP_E */
808
+ CNL_GPP(2, 229, 237, INTEL_GPIO_BASE_NOMAP), /* JTAG */
809
+ CNL_GPP(3, 238, 243, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
810810 };
811811
812812 static const struct intel_community cnllp_communities[] = {
813
- CNLLP_COMMUNITY(0, 0, 67, cnllp_community0_gpps),
814
- CNLLP_COMMUNITY(1, 68, 180, cnllp_community1_gpps),
815
- CNLLP_COMMUNITY(2, 181, 243, cnllp_community4_gpps),
813
+ CNL_LP_COMMUNITY(0, 0, 67, cnllp_community0_gpps),
814
+ CNL_LP_COMMUNITY(1, 68, 180, cnllp_community1_gpps),
815
+ CNL_LP_COMMUNITY(2, 181, 243, cnllp_community4_gpps),
816816 };
817817
818818 static const struct intel_pinctrl_soc_data cnllp_soc_data = {
....@@ -829,30 +829,14 @@
829829 static const struct acpi_device_id cnl_pinctrl_acpi_match[] = {
830830 { "INT3450", (kernel_ulong_t)&cnlh_soc_data },
831831 { "INT34BB", (kernel_ulong_t)&cnllp_soc_data },
832
- { },
832
+ { }
833833 };
834834 MODULE_DEVICE_TABLE(acpi, cnl_pinctrl_acpi_match);
835835
836
-static int cnl_pinctrl_probe(struct platform_device *pdev)
837
-{
838
- const struct intel_pinctrl_soc_data *soc_data;
839
- const struct acpi_device_id *id;
840
-
841
- id = acpi_match_device(cnl_pinctrl_acpi_match, &pdev->dev);
842
- if (!id || !id->driver_data)
843
- return -ENODEV;
844
-
845
- soc_data = (const struct intel_pinctrl_soc_data *)id->driver_data;
846
- return intel_pinctrl_probe(pdev, soc_data);
847
-}
848
-
849
-static const struct dev_pm_ops cnl_pinctrl_pm_ops = {
850
- SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend,
851
- intel_pinctrl_resume)
852
-};
836
+static INTEL_PINCTRL_PM_OPS(cnl_pinctrl_pm_ops);
853837
854838 static struct platform_driver cnl_pinctrl_driver = {
855
- .probe = cnl_pinctrl_probe,
839
+ .probe = intel_pinctrl_probe_by_hid,
856840 .driver = {
857841 .name = "cannonlake-pinctrl",
858842 .acpi_match_table = cnl_pinctrl_acpi_match,