.. | .. |
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7 | 7 | * Mika Westerberg <mika.westerberg@linux.intel.com> |
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8 | 8 | */ |
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9 | 9 | |
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10 | | -#include <linux/acpi.h> |
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| 10 | +#include <linux/mod_devicetable.h> |
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11 | 11 | #include <linux/module.h> |
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12 | 12 | #include <linux/platform_device.h> |
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13 | | -#include <linux/pm.h> |
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| 13 | + |
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14 | 14 | #include <linux/pinctrl/pinctrl.h> |
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15 | 15 | |
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16 | 16 | #include "pinctrl-intel.h" |
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.. | .. |
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19 | 19 | #define CNL_PADCFGLOCK 0x080 |
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20 | 20 | #define CNL_LP_HOSTSW_OWN 0x0b0 |
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21 | 21 | #define CNL_H_HOSTSW_OWN 0x0c0 |
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| 22 | +#define CNL_GPI_IS 0x100 |
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22 | 23 | #define CNL_GPI_IE 0x120 |
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23 | 24 | |
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24 | 25 | #define CNL_GPP(r, s, e, g) \ |
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.. | .. |
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29 | 30 | .gpio_base = (g), \ |
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30 | 31 | } |
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31 | 32 | |
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32 | | -#define CNL_NO_GPIO -1 |
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33 | | - |
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34 | | -#define CNL_COMMUNITY(b, s, e, o, g) \ |
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| 33 | +#define CNL_COMMUNITY(b, s, e, ho, g) \ |
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35 | 34 | { \ |
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36 | 35 | .barno = (b), \ |
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37 | 36 | .padown_offset = CNL_PAD_OWN, \ |
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38 | 37 | .padcfglock_offset = CNL_PADCFGLOCK, \ |
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39 | | - .hostown_offset = (o), \ |
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| 38 | + .hostown_offset = (ho), \ |
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| 39 | + .is_offset = CNL_GPI_IS, \ |
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40 | 40 | .ie_offset = CNL_GPI_IE, \ |
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41 | 41 | .pin_base = (s), \ |
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42 | 42 | .npins = ((e) - (s) + 1), \ |
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.. | .. |
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44 | 44 | .ngpps = ARRAY_SIZE(g), \ |
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45 | 45 | } |
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46 | 46 | |
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47 | | -#define CNLLP_COMMUNITY(b, s, e, g) \ |
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| 47 | +#define CNL_LP_COMMUNITY(b, s, e, g) \ |
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48 | 48 | CNL_COMMUNITY(b, s, e, CNL_LP_HOSTSW_OWN, g) |
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49 | 49 | |
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50 | | -#define CNLH_COMMUNITY(b, s, e, g) \ |
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| 50 | +#define CNL_H_COMMUNITY(b, s, e, g) \ |
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51 | 51 | CNL_COMMUNITY(b, s, e, CNL_H_HOSTSW_OWN, g) |
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52 | 52 | |
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53 | 53 | /* Cannon Lake-H */ |
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.. | .. |
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375 | 375 | }; |
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376 | 376 | |
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377 | 377 | static const struct intel_padgroup cnlh_community1_gpps[] = { |
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378 | | - CNL_GPP(0, 51, 74, 64), /* GPP_C */ |
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379 | | - CNL_GPP(1, 75, 98, 96), /* GPP_D */ |
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380 | | - CNL_GPP(2, 99, 106, 128), /* GPP_G */ |
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381 | | - CNL_GPP(3, 107, 114, CNL_NO_GPIO), /* AZA */ |
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382 | | - CNL_GPP(4, 115, 146, 160), /* vGPIO_0 */ |
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383 | | - CNL_GPP(5, 147, 154, CNL_NO_GPIO), /* vGPIO_1 */ |
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| 378 | + CNL_GPP(0, 51, 74, 64), /* GPP_C */ |
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| 379 | + CNL_GPP(1, 75, 98, 96), /* GPP_D */ |
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| 380 | + CNL_GPP(2, 99, 106, 128), /* GPP_G */ |
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| 381 | + CNL_GPP(3, 107, 114, INTEL_GPIO_BASE_NOMAP), /* AZA */ |
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| 382 | + CNL_GPP(4, 115, 146, 160), /* vGPIO_0 */ |
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| 383 | + CNL_GPP(5, 147, 154, INTEL_GPIO_BASE_NOMAP), /* vGPIO_1 */ |
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384 | 384 | }; |
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385 | 385 | |
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386 | 386 | static const struct intel_padgroup cnlh_community3_gpps[] = { |
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387 | | - CNL_GPP(0, 155, 178, 192), /* GPP_K */ |
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388 | | - CNL_GPP(1, 179, 202, 224), /* GPP_H */ |
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389 | | - CNL_GPP(2, 203, 215, 256), /* GPP_E */ |
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390 | | - CNL_GPP(3, 216, 239, 288), /* GPP_F */ |
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391 | | - CNL_GPP(4, 240, 248, CNL_NO_GPIO), /* SPI */ |
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| 387 | + CNL_GPP(0, 155, 178, 192), /* GPP_K */ |
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| 388 | + CNL_GPP(1, 179, 202, 224), /* GPP_H */ |
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| 389 | + CNL_GPP(2, 203, 215, 256), /* GPP_E */ |
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| 390 | + CNL_GPP(3, 216, 239, 288), /* GPP_F */ |
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| 391 | + CNL_GPP(4, 240, 248, INTEL_GPIO_BASE_NOMAP), /* SPI */ |
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392 | 392 | }; |
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393 | 393 | |
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394 | 394 | static const struct intel_padgroup cnlh_community4_gpps[] = { |
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395 | | - CNL_GPP(0, 249, 259, CNL_NO_GPIO), /* CPU */ |
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396 | | - CNL_GPP(1, 260, 268, CNL_NO_GPIO), /* JTAG */ |
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397 | | - CNL_GPP(2, 269, 286, 320), /* GPP_I */ |
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398 | | - CNL_GPP(3, 287, 298, 352), /* GPP_J */ |
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| 395 | + CNL_GPP(0, 249, 259, INTEL_GPIO_BASE_NOMAP), /* CPU */ |
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| 396 | + CNL_GPP(1, 260, 268, INTEL_GPIO_BASE_NOMAP), /* JTAG */ |
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| 397 | + CNL_GPP(2, 269, 286, 320), /* GPP_I */ |
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| 398 | + CNL_GPP(3, 287, 298, 352), /* GPP_J */ |
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399 | 399 | }; |
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400 | 400 | |
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401 | 401 | static const unsigned int cnlh_spi0_pins[] = { 40, 41, 42, 43 }; |
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.. | .. |
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449 | 449 | }; |
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450 | 450 | |
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451 | 451 | static const struct intel_community cnlh_communities[] = { |
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452 | | - CNLH_COMMUNITY(0, 0, 50, cnlh_community0_gpps), |
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453 | | - CNLH_COMMUNITY(1, 51, 154, cnlh_community1_gpps), |
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454 | | - CNLH_COMMUNITY(2, 155, 248, cnlh_community3_gpps), |
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455 | | - CNLH_COMMUNITY(3, 249, 298, cnlh_community4_gpps), |
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| 452 | + CNL_H_COMMUNITY(0, 0, 50, cnlh_community0_gpps), |
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| 453 | + CNL_H_COMMUNITY(1, 51, 154, cnlh_community1_gpps), |
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| 454 | + CNL_H_COMMUNITY(2, 155, 248, cnlh_community3_gpps), |
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| 455 | + CNL_H_COMMUNITY(3, 249, 298, cnlh_community4_gpps), |
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456 | 456 | }; |
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457 | 457 | |
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458 | 458 | static const struct intel_pinctrl_soc_data cnlh_soc_data = { |
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.. | .. |
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788 | 788 | }; |
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789 | 789 | |
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790 | 790 | static const struct intel_padgroup cnllp_community0_gpps[] = { |
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791 | | - CNL_GPP(0, 0, 24, 0), /* GPP_A */ |
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792 | | - CNL_GPP(1, 25, 50, 32), /* GPP_B */ |
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793 | | - CNL_GPP(2, 51, 58, 64), /* GPP_G */ |
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794 | | - CNL_GPP(3, 59, 67, CNL_NO_GPIO), /* SPI */ |
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| 791 | + CNL_GPP(0, 0, 24, 0), /* GPP_A */ |
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| 792 | + CNL_GPP(1, 25, 50, 32), /* GPP_B */ |
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| 793 | + CNL_GPP(2, 51, 58, 64), /* GPP_G */ |
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| 794 | + CNL_GPP(3, 59, 67, INTEL_GPIO_BASE_NOMAP), /* SPI */ |
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795 | 795 | }; |
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796 | 796 | |
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797 | 797 | static const struct intel_padgroup cnllp_community1_gpps[] = { |
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798 | | - CNL_GPP(0, 68, 92, 96), /* GPP_D */ |
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799 | | - CNL_GPP(1, 93, 116, 128), /* GPP_F */ |
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800 | | - CNL_GPP(2, 117, 140, 160), /* GPP_H */ |
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801 | | - CNL_GPP(3, 141, 172, 192), /* vGPIO */ |
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802 | | - CNL_GPP(4, 173, 180, 224), /* vGPIO */ |
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| 798 | + CNL_GPP(0, 68, 92, 96), /* GPP_D */ |
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| 799 | + CNL_GPP(1, 93, 116, 128), /* GPP_F */ |
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| 800 | + CNL_GPP(2, 117, 140, 160), /* GPP_H */ |
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| 801 | + CNL_GPP(3, 141, 172, 192), /* vGPIO */ |
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| 802 | + CNL_GPP(4, 173, 180, 224), /* vGPIO */ |
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803 | 803 | }; |
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804 | 804 | |
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805 | 805 | static const struct intel_padgroup cnllp_community4_gpps[] = { |
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806 | | - CNL_GPP(0, 181, 204, 256), /* GPP_C */ |
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807 | | - CNL_GPP(1, 205, 228, 288), /* GPP_E */ |
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808 | | - CNL_GPP(2, 229, 237, CNL_NO_GPIO), /* JTAG */ |
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809 | | - CNL_GPP(3, 238, 243, CNL_NO_GPIO), /* HVCMOS */ |
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| 806 | + CNL_GPP(0, 181, 204, 256), /* GPP_C */ |
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| 807 | + CNL_GPP(1, 205, 228, 288), /* GPP_E */ |
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| 808 | + CNL_GPP(2, 229, 237, INTEL_GPIO_BASE_NOMAP), /* JTAG */ |
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| 809 | + CNL_GPP(3, 238, 243, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ |
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810 | 810 | }; |
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811 | 811 | |
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812 | 812 | static const struct intel_community cnllp_communities[] = { |
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813 | | - CNLLP_COMMUNITY(0, 0, 67, cnllp_community0_gpps), |
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814 | | - CNLLP_COMMUNITY(1, 68, 180, cnllp_community1_gpps), |
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815 | | - CNLLP_COMMUNITY(2, 181, 243, cnllp_community4_gpps), |
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| 813 | + CNL_LP_COMMUNITY(0, 0, 67, cnllp_community0_gpps), |
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| 814 | + CNL_LP_COMMUNITY(1, 68, 180, cnllp_community1_gpps), |
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| 815 | + CNL_LP_COMMUNITY(2, 181, 243, cnllp_community4_gpps), |
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816 | 816 | }; |
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817 | 817 | |
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818 | 818 | static const struct intel_pinctrl_soc_data cnllp_soc_data = { |
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.. | .. |
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829 | 829 | static const struct acpi_device_id cnl_pinctrl_acpi_match[] = { |
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830 | 830 | { "INT3450", (kernel_ulong_t)&cnlh_soc_data }, |
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831 | 831 | { "INT34BB", (kernel_ulong_t)&cnllp_soc_data }, |
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832 | | - { }, |
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| 832 | + { } |
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833 | 833 | }; |
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834 | 834 | MODULE_DEVICE_TABLE(acpi, cnl_pinctrl_acpi_match); |
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835 | 835 | |
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836 | | -static int cnl_pinctrl_probe(struct platform_device *pdev) |
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837 | | -{ |
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838 | | - const struct intel_pinctrl_soc_data *soc_data; |
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839 | | - const struct acpi_device_id *id; |
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840 | | - |
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841 | | - id = acpi_match_device(cnl_pinctrl_acpi_match, &pdev->dev); |
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842 | | - if (!id || !id->driver_data) |
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843 | | - return -ENODEV; |
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844 | | - |
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845 | | - soc_data = (const struct intel_pinctrl_soc_data *)id->driver_data; |
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846 | | - return intel_pinctrl_probe(pdev, soc_data); |
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847 | | -} |
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848 | | - |
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849 | | -static const struct dev_pm_ops cnl_pinctrl_pm_ops = { |
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850 | | - SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend, |
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851 | | - intel_pinctrl_resume) |
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852 | | -}; |
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| 836 | +static INTEL_PINCTRL_PM_OPS(cnl_pinctrl_pm_ops); |
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853 | 837 | |
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854 | 838 | static struct platform_driver cnl_pinctrl_driver = { |
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855 | | - .probe = cnl_pinctrl_probe, |
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| 839 | + .probe = intel_pinctrl_probe_by_hid, |
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856 | 840 | .driver = { |
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857 | 841 | .name = "cannonlake-pinctrl", |
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858 | 842 | .acpi_match_table = cnl_pinctrl_acpi_match, |
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