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2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390 
 kernel/drivers/net/wireless/realtek/rtlwifi/rtl8192se/phy.c
....@@ -1,27 +1,5 @@
1
-/******************************************************************************
2
- *
3
- * Copyright(c) 2009-2012  Realtek Corporation.
4
- *
5
- * This program is free software; you can redistribute it and/or modify it
6
- * under the terms of version 2 of the GNU General Public License as
7
- * published by the Free Software Foundation.
8
- *
9
- * This program is distributed in the hope that it will be useful, but WITHOUT
10
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12
- * more details.
13
- *
14
- * The full GNU General Public License is included in this distribution in the
15
- * file called LICENSE.
16
- *
17
- * Contact Information:
18
- * wlanfae <wlanfae@realtek.com>
19
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20
- * Hsinchu 300, Taiwan.
21
- *
22
- * Larry Finger <Larry.Finger@lwfinger.net>
23
- *
24
- *****************************************************************************/
1
+// SPDX-License-Identifier: GPL-2.0
2
+/* Copyright(c) 2009-2012  Realtek Corporation.*/
253 
264 #include "../wifi.h"
275 #include "../pci.h"
....@@ -38,14 +16,9 @@
3816 
3917 static u32 _rtl92s_phy_calculate_bit_shift(u32 bitmask)
4018 {
41
-	u32 i;
19
+	u32 i = ffs(bitmask);
4220 
43
-	for (i = 0; i <= 31; i++) {
44
-		if (((bitmask >> i) & 0x1) == 1)
45
-			break;
46
-	}
47
-
48
-	return i;
21
+	return i ? i - 1 : 32;
4922 }
5023 
5124 u32 rtl92s_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
....@@ -53,15 +26,15 @@
5326 	struct rtl_priv *rtlpriv = rtl_priv(hw);
5427 	u32 returnvalue = 0, originalvalue, bitshift;
5528 
56
-	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n",
57
-		 regaddr, bitmask);
29
+	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n",
30
+		regaddr, bitmask);
5831 
5932 	originalvalue = rtl_read_dword(rtlpriv, regaddr);
6033 	bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
6134 	returnvalue = (originalvalue & bitmask) >> bitshift;
6235 
63
-	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "BBR MASK=0x%x Addr[0x%x]=0x%x\n",
64
-		 bitmask, regaddr, originalvalue);
36
+	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "BBR MASK=0x%x Addr[0x%x]=0x%x\n",
37
+		bitmask, regaddr, originalvalue);
6538 
6639 	return returnvalue;
6740 
....@@ -73,9 +46,9 @@
7346 	struct rtl_priv *rtlpriv = rtl_priv(hw);
7447 	u32 originalvalue, bitshift;
7548 
76
-	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
77
-		 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
78
-		 regaddr, bitmask, data);
49
+	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
50
+		"regaddr(%#x), bitmask(%#x), data(%#x)\n",
51
+		regaddr, bitmask, data);
7952 
8053 	if (bitmask != MASKDWORD) {
8154 		originalvalue = rtl_read_dword(rtlpriv, regaddr);
....@@ -85,9 +58,9 @@
8558 
8659 	rtl_write_dword(rtlpriv, regaddr, data);
8760 
88
-	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
89
-		 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
90
-		 regaddr, bitmask, data);
61
+	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
62
+		"regaddr(%#x), bitmask(%#x), data(%#x)\n",
63
+		regaddr, bitmask, data);
9164 
9265 }
9366 
....@@ -145,8 +118,8 @@
145118 	retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
146119 				 BLSSI_READBACK_DATA);
147120 
148
-	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x]=0x%x\n",
149
-		 rfpath, pphyreg->rf_rb, retvalue);
121
+	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x]=0x%x\n",
122
+		rfpath, pphyreg->rf_rb, retvalue);
150123 
151124 	return retvalue;
152125 
....@@ -168,8 +141,8 @@
168141 	data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
169142 	rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
170143 
171
-	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
172
-		 rfpath, pphyreg->rf3wire_offset, data_and_addr);
144
+	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
145
+		rfpath, pphyreg->rf3wire_offset, data_and_addr);
173146 }
174147 
175148 
....@@ -179,8 +152,8 @@
179152 	struct rtl_priv *rtlpriv = rtl_priv(hw);
180153 	u32 original_value, readback_value, bitshift;
181154 
182
-	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
183
-		 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
155
+	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
156
+		"regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
184157 		 regaddr, rfpath, bitmask);
185158 
186159 	spin_lock(&rtlpriv->locks.rf_lock);
....@@ -192,9 +165,9 @@
192165 
193166 	spin_unlock(&rtlpriv->locks.rf_lock);
194167 
195
-	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
196
-		 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
197
-		 regaddr, rfpath, bitmask, original_value);
168
+	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
169
+		"regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
170
+		regaddr, rfpath, bitmask, original_value);
198171 
199172 	return readback_value;
200173 }
....@@ -209,9 +182,9 @@
209182 	if (!((rtlphy->rf_pathmap >> rfpath) & 0x1))
210183 		return;
211184 
212
-	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
213
-		 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
214
-		 regaddr, bitmask, data, rfpath);
185
+	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
186
+		"regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
187
+		regaddr, bitmask, data, rfpath);
215188 
216189 	spin_lock(&rtlpriv->locks.rf_lock);
217190 
....@@ -226,9 +199,9 @@
226199 
227200 	spin_unlock(&rtlpriv->locks.rf_lock);
228201 
229
-	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
230
-		 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
231
-		 regaddr, bitmask, data, rfpath);
202
+	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
203
+		"regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
204
+		regaddr, bitmask, data, rfpath);
232205 
233206 }
234207 
....@@ -261,9 +234,9 @@
261234 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
262235 	u8 reg_bw_opmode;
263236 
264
-	RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
265
-		 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
266
-		 "20MHz" : "40MHz");
237
+	rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
238
+		rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
239
+		"20MHz" : "40MHz");
267240 
268241 	if (rtlphy->set_bwmode_inprogress)
269242 		return;
....@@ -318,7 +291,7 @@
318291 
319292 	rtl92s_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
320293 	rtlphy->set_bwmode_inprogress = false;
321
-	RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
294
+	rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
322295 }
323296 
324297 static bool _rtl92s_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
....@@ -456,8 +429,8 @@
456429 	u32 delay;
457430 	bool ret;
458431 
459
-	RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "switch to channel%d\n",
460
-		 rtlphy->current_channel);
432
+	rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "switch to channel%d\n",
433
+		rtlphy->current_channel);
461434 
462435 	if (rtlphy->sw_chnl_inprogress)
463436 		return 0;
....@@ -493,7 +466,7 @@
493466 
494467 	rtlphy->sw_chnl_inprogress = false;
495468 
496
-	RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
469
+	rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
497470 
498471 	return 1;
499472 }
....@@ -549,23 +522,22 @@
549522 			    RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
550523 
551524 				bool rtstatus;
552
-				u32 InitializeCount = 0;
525
+				u32 initializecount = 0;
553526 				do {
554
-					InitializeCount++;
555
-					RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
556
-						 "IPS Set eRf nic enable\n");
527
+					initializecount++;
528
+					rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
529
+						"IPS Set eRf nic enable\n");
557530 					rtstatus = rtl_ps_enable_nic(hw);
558
-				} while (!rtstatus && (InitializeCount < 10));
531
+				} while (!rtstatus && (initializecount < 10));
559532 
560533 				RT_CLEAR_PS_LEVEL(ppsc,
561534 						  RT_RF_OFF_LEVL_HALT_NIC);
562535 			} else {
563
-				RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
564
-					 "awake, sleeped:%d ms state_inap:%x\n",
565
-					 jiffies_to_msecs(jiffies -
566
-							  ppsc->
567
-							  last_sleep_jiffies),
568
-					 rtlpriv->psc.state_inap);
536
+				rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
537
+					"awake, slept:%d ms state_inap:%x\n",
538
+					jiffies_to_msecs(jiffies -
539
+					ppsc->last_sleep_jiffies),
540
+					rtlpriv->psc.state_inap);
569541 				ppsc->last_awake_jiffies = jiffies;
570542 				rtl_write_word(rtlpriv, CMDR, 0x37FC);
571543 				rtl_write_byte(rtlpriv, TXPAUSE, 0x00);
....@@ -582,8 +554,8 @@
582554 		}
583555 	case ERFOFF:{
584556 			if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
585
-				RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
586
-					 "IPS Set eRf nic disable\n");
557
+				rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
558
+					"IPS Set eRf nic disable\n");
587559 				rtl_ps_disable_nic(hw);
588560 				RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
589561 			} else {
....@@ -608,34 +580,34 @@
608580 					queue_id++;
609581 					continue;
610582 				} else {
611
-					RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
612
-						 "eRf Off/Sleep: %d times TcbBusyQueue[%d] = %d before doze!\n",
613
-						 i + 1, queue_id,
614
-						 skb_queue_len(&ring->queue));
583
+					rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
584
+						"eRf Off/Sleep: %d times TcbBusyQueue[%d] = %d before doze!\n",
585
+						i + 1, queue_id,
586
+						skb_queue_len(&ring->queue));
615587 
616588 					udelay(10);
617589 					i++;
618590 				}
619591 
620592 				if (i >= MAX_DOZE_WAITING_TIMES_9x) {
621
-					RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
622
-						 "ERFOFF: %d times TcbBusyQueue[%d] = %d !\n",
623
-						 MAX_DOZE_WAITING_TIMES_9x,
624
-						 queue_id,
625
-						 skb_queue_len(&ring->queue));
593
+					rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
594
+						"ERFOFF: %d times TcbBusyQueue[%d] = %d !\n",
595
+						MAX_DOZE_WAITING_TIMES_9x,
596
+						queue_id,
597
+						skb_queue_len(&ring->queue));
626598 					break;
627599 				}
628600 			}
629601 
630
-			RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
631
-				 "Set ERFSLEEP awaked:%d ms\n",
632
-				 jiffies_to_msecs(jiffies -
633
-						  ppsc->last_awake_jiffies));
602
+			rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
603
+				"Set ERFSLEEP awaked:%d ms\n",
604
+				jiffies_to_msecs(jiffies -
605
+						 ppsc->last_awake_jiffies));
634606 
635
-			RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
636
-				 "sleep awaked:%d ms state_inap:%x\n",
637
-				 jiffies_to_msecs(jiffies -
638
-						  ppsc->last_awake_jiffies),
607
+			rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
608
+				"sleep awaked:%d ms state_inap:%x\n",
609
+				jiffies_to_msecs(jiffies -
610
+						 ppsc->last_awake_jiffies),
639611 				 rtlpriv->psc.state_inap);
640612 			ppsc->last_sleep_jiffies = jiffies;
641613 			_rtl92se_phy_set_rf_sleep(hw);
....@@ -935,7 +907,7 @@
935907 
936908 	if (!rtstatus) {
937909 		pr_err("Write BB Reg Fail!!\n");
938
-		goto phy_BB8190_Config_ParaFile_Fail;
910
+		goto phy_bb8190_config_parafile_fail;
939911 	}
940912 
941913 	/* 2. If EEPROM or EFUSE autoload OK, We must config by
....@@ -948,7 +920,7 @@
948920 	}
949921 	if (!rtstatus) {
950922 		pr_err("_rtl92s_phy_bb_config_parafile(): BB_PG Reg Fail!!\n");
951
-		goto phy_BB8190_Config_ParaFile_Fail;
923
+		goto phy_bb8190_config_parafile_fail;
952924 	}
953925 
954926 	/* 3. BB AGC table Initialization */
....@@ -956,7 +928,7 @@
956928 
957929 	if (!rtstatus) {
958930 		pr_err("%s(): AGC Table Fail\n", __func__);
959
-		goto phy_BB8190_Config_ParaFile_Fail;
931
+		goto phy_bb8190_config_parafile_fail;
960932 	}
961933 
962934 	/* Check if the CCK HighPower is turned ON. */
....@@ -964,7 +936,7 @@
964936 	rtlphy->cck_high_power = (bool)(rtl92s_phy_query_bb_reg(hw,
965937 			RFPGA0_XA_HSSIPARAMETER2, 0x200));
966938 
967
-phy_BB8190_Config_ParaFile_Fail:
939
+phy_bb8190_config_parafile_fail:
968940 	return rtstatus;
969941 }
970942 
....@@ -990,7 +962,7 @@
990962 		radio_b_tblen = RADIOB_ARRAYLENGTH;
991963 	}
992964 
993
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath);
965
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath);
994966 	rtstatus = true;
995967 
996968 	switch (rfpath) {
....@@ -1029,13 +1001,13 @@
10291001 	struct rtl_priv *rtlpriv = rtl_priv(hw);
10301002 	u32 i;
10311003 	u32 arraylength;
1032
-	u32 *ptraArray;
1004
+	u32 *ptrarray;
10331005 
10341006 	arraylength = MAC_2T_ARRAYLENGTH;
1035
-	ptraArray = rtl8192semac_2t_array;
1007
+	ptrarray = rtl8192semac_2t_array;
10361008 
10371009 	for (i = 0; i < arraylength; i = i + 2)
1038
-		rtl_write_byte(rtlpriv, ptraArray[i], (u8)ptraArray[i + 1]);
1010
+		rtl_write_byte(rtlpriv, ptrarray[i], (u8)ptrarray[i + 1]);
10391011 
10401012 	return true;
10411013 }
....@@ -1110,25 +1082,25 @@
11101082 			ROFDM0_XCAGCCORE1, MASKBYTE0);
11111083 	rtlphy->default_initialgain[3] = rtl_get_bbreg(hw,
11121084 			ROFDM0_XDAGCCORE1, MASKBYTE0);
1113
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1114
-		 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
1115
-		 rtlphy->default_initialgain[0],
1116
-		 rtlphy->default_initialgain[1],
1117
-		 rtlphy->default_initialgain[2],
1118
-		 rtlphy->default_initialgain[3]);
1085
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1086
+		"Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
1087
+		rtlphy->default_initialgain[0],
1088
+		rtlphy->default_initialgain[1],
1089
+		rtlphy->default_initialgain[2],
1090
+		rtlphy->default_initialgain[3]);
11191091 
11201092 	/* read framesync */
11211093 	rtlphy->framesync = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, MASKBYTE0);
11221094 	rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
11231095 					      MASKDWORD);
1124
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1125
-		 "Default framesync (0x%x) = 0x%x\n",
1126
-		 ROFDM0_RXDETECTOR3, rtlphy->framesync);
1096
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1097
+		"Default framesync (0x%x) = 0x%x\n",
1098
+		ROFDM0_RXDETECTOR3, rtlphy->framesync);
11271099 
11281100 }
11291101 
11301102 static void _rtl92s_phy_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
1131
-					  u8 *cckpowerlevel, u8 *ofdmpowerLevel)
1103
+					  u8 *cckpowerlevel, u8 *ofdmpowerlevel)
11321104 {
11331105 	struct rtl_priv *rtlpriv = rtl_priv(hw);
11341106 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
....@@ -1144,15 +1116,15 @@
11441116 	/* 2. OFDM for 1T or 2T */
11451117 	if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) {
11461118 		/* Read HT 40 OFDM TX power */
1147
-		ofdmpowerLevel[0] = rtlefuse->txpwrlevel_ht40_1s[0][index];
1148
-		ofdmpowerLevel[1] = rtlefuse->txpwrlevel_ht40_1s[1][index];
1119
+		ofdmpowerlevel[0] = rtlefuse->txpwrlevel_ht40_1s[0][index];
1120
+		ofdmpowerlevel[1] = rtlefuse->txpwrlevel_ht40_1s[1][index];
11491121 	} else if (rtlphy->rf_type == RF_2T2R) {
11501122 		/* Read HT 40 OFDM TX power */
1151
-		ofdmpowerLevel[0] = rtlefuse->txpwrlevel_ht40_2s[0][index];
1152
-		ofdmpowerLevel[1] = rtlefuse->txpwrlevel_ht40_2s[1][index];
1123
+		ofdmpowerlevel[0] = rtlefuse->txpwrlevel_ht40_2s[0][index];
1124
+		ofdmpowerlevel[1] = rtlefuse->txpwrlevel_ht40_2s[1][index];
11531125 	} else {
1154
-		ofdmpowerLevel[0] = 0;
1155
-		ofdmpowerLevel[1] = 0;
1126
+		ofdmpowerlevel[0] = 0;
1127
+		ofdmpowerlevel[1] = 0;
11561128 	}
11571129 }
11581130 
....@@ -1171,7 +1143,7 @@
11711143 	struct rtl_priv *rtlpriv = rtl_priv(hw);
11721144 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
11731145 	/* [0]:RF-A, [1]:RF-B */
1174
-	u8 cckpowerlevel[2], ofdmpowerLevel[2];
1146
+	u8 cckpowerlevel[2], ofdmpowerlevel[2];
11751147 
11761148 	if (!rtlefuse->txpwr_fromeprom)
11771149 		return;
....@@ -1183,18 +1155,18 @@
11831155 	 * 1. For CCK.
11841156 	 * 2. For OFDM 1T or 2T */
11851157 	_rtl92s_phy_get_txpower_index(hw, channel, &cckpowerlevel[0],
1186
-			&ofdmpowerLevel[0]);
1158
+			&ofdmpowerlevel[0]);
11871159 
1188
-	RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1189
-		 "Channel-%d, cckPowerLevel (A / B) = 0x%x / 0x%x, ofdmPowerLevel (A / B) = 0x%x / 0x%x\n",
1190
-		 channel, cckpowerlevel[0], cckpowerlevel[1],
1191
-		 ofdmpowerLevel[0], ofdmpowerLevel[1]);
1160
+	rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
1161
+		"Channel-%d, cckPowerLevel (A / B) = 0x%x / 0x%x, ofdmPowerLevel (A / B) = 0x%x / 0x%x\n",
1162
+		channel, cckpowerlevel[0], cckpowerlevel[1],
1163
+		ofdmpowerlevel[0], ofdmpowerlevel[1]);
11921164 
11931165 	_rtl92s_phy_ccxpower_indexcheck(hw, channel, &cckpowerlevel[0],
1194
-			&ofdmpowerLevel[0]);
1166
+			&ofdmpowerlevel[0]);
11951167 
11961168 	rtl92s_phy_rf6052_set_ccktxpower(hw, cckpowerlevel[0]);
1197
-	rtl92s_phy_rf6052_set_ofdmtxpower(hw, &ofdmpowerLevel[0], channel);
1169
+	rtl92s_phy_rf6052_set_ofdmtxpower(hw, &ofdmpowerlevel[0], channel);
11981170 
11991171 }
12001172 
....@@ -1246,17 +1218,17 @@
12461218 skip:
12471219 	switch (rtlhal->current_fwcmd_io) {
12481220 	case FW_CMD_RA_RESET:
1249
-		RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_RESET\n");
1221
+		rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_RESET\n");
12501222 		rtl_write_dword(rtlpriv, WFM5, FW_RA_RESET);
12511223 		rtl92s_phy_chk_fwcmd_iodone(hw);
12521224 		break;
12531225 	case FW_CMD_RA_ACTIVE:
1254
-		RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_ACTIVE\n");
1226
+		rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_ACTIVE\n");
12551227 		rtl_write_dword(rtlpriv, WFM5, FW_RA_ACTIVE);
12561228 		rtl92s_phy_chk_fwcmd_iodone(hw);
12571229 		break;
12581230 	case FW_CMD_RA_REFRESH_N:
1259
-		RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_REFRESH_N\n");
1231
+		rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_REFRESH_N\n");
12601232 		input = FW_RA_REFRESH;
12611233 		rtl_write_dword(rtlpriv, WFM5, input);
12621234 		rtl92s_phy_chk_fwcmd_iodone(hw);
....@@ -1264,29 +1236,29 @@
12641236 		rtl92s_phy_chk_fwcmd_iodone(hw);
12651237 		break;
12661238 	case FW_CMD_RA_REFRESH_BG:
1267
-		RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1268
-			 "FW_CMD_RA_REFRESH_BG\n");
1239
+		rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG,
1240
+			"FW_CMD_RA_REFRESH_BG\n");
12691241 		rtl_write_dword(rtlpriv, WFM5, FW_RA_REFRESH);
12701242 		rtl92s_phy_chk_fwcmd_iodone(hw);
12711243 		rtl_write_dword(rtlpriv, WFM5, FW_RA_DISABLE_RSSI_MASK);
12721244 		rtl92s_phy_chk_fwcmd_iodone(hw);
12731245 		break;
12741246 	case FW_CMD_RA_REFRESH_N_COMB:
1275
-		RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1276
-			 "FW_CMD_RA_REFRESH_N_COMB\n");
1247
+		rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG,
1248
+			"FW_CMD_RA_REFRESH_N_COMB\n");
12771249 		input = FW_RA_IOT_N_COMB;
12781250 		rtl_write_dword(rtlpriv, WFM5, input);
12791251 		rtl92s_phy_chk_fwcmd_iodone(hw);
12801252 		break;
12811253 	case FW_CMD_RA_REFRESH_BG_COMB:
1282
-		RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1283
-			 "FW_CMD_RA_REFRESH_BG_COMB\n");
1254
+		rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG,
1255
+			"FW_CMD_RA_REFRESH_BG_COMB\n");
12841256 		input = FW_RA_IOT_BG_COMB;
12851257 		rtl_write_dword(rtlpriv, WFM5, input);
12861258 		rtl92s_phy_chk_fwcmd_iodone(hw);
12871259 		break;
12881260 	case FW_CMD_IQK_ENABLE:
1289
-		RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_IQK_ENABLE\n");
1261
+		rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_IQK_ENABLE\n");
12901262 		rtl_write_dword(rtlpriv, WFM5, FW_IQK_ENABLE);
12911263 		rtl92s_phy_chk_fwcmd_iodone(hw);
12921264 		break;
....@@ -1321,7 +1293,7 @@
13211293 		rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
13221294 		break;
13231295 	case FW_CMD_LPS_ENTER:
1324
-		RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_LPS_ENTER\n");
1296
+		rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_LPS_ENTER\n");
13251297 		current_aid = rtlpriv->mac80211.assoc_id;
13261298 		rtl_write_dword(rtlpriv, WFM5, (FW_LPS_ENTER |
13271299 				((current_aid | 0xc000) << 8)));
....@@ -1330,18 +1302,18 @@
13301302 		 * turbo mode until driver leave LPS */
13311303 		break;
13321304 	case FW_CMD_LPS_LEAVE:
1333
-		RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_LPS_LEAVE\n");
1305
+		rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_LPS_LEAVE\n");
13341306 		rtl_write_dword(rtlpriv, WFM5, FW_LPS_LEAVE);
13351307 		rtl92s_phy_chk_fwcmd_iodone(hw);
13361308 		break;
13371309 	case FW_CMD_ADD_A2_ENTRY:
1338
-		RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_ADD_A2_ENTRY\n");
1310
+		rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_ADD_A2_ENTRY\n");
13391311 		rtl_write_dword(rtlpriv, WFM5, FW_ADD_A2_ENTRY);
13401312 		rtl92s_phy_chk_fwcmd_iodone(hw);
13411313 		break;
13421314 	case FW_CMD_CTRL_DM_BY_DRIVER:
1343
-		RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1344
-			 "FW_CMD_CTRL_DM_BY_DRIVER\n");
1315
+		rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
1316
+			"FW_CMD_CTRL_DM_BY_DRIVER\n");
13451317 		rtl_write_dword(rtlpriv, WFM5, FW_CTRL_DM_BY_DRIVER);
13461318 		rtl92s_phy_chk_fwcmd_iodone(hw);
13471319 		break;
....@@ -1366,9 +1338,9 @@
13661338 	u16	fw_cmdmap = FW_CMD_IO_QUERY(rtlpriv);
13671339 	bool postprocessing = false;
13681340 
1369
-	RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1370
-		 "Set FW Cmd(%#x), set_fwcmd_inprogress(%d)\n",
1371
-		 fw_cmdio, rtlhal->set_fwcmd_inprogress);
1341
+	rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
1342
+		"Set FW Cmd(%#x), set_fwcmd_inprogress(%d)\n",
1343
+		fw_cmdio, rtlhal->set_fwcmd_inprogress);
13721344 
13731345 	do {
13741346 		/* We re-map to combined FW CMD ones if firmware version */
....@@ -1405,30 +1377,30 @@
14051377 		 * DM map table in the future. */
14061378 		switch (fw_cmdio) {
14071379 		case FW_CMD_RA_INIT:
1408
-			RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "RA init!!\n");
1380
+			rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "RA init!!\n");
14091381 			fw_cmdmap |= FW_RA_INIT_CTL;
14101382 			FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
14111383 			/* Clear control flag to sync with FW. */
14121384 			FW_CMD_IO_CLR(rtlpriv, FW_RA_INIT_CTL);
14131385 			break;
14141386 		case FW_CMD_DIG_DISABLE:
1415
-			RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1416
-				 "Set DIG disable!!\n");
1387
+			rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
1388
+				"Set DIG disable!!\n");
14171389 			fw_cmdmap &= ~FW_DIG_ENABLE_CTL;
14181390 			FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
14191391 			break;
14201392 		case FW_CMD_DIG_ENABLE:
14211393 		case FW_CMD_DIG_RESUME:
14221394 			if (!(rtlpriv->dm.dm_flag & HAL_DM_DIG_DISABLE)) {
1423
-				RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1424
-					 "Set DIG enable or resume!!\n");
1395
+				rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
1396
+					"Set DIG enable or resume!!\n");
14251397 				fw_cmdmap |= (FW_DIG_ENABLE_CTL | FW_SS_CTL);
14261398 				FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
14271399 			}
14281400 			break;
14291401 		case FW_CMD_DIG_HALT:
1430
-			RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1431
-				 "Set DIG halt!!\n");
1402
+			rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
1403
+				"Set DIG halt!!\n");
14321404 			fw_cmdmap &= ~(FW_DIG_ENABLE_CTL | FW_SS_CTL);
14331405 			FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
14341406 			break;
....@@ -1443,9 +1415,9 @@
14431415 			fw_param |= ((thermalval << 24) |
14441416 				     (rtlefuse->thermalmeter[0] << 16));
14451417 
1446
-			RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1447
-				 "Set TxPwr tracking!! FwCmdMap(%#x), FwParam(%#x)\n",
1448
-				 fw_cmdmap, fw_param);
1418
+			rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
1419
+				"Set TxPwr tracking!! FwCmdMap(%#x), FwParam(%#x)\n",
1420
+				fw_cmdmap, fw_param);
14491421 
14501422 			FW_CMD_PARA_SET(rtlpriv, fw_param);
14511423 			FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
....@@ -1465,9 +1437,9 @@
14651437 			/* Clear FW parameter in terms of RA parts. */
14661438 			fw_param &= FW_RA_PARAM_CLR;
14671439 
1468
-			RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1469
-				 "[FW CMD] [New Version] Set RA/IOT Comb in n mode!! FwCmdMap(%#x), FwParam(%#x)\n",
1470
-				 fw_cmdmap, fw_param);
1440
+			rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
1441
+				"[FW CMD] [New Version] Set RA/IOT Comb in n mode!! FwCmdMap(%#x), FwParam(%#x)\n",
1442
+				fw_cmdmap, fw_param);
14711443 
14721444 			FW_CMD_PARA_SET(rtlpriv, fw_param);
14731445 			FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
....@@ -1553,8 +1525,8 @@
15531525 			FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
15541526 			break;
15551527 		case FW_CMD_PAPE_CONTROL:
1556
-			RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1557
-				 "[FW CMD] Set PAPE Control\n");
1528
+			rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
1529
+				"[FW CMD] Set PAPE Control\n");
15581530 			fw_cmdmap &= ~FW_PAPE_CTL_BY_SW_HW;
15591531 
15601532 			FW_CMD_IO_SET(rtlpriv, fw_cmdmap);