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2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390 
 kernel/drivers/net/wireless/ath/ath10k/pci.c
....@@ -1,18 +1,7 @@
1
+// SPDX-License-Identifier: ISC
12 /*
23  * Copyright (c) 2005-2011 Atheros Communications Inc.
34  * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
4
- *
5
- * Permission to use, copy, modify, and/or distribute this software for any
6
- * purpose with or without fee is hereby granted, provided that the above
7
- * copyright notice and this permission notice appear in all copies.
8
- *
9
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
165  */
176 
187 #include <linux/pci.h>
....@@ -127,7 +116,7 @@
127116 static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state);
128117 static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state);
129118 
130
-static struct ce_attr host_ce_config_wlan[] = {
119
+static const struct ce_attr pci_host_ce_config_wlan[] = {
131120 	/* CE0: host->target HTC control and raw streams */
132121 	{
133122 		.flags = CE_ATTR_FLAGS,
....@@ -192,7 +181,7 @@
192181 
193182 	/* CE7: ce_diag, the Diagnostic Window */
194183 	{
195
-		.flags = CE_ATTR_FLAGS,
184
+		.flags = CE_ATTR_FLAGS | CE_ATTR_POLL,
196185 		.src_nentries = 2,
197186 		.src_sz_max = DIAG_TRANSFER_LIMIT,
198187 		.dest_nentries = 2,
....@@ -233,7 +222,7 @@
233222 };
234223 
235224 /* Target firmware's Copy Engine configuration. */
236
-static struct ce_pipe_config target_ce_config_wlan[] = {
225
+static const struct ce_pipe_config pci_target_ce_config_wlan[] = {
237226 	/* CE0: host->target HTC control and raw streams */
238227 	{
239228 		.pipenum = __cpu_to_le32(0),
....@@ -346,7 +335,7 @@
346335  * This table is derived from the CE_PCI TABLE, above.
347336  * It is passed to the Target at startup for use by firmware.
348337  */
349
-static struct service_to_pipe target_service_to_ce_map_wlan[] = {
338
+static const struct ce_service_to_pipe pci_target_service_to_ce_map_wlan[] = {
350339 	{
351340 		__cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
352341 		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
....@@ -870,6 +859,21 @@
870859 	return val;
871860 }
872861 
862
+/* Refactor from ath10k_pci_qca988x_targ_cpu_to_ce_addr.
863
+ * Support to access target space below 1M for qca6174 and qca9377.
864
+ * If target space is below 1M, the bit[20] of converted CE addr is 0.
865
+ * Otherwise bit[20] of converted CE addr is 1.
866
+ */
867
+static u32 ath10k_pci_qca6174_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
868
+{
869
+	u32 val = 0, region = addr & 0xfffff;
870
+
871
+	val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS)
872
+				 & 0x7ff) << 21;
873
+	val |= ((addr >= 0x100000) ? 0x100000 : 0) | region;
874
+	return val;
875
+}
876
+
873877 static u32 ath10k_pci_qca99x0_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
874878 {
875879 	u32 val = 0, region = addr & 0xfffff;
....@@ -898,7 +902,6 @@
898902 				    int nbytes)
899903 {
900904 	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
901
-	struct ath10k_ce *ce = ath10k_ce_priv(ar);
902905 	int ret = 0;
903906 	u32 *buf;
904907 	unsigned int completed_nbytes, alloc_nbytes, remaining_bytes;
....@@ -906,11 +909,10 @@
906909 	/* Host buffer address in CE space */
907910 	u32 ce_data;
908911 	dma_addr_t ce_data_base = 0;
909
-	void *data_buf = NULL;
912
+	void *data_buf;
910913 	int i;
911914 
912
-	spin_lock_bh(&ce->ce_lock);
913
-
915
+	mutex_lock(&ar_pci->ce_diag_mutex);
914916 	ce_diag = ar_pci->ce_diag;
915917 
916918 	/*
....@@ -921,15 +923,21 @@
921923 	 */
922924 	alloc_nbytes = min_t(unsigned int, nbytes, DIAG_TRANSFER_LIMIT);
923925 
924
-	data_buf = (unsigned char *)dma_zalloc_coherent(ar->dev,
925
-						       alloc_nbytes,
926
-						       &ce_data_base,
927
-						       GFP_ATOMIC);
928
-
926
+	data_buf = dma_alloc_coherent(ar->dev, alloc_nbytes, &ce_data_base,
927
+				      GFP_ATOMIC);
929928 	if (!data_buf) {
930929 		ret = -ENOMEM;
931930 		goto done;
932931 	}
932
+
933
+	/* The address supplied by the caller is in the
934
+	 * Target CPU virtual address space.
935
+	 *
936
+	 * In order to use this address with the diagnostic CE,
937
+	 * convert it from Target CPU virtual address space
938
+	 * to CE address space
939
+	 */
940
+	address = ath10k_pci_targ_cpu_to_ce_addr(ar, address);
933941 
934942 	remaining_bytes = nbytes;
935943 	ce_data = ce_data_base;
....@@ -937,44 +945,33 @@
937945 		nbytes = min_t(unsigned int, remaining_bytes,
938946 			       DIAG_TRANSFER_LIMIT);
939947 
940
-		ret = ce_diag->ops->ce_rx_post_buf(ce_diag, &ce_data, ce_data);
948
+		ret = ath10k_ce_rx_post_buf(ce_diag, &ce_data, ce_data);
941949 		if (ret != 0)
942950 			goto done;
943951 
944952 		/* Request CE to send from Target(!) address to Host buffer */
945
-		/*
946
-		 * The address supplied by the caller is in the
947
-		 * Target CPU virtual address space.
948
-		 *
949
-		 * In order to use this address with the diagnostic CE,
950
-		 * convert it from Target CPU virtual address space
951
-		 * to CE address space
952
-		 */
953
-		address = ath10k_pci_targ_cpu_to_ce_addr(ar, address);
954
-
955
-		ret = ath10k_ce_send_nolock(ce_diag, NULL, (u32)address, nbytes, 0,
956
-					    0);
953
+		ret = ath10k_ce_send(ce_diag, NULL, (u32)address, nbytes, 0, 0);
957954 		if (ret)
958955 			goto done;
959956 
960957 		i = 0;
961
-		while (ath10k_ce_completed_send_next_nolock(ce_diag,
962
-							    NULL) != 0) {
963
-			mdelay(1);
964
-			if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
958
+		while (ath10k_ce_completed_send_next(ce_diag, NULL) != 0) {
959
+			udelay(DIAG_ACCESS_CE_WAIT_US);
960
+			i += DIAG_ACCESS_CE_WAIT_US;
961
+
962
+			if (i > DIAG_ACCESS_CE_TIMEOUT_US) {
965963 				ret = -EBUSY;
966964 				goto done;
967965 			}
968966 		}
969967 
970968 		i = 0;
971
-		while (ath10k_ce_completed_recv_next_nolock(ce_diag,
972
-							    (void **)&buf,
973
-							    &completed_nbytes)
974
-								!= 0) {
975
-			mdelay(1);
969
+		while (ath10k_ce_completed_recv_next(ce_diag, (void **)&buf,
970
+						     &completed_nbytes) != 0) {
971
+			udelay(DIAG_ACCESS_CE_WAIT_US);
972
+			i += DIAG_ACCESS_CE_WAIT_US;
976973 
977
-			if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
974
+			if (i > DIAG_ACCESS_CE_TIMEOUT_US) {
978975 				ret = -EBUSY;
979976 				goto done;
980977 			}
....@@ -1003,7 +1000,7 @@
10031000 		dma_free_coherent(ar->dev, alloc_nbytes, data_buf,
10041001 				  ce_data_base);
10051002 
1006
-	spin_unlock_bh(&ce->ce_lock);
1003
+	mutex_unlock(&ar_pci->ce_diag_mutex);
10071004 
10081005 	return ret;
10091006 }
....@@ -1051,17 +1048,15 @@
10511048 			      const void *data, int nbytes)
10521049 {
10531050 	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1054
-	struct ath10k_ce *ce = ath10k_ce_priv(ar);
10551051 	int ret = 0;
10561052 	u32 *buf;
10571053 	unsigned int completed_nbytes, alloc_nbytes, remaining_bytes;
10581054 	struct ath10k_ce_pipe *ce_diag;
1059
-	void *data_buf = NULL;
1055
+	void *data_buf;
10601056 	dma_addr_t ce_data_base = 0;
10611057 	int i;
10621058 
1063
-	spin_lock_bh(&ce->ce_lock);
1064
-
1059
+	mutex_lock(&ar_pci->ce_diag_mutex);
10651060 	ce_diag = ar_pci->ce_diag;
10661061 
10671062 	/*
....@@ -1072,10 +1067,8 @@
10721067 	 */
10731068 	alloc_nbytes = min_t(unsigned int, nbytes, DIAG_TRANSFER_LIMIT);
10741069 
1075
-	data_buf = (unsigned char *)dma_alloc_coherent(ar->dev,
1076
-						       alloc_nbytes,
1077
-						       &ce_data_base,
1078
-						       GFP_ATOMIC);
1070
+	data_buf = dma_alloc_coherent(ar->dev, alloc_nbytes, &ce_data_base,
1071
+				      GFP_ATOMIC);
10791072 	if (!data_buf) {
10801073 		ret = -ENOMEM;
10811074 		goto done;
....@@ -1102,7 +1095,7 @@
11021095 		memcpy(data_buf, data, nbytes);
11031096 
11041097 		/* Set up to receive directly into Target(!) address */
1105
-		ret = ce_diag->ops->ce_rx_post_buf(ce_diag, &address, address);
1098
+		ret = ath10k_ce_rx_post_buf(ce_diag, &address, address);
11061099 		if (ret != 0)
11071100 			goto done;
11081101 
....@@ -1110,30 +1103,28 @@
11101103 		 * Request CE to send caller-supplied data that
11111104 		 * was copied to bounce buffer to Target(!) address.
11121105 		 */
1113
-		ret = ath10k_ce_send_nolock(ce_diag, NULL, ce_data_base,
1114
-					    nbytes, 0, 0);
1106
+		ret = ath10k_ce_send(ce_diag, NULL, ce_data_base, nbytes, 0, 0);
11151107 		if (ret != 0)
11161108 			goto done;
11171109 
11181110 		i = 0;
1119
-		while (ath10k_ce_completed_send_next_nolock(ce_diag,
1120
-							    NULL) != 0) {
1121
-			mdelay(1);
1111
+		while (ath10k_ce_completed_send_next(ce_diag, NULL) != 0) {
1112
+			udelay(DIAG_ACCESS_CE_WAIT_US);
1113
+			i += DIAG_ACCESS_CE_WAIT_US;
11221114 
1123
-			if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
1115
+			if (i > DIAG_ACCESS_CE_TIMEOUT_US) {
11241116 				ret = -EBUSY;
11251117 				goto done;
11261118 			}
11271119 		}
11281120 
11291121 		i = 0;
1130
-		while (ath10k_ce_completed_recv_next_nolock(ce_diag,
1131
-							    (void **)&buf,
1132
-							    &completed_nbytes)
1133
-								!= 0) {
1134
-			mdelay(1);
1122
+		while (ath10k_ce_completed_recv_next(ce_diag, (void **)&buf,
1123
+						     &completed_nbytes) != 0) {
1124
+			udelay(DIAG_ACCESS_CE_WAIT_US);
1125
+			i += DIAG_ACCESS_CE_WAIT_US;
11351126 
1136
-			if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
1127
+			if (i > DIAG_ACCESS_CE_TIMEOUT_US) {
11371128 				ret = -EBUSY;
11381129 				goto done;
11391130 			}
....@@ -1164,7 +1155,7 @@
11641155 		ath10k_warn(ar, "failed to write diag value at 0x%x: %d\n",
11651156 			    address, ret);
11661157 
1167
-	spin_unlock_bh(&ce->ce_lock);
1158
+	mutex_unlock(&ar_pci->ce_diag_mutex);
11681159 
11691160 	return ret;
11701161 }
....@@ -1446,7 +1437,7 @@
14461437 	__le32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {};
14471438 	int i, ret;
14481439 
1449
-	lockdep_assert_held(&ar->data_lock);
1440
+	lockdep_assert_held(&ar->dump_mutex);
14501441 
14511442 	ret = ath10k_pci_diag_read_hi(ar, &reg_dump_values[0],
14521443 				      hi_failure_state,
....@@ -1587,7 +1578,7 @@
15871578 	return 0;
15881579 }
15891580 
1590
-/* if an error happened returns < 0, otherwise the length */
1581
+/* Always returns the length */
15911582 static int ath10k_pci_dump_memory_sram(struct ath10k *ar,
15921583 				       const struct ath10k_mem_region *region,
15931584 				       u8 *buf)
....@@ -1672,7 +1663,7 @@
16721663 	int ret, i;
16731664 	u8 *buf;
16741665 
1675
-	lockdep_assert_held(&ar->data_lock);
1666
+	lockdep_assert_held(&ar->dump_mutex);
16761667 
16771668 	if (!crash_data)
16781669 		return;
....@@ -1754,14 +1745,19 @@
17541745 	}
17551746 }
17561747 
1757
-static void ath10k_pci_fw_crashed_dump(struct ath10k *ar)
1748
+static void ath10k_pci_fw_dump_work(struct work_struct *work)
17581749 {
1750
+	struct ath10k_pci *ar_pci = container_of(work, struct ath10k_pci,
1751
+						 dump_work);
17591752 	struct ath10k_fw_crash_data *crash_data;
1753
+	struct ath10k *ar = ar_pci->ar;
17601754 	char guid[UUID_STRING_LEN + 1];
17611755 
1762
-	spin_lock_bh(&ar->data_lock);
1756
+	mutex_lock(&ar->dump_mutex);
17631757 
1758
+	spin_lock_bh(&ar->data_lock);
17641759 	ar->stats.fw_crash_counter++;
1760
+	spin_unlock_bh(&ar->data_lock);
17651761 
17661762 	crash_data = ath10k_coredump_new(ar);
17671763 
....@@ -1776,14 +1772,23 @@
17761772 	ath10k_ce_dump_registers(ar, crash_data);
17771773 	ath10k_pci_dump_memory(ar, crash_data);
17781774 
1779
-	spin_unlock_bh(&ar->data_lock);
1775
+	mutex_unlock(&ar->dump_mutex);
17801776 
17811777 	queue_work(ar->workqueue, &ar->restart_work);
1778
+}
1779
+
1780
+static void ath10k_pci_fw_crashed_dump(struct ath10k *ar)
1781
+{
1782
+	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1783
+
1784
+	queue_work(ar->workqueue, &ar_pci->dump_work);
17821785 }
17831786 
17841787 void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
17851788 					int force)
17861789 {
1790
+	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1791
+
17871792 	ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif send complete check\n");
17881793 
17891794 	if (!force) {
....@@ -1801,7 +1806,7 @@
18011806 		 * If at least 50% of the total resources are still available,
18021807 		 * don't bother checking again yet.
18031808 		 */
1804
-		if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1))
1809
+		if (resources > (ar_pci->attr[pipe].src_nentries >> 1))
18051810 			return;
18061811 	}
18071812 	ath10k_ce_per_engine_service(ar, pipe);
....@@ -1817,14 +1822,15 @@
18171822 int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id,
18181823 				       u8 *ul_pipe, u8 *dl_pipe)
18191824 {
1820
-	const struct service_to_pipe *entry;
1825
+	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1826
+	const struct ce_service_to_pipe *entry;
18211827 	bool ul_set = false, dl_set = false;
18221828 	int i;
18231829 
18241830 	ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif map service\n");
18251831 
1826
-	for (i = 0; i < ARRAY_SIZE(target_service_to_ce_map_wlan); i++) {
1827
-		entry = &target_service_to_ce_map_wlan[i];
1832
+	for (i = 0; i < ARRAY_SIZE(pci_target_service_to_ce_map_wlan); i++) {
1833
+		entry = &ar_pci->serv_to_pipe[i];
18281834 
18291835 		if (__le32_to_cpu(entry->service_id) != service_id)
18301836 			continue;
....@@ -1853,7 +1859,7 @@
18531859 		}
18541860 	}
18551861 
1856
-	if (WARN_ON(!ul_set || !dl_set))
1862
+	if (!ul_set || !dl_set)
18571863 		return -ENOENT;
18581864 
18591865 	return 0;
....@@ -1957,8 +1963,9 @@
19571963 	ath10k_pci_irq_enable(ar);
19581964 	ath10k_pci_rx_post(ar);
19591965 
1960
-	pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL,
1961
-				   ar_pci->link_ctl);
1966
+	pcie_capability_clear_and_set_word(ar_pci->pdev, PCI_EXP_LNKCTL,
1967
+					   PCI_EXP_LNKCTL_ASPMC,
1968
+					   ar_pci->link_ctl & PCI_EXP_LNKCTL_ASPMC);
19621969 
19631970 	return 0;
19641971 }
....@@ -2071,6 +2078,7 @@
20712078 	ath10k_pci_irq_sync(ar);
20722079 	napi_synchronize(&ar->napi);
20732080 	napi_disable(&ar->napi);
2081
+	cancel_work_sync(&ar_pci->dump_work);
20742082 
20752083 	/* Most likely the device has HTT Rx ring configured. The only way to
20762084 	 * prevent the device from accessing (and possible corrupting) host
....@@ -2177,7 +2185,7 @@
21772185 
21782186 	if (ret == 0 && resp_len) {
21792187 		*resp_len = min(*resp_len, xfer.resp_len);
2180
-		memcpy(resp, tresp, xfer.resp_len);
2188
+		memcpy(resp, tresp, *resp_len);
21812189 	}
21822190 err_dma:
21832191 	kfree(treq);
....@@ -2281,7 +2289,7 @@
22812289 		return 1;
22822290 	case QCA6164_2_1_DEVICE_ID:
22832291 	case QCA6174_2_1_DEVICE_ID:
2284
-		switch (MS(ar->chip_id, SOC_CHIP_ID_REV)) {
2292
+		switch (MS(ar->bus_param.chip_id, SOC_CHIP_ID_REV)) {
22852293 		case QCA6174_HW_1_0_CHIP_ID_REV:
22862294 		case QCA6174_HW_1_1_CHIP_ID_REV:
22872295 		case QCA6174_HW_2_1_CHIP_ID_REV:
....@@ -2312,6 +2320,7 @@
23122320 
23132321 int ath10k_pci_init_config(struct ath10k *ar)
23142322 {
2323
+	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
23152324 	u32 interconnect_targ_addr;
23162325 	u32 pcie_state_targ_addr = 0;
23172326 	u32 pipe_cfg_targ_addr = 0;
....@@ -2357,7 +2366,7 @@
23572366 	}
23582367 
23592368 	ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr,
2360
-					target_ce_config_wlan,
2369
+					ar_pci->pipe_config,
23612370 					sizeof(struct ce_pipe_config) *
23622371 					NUM_TARGET_CE_CONFIG_WLAN);
23632372 
....@@ -2382,8 +2391,8 @@
23822391 	}
23832392 
23842393 	ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map,
2385
-					target_service_to_ce_map_wlan,
2386
-					sizeof(target_service_to_ce_map_wlan));
2394
+					ar_pci->serv_to_pipe,
2395
+					sizeof(pci_target_service_to_ce_map_wlan));
23872396 	if (ret != 0) {
23882397 		ath10k_err(ar, "Failed to write svc/pipe map: %d\n", ret);
23892398 		return ret;
....@@ -2455,23 +2464,24 @@
24552464 {
24562465 	struct ce_attr *attr;
24572466 	struct ce_pipe_config *config;
2467
+	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
24582468 
24592469 	/* For QCA6174 we're overriding the Copy Engine 5 configuration,
24602470 	 * since it is currently used for other feature.
24612471 	 */
24622472 
24632473 	/* Override Host's Copy Engine 5 configuration */
2464
-	attr = &host_ce_config_wlan[5];
2474
+	attr = &ar_pci->attr[5];
24652475 	attr->src_sz_max = 0;
24662476 	attr->dest_nentries = 0;
24672477 
24682478 	/* Override Target firmware's Copy Engine configuration */
2469
-	config = &target_ce_config_wlan[5];
2479
+	config = &ar_pci->pipe_config[5];
24702480 	config->pipedir = __cpu_to_le32(PIPEDIR_OUT);
24712481 	config->nbytes_max = __cpu_to_le32(2048);
24722482 
24732483 	/* Map from service/endpoint to Copy Engine */
2474
-	target_service_to_ce_map_wlan[15].pipenum = __cpu_to_le32(1);
2484
+	ar_pci->serv_to_pipe[15].pipenum = __cpu_to_le32(1);
24752485 }
24762486 
24772487 int ath10k_pci_alloc_pipes(struct ath10k *ar)
....@@ -2487,7 +2497,7 @@
24872497 		pipe->pipe_num = i;
24882498 		pipe->hif_ce_state = ar;
24892499 
2490
-		ret = ath10k_ce_alloc_pipe(ar, i, &host_ce_config_wlan[i]);
2500
+		ret = ath10k_ce_alloc_pipe(ar, i, &ar_pci->attr[i]);
24912501 		if (ret) {
24922502 			ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n",
24932503 				   i, ret);
....@@ -2500,7 +2510,7 @@
25002510 			continue;
25012511 		}
25022512 
2503
-		pipe->buf_sz = (size_t)(host_ce_config_wlan[i].src_sz_max);
2513
+		pipe->buf_sz = (size_t)(ar_pci->attr[i].src_sz_max);
25042514 	}
25052515 
25062516 	return 0;
....@@ -2516,10 +2526,11 @@
25162526 
25172527 int ath10k_pci_init_pipes(struct ath10k *ar)
25182528 {
2529
+	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
25192530 	int i, ret;
25202531 
25212532 	for (i = 0; i < CE_COUNT; i++) {
2522
-		ret = ath10k_ce_init_pipe(ar, i, &host_ce_config_wlan[i]);
2533
+		ret = ath10k_ce_init_pipe(ar, i, &ar_pci->attr[i]);
25232534 		if (ret) {
25242535 			ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n",
25252536 				   i, ret);
....@@ -2579,35 +2590,31 @@
25792590 
25802591 	ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0);
25812592 
2582
-	val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
2583
-				SOC_RESET_CONTROL_ADDRESS);
2584
-	ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
2585
-			   val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK);
2593
+	val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2594
+	ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
2595
+			       val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK);
25862596 }
25872597 
25882598 static void ath10k_pci_warm_reset_ce(struct ath10k *ar)
25892599 {
25902600 	u32 val;
25912601 
2592
-	val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
2593
-				SOC_RESET_CONTROL_ADDRESS);
2602
+	val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
25942603 
2595
-	ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
2596
-			   val | SOC_RESET_CONTROL_CE_RST_MASK);
2604
+	ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
2605
+			       val | SOC_RESET_CONTROL_CE_RST_MASK);
25972606 	msleep(10);
2598
-	ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
2599
-			   val & ~SOC_RESET_CONTROL_CE_RST_MASK);
2607
+	ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
2608
+			       val & ~SOC_RESET_CONTROL_CE_RST_MASK);
26002609 }
26012610 
26022611 static void ath10k_pci_warm_reset_clear_lf(struct ath10k *ar)
26032612 {
26042613 	u32 val;
26052614 
2606
-	val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
2607
-				SOC_LF_TIMER_CONTROL0_ADDRESS);
2608
-	ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS +
2609
-			   SOC_LF_TIMER_CONTROL0_ADDRESS,
2610
-			   val & ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK);
2615
+	val = ath10k_pci_soc_read32(ar, SOC_LF_TIMER_CONTROL0_ADDRESS);
2616
+	ath10k_pci_soc_write32(ar, SOC_LF_TIMER_CONTROL0_ADDRESS,
2617
+			       val & ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK);
26112618 }
26122619 
26132620 static int ath10k_pci_warm_reset(struct ath10k *ar)
....@@ -2804,7 +2811,8 @@
28042811 	return ar_pci->pci_hard_reset(ar);
28052812 }
28062813 
2807
-static int ath10k_pci_hif_power_up(struct ath10k *ar)
2814
+static int ath10k_pci_hif_power_up(struct ath10k *ar,
2815
+				   enum ath10k_firmware_mode fw_mode)
28082816 {
28092817 	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
28102818 	int ret;
....@@ -2813,8 +2821,8 @@
28132821 
28142822 	pcie_capability_read_word(ar_pci->pdev, PCI_EXP_LNKCTL,
28152823 				  &ar_pci->link_ctl);
2816
-	pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL,
2817
-				   ar_pci->link_ctl & ~PCI_EXP_LNKCTL_ASPMC);
2824
+	pcie_capability_clear_word(ar_pci->pdev, PCI_EXP_LNKCTL,
2825
+				   PCI_EXP_LNKCTL_ASPMC);
28182826 
28192827 	/*
28202828 	 * Bring the target up cleanly.
....@@ -3460,8 +3468,33 @@
34603468 
34613469 	spin_lock_init(&ce->ce_lock);
34623470 	spin_lock_init(&ar_pci->ps_lock);
3471
+	mutex_init(&ar_pci->ce_diag_mutex);
3472
+
3473
+	INIT_WORK(&ar_pci->dump_work, ath10k_pci_fw_dump_work);
34633474 
34643475 	timer_setup(&ar_pci->rx_post_retry, ath10k_pci_rx_replenish_retry, 0);
3476
+
3477
+	ar_pci->attr = kmemdup(pci_host_ce_config_wlan,
3478
+			       sizeof(pci_host_ce_config_wlan),
3479
+			       GFP_KERNEL);
3480
+	if (!ar_pci->attr)
3481
+		return -ENOMEM;
3482
+
3483
+	ar_pci->pipe_config = kmemdup(pci_target_ce_config_wlan,
3484
+				      sizeof(pci_target_ce_config_wlan),
3485
+				      GFP_KERNEL);
3486
+	if (!ar_pci->pipe_config) {
3487
+		ret = -ENOMEM;
3488
+		goto err_free_attr;
3489
+	}
3490
+
3491
+	ar_pci->serv_to_pipe = kmemdup(pci_target_service_to_ce_map_wlan,
3492
+				       sizeof(pci_target_service_to_ce_map_wlan),
3493
+				       GFP_KERNEL);
3494
+	if (!ar_pci->serv_to_pipe) {
3495
+		ret = -ENOMEM;
3496
+		goto err_free_pipe_config;
3497
+	}
34653498 
34663499 	if (QCA_REV_6174(ar) || QCA_REV_9377(ar))
34673500 		ath10k_pci_override_ce_config(ar);
....@@ -3470,18 +3503,31 @@
34703503 	if (ret) {
34713504 		ath10k_err(ar, "failed to allocate copy engine pipes: %d\n",
34723505 			   ret);
3473
-		return ret;
3506
+		goto err_free_serv_to_pipe;
34743507 	}
34753508 
34763509 	return 0;
3510
+
3511
+err_free_serv_to_pipe:
3512
+	kfree(ar_pci->serv_to_pipe);
3513
+err_free_pipe_config:
3514
+	kfree(ar_pci->pipe_config);
3515
+err_free_attr:
3516
+	kfree(ar_pci->attr);
3517
+	return ret;
34773518 }
34783519 
34793520 void ath10k_pci_release_resource(struct ath10k *ar)
34803521 {
3522
+	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3523
+
34813524 	ath10k_pci_rx_retry_sync(ar);
34823525 	netif_napi_del(&ar->napi);
34833526 	ath10k_pci_ce_deinit(ar);
34843527 	ath10k_pci_free_pipes(ar);
3528
+	kfree(ar_pci->attr);
3529
+	kfree(ar_pci->pipe_config);
3530
+	kfree(ar_pci->serv_to_pipe);
34853531 }
34863532 
34873533 static const struct ath10k_bus_ops ath10k_pci_bus_ops = {
....@@ -3497,8 +3543,8 @@
34973543 	struct ath10k *ar;
34983544 	struct ath10k_pci *ar_pci;
34993545 	enum ath10k_hw_rev hw_rev;
3500
-	u32 chip_id;
3501
-	bool pci_ps;
3546
+	struct ath10k_bus_params bus_params = {};
3547
+	bool pci_ps, is_qca988x = false;
35023548 	int (*pci_soft_reset)(struct ath10k *ar);
35033549 	int (*pci_hard_reset)(struct ath10k *ar);
35043550 	u32 (*targ_cpu_to_ce_addr)(struct ath10k *ar, u32 addr);
....@@ -3508,6 +3554,7 @@
35083554 	case QCA988X_2_0_DEVICE_ID:
35093555 		hw_rev = ATH10K_HW_QCA988X;
35103556 		pci_ps = false;
3557
+		is_qca988x = true;
35113558 		pci_soft_reset = ath10k_pci_warm_reset;
35123559 		pci_hard_reset = ath10k_pci_qca988x_chip_reset;
35133560 		targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr;
....@@ -3525,7 +3572,7 @@
35253572 		pci_ps = true;
35263573 		pci_soft_reset = ath10k_pci_warm_reset;
35273574 		pci_hard_reset = ath10k_pci_qca6174_chip_reset;
3528
-		targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr;
3575
+		targ_cpu_to_ce_addr = ath10k_pci_qca6174_targ_cpu_to_ce_addr;
35293576 		break;
35303577 	case QCA99X0_2_0_DEVICE_ID:
35313578 		hw_rev = ATH10K_HW_QCA99X0;
....@@ -3551,9 +3598,9 @@
35513598 	case QCA9377_1_0_DEVICE_ID:
35523599 		hw_rev = ATH10K_HW_QCA9377;
35533600 		pci_ps = true;
3554
-		pci_soft_reset = NULL;
3601
+		pci_soft_reset = ath10k_pci_warm_reset;
35553602 		pci_hard_reset = ath10k_pci_qca6174_chip_reset;
3556
-		targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr;
3603
+		targ_cpu_to_ce_addr = ath10k_pci_qca6174_targ_cpu_to_ce_addr;
35573604 		break;
35583605 	default:
35593606 		WARN_ON(1);
....@@ -3627,25 +3674,42 @@
36273674 		goto err_deinit_irq;
36283675 	}
36293676 
3677
+	bus_params.dev_type = ATH10K_DEV_TYPE_LL;
3678
+	bus_params.link_can_suspend = true;
3679
+	/* Read CHIP_ID before reset to catch QCA9880-AR1A v1 devices that
3680
+	 * fall off the bus during chip_reset. These chips have the same pci
3681
+	 * device id as the QCA9880 BR4A or 2R4E. So that's why the check.
3682
+	 */
3683
+	if (is_qca988x) {
3684
+		bus_params.chip_id =
3685
+			ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
3686
+		if (bus_params.chip_id != 0xffffffff) {
3687
+			if (!ath10k_pci_chip_is_supported(pdev->device,
3688
+							  bus_params.chip_id)) {
3689
+				ret = -ENODEV;
3690
+				goto err_unsupported;
3691
+			}
3692
+		}
3693
+	}
3694
+
36303695 	ret = ath10k_pci_chip_reset(ar);
36313696 	if (ret) {
36323697 		ath10k_err(ar, "failed to reset chip: %d\n", ret);
36333698 		goto err_free_irq;
36343699 	}
36353700 
3636
-	chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
3637
-	if (chip_id == 0xffffffff) {
3638
-		ath10k_err(ar, "failed to get chip id\n");
3639
-		goto err_free_irq;
3701
+	bus_params.chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
3702
+	if (bus_params.chip_id == 0xffffffff) {
3703
+		ret = -ENODEV;
3704
+		goto err_unsupported;
36403705 	}
36413706 
3642
-	if (!ath10k_pci_chip_is_supported(pdev->device, chip_id)) {
3643
-		ath10k_err(ar, "device %04x with chip_id %08x isn't supported\n",
3644
-			   pdev->device, chip_id);
3645
-		goto err_free_irq;
3707
+	if (!ath10k_pci_chip_is_supported(pdev->device, bus_params.chip_id)) {
3708
+		ret = -ENODEV;
3709
+		goto err_unsupported;
36463710 	}
36473711 
3648
-	ret = ath10k_core_register(ar, chip_id);
3712
+	ret = ath10k_core_register(ar, &bus_params);
36493713 	if (ret) {
36503714 		ath10k_err(ar, "failed to register driver core: %d\n", ret);
36513715 		goto err_free_irq;
....@@ -3653,12 +3717,15 @@
36533717 
36543718 	return 0;
36553719 
3720
+err_unsupported:
3721
+	ath10k_err(ar, "device %04x with chip_id %08x isn't supported\n",
3722
+		   pdev->device, bus_params.chip_id);
3723
+
36563724 err_free_irq:
36573725 	ath10k_pci_free_irq(ar);
3658
-	ath10k_pci_rx_retry_sync(ar);
36593726 
36603727 err_deinit_irq:
3661
-	ath10k_pci_deinit_irq(ar);
3728
+	ath10k_pci_release_resource(ar);
36623729 
36633730 err_sleep:
36643731 	ath10k_pci_sleep_sync(ar);
....@@ -3676,16 +3743,10 @@
36763743 static void ath10k_pci_remove(struct pci_dev *pdev)
36773744 {
36783745 	struct ath10k *ar = pci_get_drvdata(pdev);
3679
-	struct ath10k_pci *ar_pci;
36803746 
36813747 	ath10k_dbg(ar, ATH10K_DBG_PCI, "pci remove\n");
36823748 
36833749 	if (!ar)
3684
-		return;
3685
-
3686
-	ar_pci = ath10k_pci_priv(ar);
3687
-
3688
-	if (!ar_pci)
36893750 		return;
36903751 
36913752 	ath10k_core_unregister(ar);
....@@ -3739,18 +3800,22 @@
37393800 
37403801 static int __init ath10k_pci_init(void)
37413802 {
3742
-	int ret;
3803
+	int ret1, ret2;
37433804 
3744
-	ret = pci_register_driver(&ath10k_pci_driver);
3745
-	if (ret)
3805
+	ret1 = pci_register_driver(&ath10k_pci_driver);
3806
+	if (ret1)
37463807 		printk(KERN_ERR "failed to register ath10k pci driver: %d\n",
3747
-		       ret);
3808
+		       ret1);
37483809 
3749
-	ret = ath10k_ahb_init();
3750
-	if (ret)
3751
-		printk(KERN_ERR "ahb init failed: %d\n", ret);
3810
+	ret2 = ath10k_ahb_init();
3811
+	if (ret2)
3812
+		printk(KERN_ERR "ahb init failed: %d\n", ret2);
37523813 
3753
-	return ret;
3814
+	if (ret1 && ret2)
3815
+		return ret1;
3816
+
3817
+	/* registered to at least one bus */
3818
+	return 0;
37543819 }
37553820 module_init(ath10k_pci_init);
37563821