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2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390 
 kernel/drivers/net/wan/fsl_ucc_hdlc.c
....@@ -1,11 +1,7 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /* Freescale QUICC Engine HDLC Device Driver
23  *
34  * Copyright 2016 Freescale Semiconductor Inc.
4
- *
5
- * This program is free software; you can redistribute  it and/or modify it
6
- * under  the terms of  the GNU General  Public License as published by the
7
- * Free Software Foundation;  either version 2 of the  License, or (at your
8
- * option) any later version.
95  */
106 
117 #include <linux/delay.h>
....@@ -36,6 +32,9 @@
3632 #define DRV_NAME "ucc_hdlc"
3733 
3834 #define TDM_PPPOHT_SLIC_MAXIN
35
+#define RX_BD_ERRORS (R_CD_S | R_OV_S | R_CR_S | R_AB_S | R_NO_S | R_LG_S)
36
+
37
+static int uhdlc_close(struct net_device *dev);
3938 
4039 static struct ucc_tdm_info utdm_primary_info = {
4140 	.uf_info = {
....@@ -87,8 +86,8 @@
8786 	int ret, i;
8887 	void *bd_buffer;
8988 	dma_addr_t bd_dma_addr;
90
-	u32 riptr;
91
-	u32 tiptr;
89
+	s32 riptr;
90
+	s32 tiptr;
9291 	u32 gumr;
9392 
9493 	ut_info = priv->ut_info;
....@@ -97,6 +96,12 @@
9796 	if (priv->tsa) {
9897 		uf_info->tsa = 1;
9998 		uf_info->ctsp = 1;
99
+		uf_info->cds = 1;
100
+		uf_info->ctss = 1;
101
+	} else {
102
+		uf_info->cds = 0;
103
+		uf_info->ctsp = 0;
104
+		uf_info->ctss = 0;
100105 	}
101106 
102107 	/* This sets HPM register in CMXUCR register which configures a
....@@ -192,7 +197,7 @@
192197 	priv->ucc_pram_offset = qe_muram_alloc(sizeof(struct ucc_hdlc_param),
193198 				ALIGNMENT_OF_UCC_HDLC_PRAM);
194199 
195
-	if (IS_ERR_VALUE(priv->ucc_pram_offset)) {
200
+	if (priv->ucc_pram_offset < 0) {
196201 		dev_err(priv->dev, "Can not allocate MURAM for hdlc parameter.\n");
197202 		ret = -ENOMEM;
198203 		goto free_tx_bd;
....@@ -234,14 +239,14 @@
234239 
235240 	/* Alloc riptr, tiptr */
236241 	riptr = qe_muram_alloc(32, 32);
237
-	if (IS_ERR_VALUE(riptr)) {
242
+	if (riptr < 0) {
238243 		dev_err(priv->dev, "Cannot allocate MURAM mem for Receive internal temp data pointer\n");
239244 		ret = -ENOMEM;
240245 		goto free_tx_skbuff;
241246 	}
242247 
243248 	tiptr = qe_muram_alloc(32, 32);
244
-	if (IS_ERR_VALUE(tiptr)) {
249
+	if (tiptr < 0) {
245250 		dev_err(priv->dev, "Cannot allocate MURAM mem for Transmit internal temp data pointer\n");
246251 		ret = -ENOMEM;
247252 		goto free_riptr;
....@@ -274,17 +279,16 @@
274279 	iowrite16be(MAX_FRAME_LENGTH, &priv->ucc_pram->mflr);
275280 	iowrite16be(DEFAULT_RFTHR, &priv->ucc_pram->rfthr);
276281 	iowrite16be(DEFAULT_RFTHR, &priv->ucc_pram->rfcnt);
277
-	iowrite16be(DEFAULT_ADDR_MASK, &priv->ucc_pram->hmask);
282
+	iowrite16be(priv->hmask, &priv->ucc_pram->hmask);
278283 	iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr1);
279284 	iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr2);
280285 	iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr3);
281286 	iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr4);
282287 
283288 	/* Get BD buffer */
284
-	bd_buffer = dma_zalloc_coherent(priv->dev,
285
-					(RX_BD_RING_LEN + TX_BD_RING_LEN) *
286
-					MAX_RX_BUF_LENGTH,
287
-					&bd_dma_addr, GFP_KERNEL);
289
+	bd_buffer = dma_alloc_coherent(priv->dev,
290
+				       (RX_BD_RING_LEN + TX_BD_RING_LEN) * MAX_RX_BUF_LENGTH,
291
+				       &bd_dma_addr, GFP_KERNEL);
288292 
289293 	if (!bd_buffer) {
290294 		dev_err(priv->dev, "Could not allocate buffer descriptors\n");
....@@ -384,11 +388,16 @@
384388 		dev->stats.tx_bytes += skb->len;
385389 		break;
386390 
391
+	case ARPHRD_ETHER:
392
+		dev->stats.tx_bytes += skb->len;
393
+		break;
394
+
387395 	default:
388396 		dev->stats.tx_dropped++;
389397 		dev_kfree_skb(skb);
390398 		return -ENOMEM;
391399 	}
400
+	netdev_sent_queue(dev, skb->len);
392401 	spin_lock_irqsave(&priv->lock, flags);
393402 
394403 	/* Start from the next BD that should be filled */
....@@ -429,12 +438,27 @@
429438 	return NETDEV_TX_OK;
430439 }
431440 
441
+static int hdlc_tx_restart(struct ucc_hdlc_private *priv)
442
+{
443
+	u32 cecr_subblock;
444
+
445
+	cecr_subblock =
446
+		ucc_fast_get_qe_cr_subblock(priv->ut_info->uf_info.ucc_num);
447
+
448
+	qe_issue_cmd(QE_RESTART_TX, cecr_subblock,
449
+		     QE_CR_PROTOCOL_UNSPECIFIED, 0);
450
+	return 0;
451
+}
452
+
432453 static int hdlc_tx_done(struct ucc_hdlc_private *priv)
433454 {
434455 	/* Start from the next BD that should be filled */
435456 	struct net_device *dev = priv->ndev;
457
+	unsigned int bytes_sent = 0;
458
+	int howmany = 0;
436459 	struct qe_bd *bd;		/* BD pointer */
437460 	u16 bd_status;
461
+	int tx_restart = 0;
438462 
439463 	bd = priv->dirty_tx;
440464 	bd_status = ioread16be(&bd->status);
....@@ -443,6 +467,15 @@
443467 	while ((bd_status & T_R_S) == 0) {
444468 		struct sk_buff *skb;
445469 
470
+		if (bd_status & T_UN_S) { /* Underrun */
471
+			dev->stats.tx_fifo_errors++;
472
+			tx_restart = 1;
473
+		}
474
+		if (bd_status & T_CT_S) { /* Carrier lost */
475
+			dev->stats.tx_carrier_errors++;
476
+			tx_restart = 1;
477
+		}
478
+
446479 		/* BD contains already transmitted buffer.   */
447480 		/* Handle the transmitted buffer and release */
448481 		/* the BD to be used with the current frame  */
....@@ -450,11 +483,13 @@
450483 		skb = priv->tx_skbuff[priv->skb_dirtytx];
451484 		if (!skb)
452485 			break;
486
+		howmany++;
487
+		bytes_sent += skb->len;
453488 		dev->stats.tx_packets++;
454489 		memset(priv->tx_buffer +
455490 		       (be32_to_cpu(bd->buf) - priv->dma_tx_addr),
456491 		       0, skb->len);
457
-		dev_kfree_skb_irq(skb);
492
+		dev_consume_skb_irq(skb);
458493 
459494 		priv->tx_skbuff[priv->skb_dirtytx] = NULL;
460495 		priv->skb_dirtytx =
....@@ -474,6 +509,10 @@
474509 	}
475510 	priv->dirty_tx = bd;
476511 
512
+	if (tx_restart)
513
+		hdlc_tx_restart(priv);
514
+
515
+	netdev_completed_queue(dev, howmany, bytes_sent);
477516 	return 0;
478517 }
479518 
....@@ -492,11 +531,22 @@
492531 
493532 	/* while there are received buffers and BD is full (~R_E) */
494533 	while (!((bd_status & (R_E_S)) || (--rx_work_limit < 0))) {
495
-		if (bd_status & R_OV_S)
496
-			dev->stats.rx_over_errors++;
497
-		if (bd_status & R_CR_S) {
498
-			dev->stats.rx_crc_errors++;
499
-			dev->stats.rx_dropped++;
534
+		if (bd_status & (RX_BD_ERRORS)) {
535
+			dev->stats.rx_errors++;
536
+
537
+			if (bd_status & R_CD_S)
538
+				dev->stats.collisions++;
539
+			if (bd_status & R_OV_S)
540
+				dev->stats.rx_fifo_errors++;
541
+			if (bd_status & R_CR_S)
542
+				dev->stats.rx_crc_errors++;
543
+			if (bd_status & R_AB_S)
544
+				dev->stats.rx_over_errors++;
545
+			if (bd_status & R_NO_S)
546
+				dev->stats.rx_frame_errors++;
547
+			if (bd_status & R_LG_S)
548
+				dev->stats.rx_length_errors++;
549
+
500550 			goto recycle;
501551 		}
502552 		bdbuffer = priv->rx_buffer +
....@@ -521,6 +571,7 @@
521571 			break;
522572 
523573 		case ARPHRD_PPP:
574
+		case ARPHRD_ETHER:
524575 			length -= HDLC_CRC_SIZE;
525576 
526577 			skb = dev_alloc_skb(length);
....@@ -544,7 +595,7 @@
544595 		netif_receive_skb(skb);
545596 
546597 recycle:
547
-		iowrite16be(bd_status | R_E_S | R_I_S, &bd->status);
598
+		iowrite16be((bd_status & R_W_S) | R_E_S | R_I_S, &bd->status);
548599 
549600 		/* update to point at the next bd */
550601 		if (bd_status & R_W_S) {
....@@ -583,8 +634,8 @@
583634 
584635 	if (howmany < budget) {
585636 		napi_complete_done(napi, howmany);
586
-		qe_setbits32(priv->uccf->p_uccm,
587
-			     (UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS) << 16);
637
+		qe_setbits_be32(priv->uccf->p_uccm,
638
+				(UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS) << 16);
588639 	}
589640 
590641 	return howmany;
....@@ -595,11 +646,9 @@
595646 	struct ucc_hdlc_private *priv = (struct ucc_hdlc_private *)dev_id;
596647 	struct net_device *dev = priv->ndev;
597648 	struct ucc_fast_private *uccf;
598
-	struct ucc_tdm_info *ut_info;
599649 	u32 ucce;
600650 	u32 uccm;
601651 
602
-	ut_info = priv->ut_info;
603652 	uccf = priv->uccf;
604653 
605654 	ucce = ioread32be(uccf->p_ucce);
....@@ -620,7 +669,7 @@
620669 
621670 	/* Errors and other events */
622671 	if (ucce >> 16 & UCC_HDLC_UCCE_BSY)
623
-		dev->stats.rx_errors++;
672
+		dev->stats.rx_missed_errors++;
624673 	if (ucce >> 16 & UCC_HDLC_UCCE_TXE)
625674 		dev->stats.tx_errors++;
626675 
....@@ -661,6 +710,7 @@
661710 	hdlc_device *hdlc = dev_to_hdlc(dev);
662711 	struct ucc_hdlc_private *priv = hdlc->priv;
663712 	struct ucc_tdm *utdm = priv->utdm;
713
+	int rc = 0;
664714 
665715 	if (priv->hdlc_busy != 1) {
666716 		if (request_irq(priv->ut_info->uf_info.irq,
....@@ -682,17 +732,21 @@
682732 		priv->hdlc_busy = 1;
683733 		netif_device_attach(priv->ndev);
684734 		napi_enable(&priv->napi);
735
+		netdev_reset_queue(dev);
685736 		netif_start_queue(dev);
686
-		hdlc_open(dev);
737
+
738
+		rc = hdlc_open(dev);
739
+		if (rc)
740
+			uhdlc_close(dev);
687741 	}
688742 
689
-	return 0;
743
+	return rc;
690744 }
691745 
692746 static void uhdlc_memclean(struct ucc_hdlc_private *priv)
693747 {
694
-	qe_muram_free(priv->ucc_pram->riptr);
695
-	qe_muram_free(priv->ucc_pram->tiptr);
748
+	qe_muram_free(ioread16be(&priv->ucc_pram->riptr));
749
+	qe_muram_free(ioread16be(&priv->ucc_pram->tiptr));
696750 
697751 	if (priv->rx_bd_base) {
698752 		dma_free_coherent(priv->dev,
....@@ -773,7 +827,10 @@
773827 
774828 	free_irq(priv->ut_info->uf_info.irq, priv);
775829 	netif_stop_queue(dev);
830
+	netdev_reset_queue(dev);
776831 	priv->hdlc_busy = 0;
832
+
833
+	hdlc_close(dev);
777834 
778835 	return 0;
779836 }
....@@ -789,6 +846,7 @@
789846 
790847 	if (parity != PARITY_NONE &&
791848 	    parity != PARITY_CRC32_PR1_CCITT &&
849
+	    parity != PARITY_CRC16_PR0_CCITT &&
792850 	    parity != PARITY_CRC16_PR1_CCITT)
793851 		return -EINVAL;
794852 
....@@ -829,7 +887,6 @@
829887 static int uhdlc_suspend(struct device *dev)
830888 {
831889 	struct ucc_hdlc_private *priv = dev_get_drvdata(dev);
832
-	struct ucc_tdm_info *ut_info;
833890 	struct ucc_fast __iomem *uf_regs;
834891 
835892 	if (!priv)
....@@ -841,7 +898,6 @@
841898 	netif_device_detach(priv->ndev);
842899 	napi_disable(&priv->napi);
843900 
844
-	ut_info = priv->ut_info;
845901 	uf_regs = priv->uf_regs;
846902 
847903 	/* backup gumr guemr*/
....@@ -874,7 +930,7 @@
874930 	struct ucc_fast __iomem *uf_regs;
875931 	struct ucc_fast_private *uccf;
876932 	struct ucc_fast_info *uf_info;
877
-	int ret, i;
933
+	int i;
878934 	u32 cecr_subblock;
879935 	u16 bd_status;
880936 
....@@ -919,16 +975,16 @@
919975 
920976 	/* Write to QE CECR, UCCx channel to Stop Transmission */
921977 	cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
922
-	ret = qe_issue_cmd(QE_STOP_TX, cecr_subblock,
923
-			   (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
978
+	qe_issue_cmd(QE_STOP_TX, cecr_subblock,
979
+		     (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
924980 
925981 	/* Set UPSMR normal mode */
926982 	iowrite32be(0, &uf_regs->upsmr);
927983 
928984 	/* init parameter base */
929985 	cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
930
-	ret = qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, cecr_subblock,
931
-			   QE_CR_PROTOCOL_UNSPECIFIED, priv->ucc_pram_offset);
986
+	qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, cecr_subblock,
987
+		     QE_CR_PROTOCOL_UNSPECIFIED, priv->ucc_pram_offset);
932988 
933989 	priv->ucc_pram = (struct ucc_hdlc_param __iomem *)
934990 				qe_muram_addr(priv->ucc_pram_offset);
....@@ -996,12 +1052,66 @@
9961052 #define HDLC_PM_OPS NULL
9971053 
9981054 #endif
1055
+static void uhdlc_tx_timeout(struct net_device *ndev, unsigned int txqueue)
1056
+{
1057
+	netdev_err(ndev, "%s\n", __func__);
1058
+}
1059
+
9991060 static const struct net_device_ops uhdlc_ops = {
10001061 	.ndo_open       = uhdlc_open,
10011062 	.ndo_stop       = uhdlc_close,
10021063 	.ndo_start_xmit = hdlc_start_xmit,
10031064 	.ndo_do_ioctl   = uhdlc_ioctl,
1065
+	.ndo_tx_timeout	= uhdlc_tx_timeout,
10041066 };
1067
+
1068
+static int hdlc_map_iomem(char *name, int init_flag, void __iomem **ptr)
1069
+{
1070
+	struct device_node *np;
1071
+	struct platform_device *pdev;
1072
+	struct resource *res;
1073
+	static int siram_init_flag;
1074
+	int ret = 0;
1075
+
1076
+	np = of_find_compatible_node(NULL, NULL, name);
1077
+	if (!np)
1078
+		return -EINVAL;
1079
+
1080
+	pdev = of_find_device_by_node(np);
1081
+	if (!pdev) {
1082
+		pr_err("%pOFn: failed to lookup pdev\n", np);
1083
+		of_node_put(np);
1084
+		return -EINVAL;
1085
+	}
1086
+
1087
+	of_node_put(np);
1088
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1089
+	if (!res) {
1090
+		ret = -EINVAL;
1091
+		goto error_put_device;
1092
+	}
1093
+	*ptr = ioremap(res->start, resource_size(res));
1094
+	if (!*ptr) {
1095
+		ret = -ENOMEM;
1096
+		goto error_put_device;
1097
+	}
1098
+
1099
+	/* We've remapped the addresses, and we don't need the device any
1100
+	 * more, so we should release it.
1101
+	 */
1102
+	put_device(&pdev->dev);
1103
+
1104
+	if (init_flag && siram_init_flag == 0) {
1105
+		memset_io(*ptr, 0, resource_size(res));
1106
+		siram_init_flag = 1;
1107
+	}
1108
+	return  0;
1109
+
1110
+error_put_device:
1111
+	put_device(&pdev->dev);
1112
+
1113
+	return ret;
1114
+}
10051115 
10061116 static int ucc_hdlc_probe(struct platform_device *pdev)
10071117 {
....@@ -1024,7 +1134,7 @@
10241134 	}
10251135 
10261136 	ucc_num = val - 1;
1027
-	if ((ucc_num > 3) || (ucc_num < 0)) {
1137
+	if (ucc_num > (UCC_MAX_NUM - 1) || ucc_num < 0) {
10281138 		dev_err(&pdev->dev, ": Invalid UCC num\n");
10291139 		return -EINVAL;
10301140 	}
....@@ -1097,12 +1207,24 @@
10971207 		ret = ucc_of_parse_tdm(np, utdm, ut_info);
10981208 		if (ret)
10991209 			goto free_utdm;
1210
+
1211
+		ret = hdlc_map_iomem("fsl,t1040-qe-si", 0,
1212
+				     (void __iomem **)&utdm->si_regs);
1213
+		if (ret)
1214
+			goto free_utdm;
1215
+		ret = hdlc_map_iomem("fsl,t1040-qe-siram", 1,
1216
+				     (void __iomem **)&utdm->siram);
1217
+		if (ret)
1218
+			goto unmap_si_regs;
11001219 	}
1220
+
1221
+	if (of_property_read_u16(np, "fsl,hmask", &uhdlc_priv->hmask))
1222
+		uhdlc_priv->hmask = DEFAULT_ADDR_MASK;
11011223 
11021224 	ret = uhdlc_init(uhdlc_priv);
11031225 	if (ret) {
11041226 		dev_err(&pdev->dev, "Failed to init uhdlc\n");
1105
-		goto free_utdm;
1227
+		goto undo_uhdlc_init;
11061228 	}
11071229 
11081230 	dev = alloc_hdlcdev(uhdlc_priv);
....@@ -1116,6 +1238,7 @@
11161238 	hdlc = dev_to_hdlc(dev);
11171239 	dev->tx_queue_len = 16;
11181240 	dev->netdev_ops = &uhdlc_ops;
1241
+	dev->watchdog_timeo = 2 * HZ;
11191242 	hdlc->attach = ucc_hdlc_attach;
11201243 	hdlc->xmit = ucc_hdlc_tx;
11211244 	netif_napi_add(dev, &uhdlc_priv->napi, ucc_hdlc_poll, 32);
....@@ -1130,6 +1253,11 @@
11301253 free_dev:
11311254 	free_netdev(dev);
11321255 undo_uhdlc_init:
1256
+	if (utdm)
1257
+		iounmap(utdm->siram);
1258
+unmap_si_regs:
1259
+	if (utdm)
1260
+		iounmap(utdm->si_regs);
11331261 free_utdm:
11341262 	if (uhdlc_priv->tsa)
11351263 		kfree(utdm);
....@@ -1181,3 +1309,4 @@
11811309 
11821310 module_platform_driver(ucc_hdlc_driver);
11831311 MODULE_LICENSE("GPL");
1312
+MODULE_DESCRIPTION(DRV_DESC);