~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,3 +1,4 @@
	1	+// SPDX-License-Identifier: GPL-2.0+
1	2	/*
2	3	* drivers/net/phy/micrel.c
3	4	*
..	..	@@ -8,13 +9,8 @@
8	9	* Copyright (c) 2010-2013 Micrel, Inc.
9	10	* Copyright (c) 2014 Johan Hovold <johan@kernel.org>
10	11	*
11		- * This program is free software; you can redistribute it and/or modify it
12		- * under the terms of the GNU General Public License as published by the
13		- * Free Software Foundation; either version 2 of the License, or (at your
14		- * option) any later version.
15		- *
16	12	* Support : Micrel Phys:
17		- * Giga phys: ksz9021, ksz9031
	13	+ * Giga phys: ksz9021, ksz9031, ksz9131
18	14	* 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
19	15	* ksz8021, ksz8031, ksz8051,
20	16	* ksz8081, ksz8091,
..	..	@@ -23,6 +19,7 @@
23	19	* ksz9477
24	20	*/
25	21
	22	+#include <linux/bitfield.h>
26	23	#include <linux/kernel.h>
27	24	#include <linux/module.h>
28	25	#include <linux/phy.h>
..	..	@@ -33,6 +30,7 @@
33	30
34	31	/* Operation Mode Strap Override */
35	32	#define MII_KSZPHY_OMSO 0x16
	33	+#define KSZPHY_OMSO_FACTORY_TEST BIT(15)
36	34	#define KSZPHY_OMSO_B_CAST_OFF BIT(9)
37	35	#define KSZPHY_OMSO_NAND_TREE_ON BIT(5)
38	36	#define KSZPHY_OMSO_RMII_OVERRIDE BIT(1)
..	..	@@ -285,7 +283,7 @@
285	283	}
286	284	}
287	285
288		- if (priv->led_mode >= 0)
	286	+ if (priv->type && priv->led_mode >= 0)
289	287	kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode);
290	288
291	289	return 0;
..	..	@@ -301,28 +299,38 @@
301	299
302	300	type = priv->type;
303	301
304		- if (type->has_broadcast_disable)
	302	+ if (type && type->has_broadcast_disable)
305	303	kszphy_broadcast_disable(phydev);
306	304
307		- if (type->has_nand_tree_disable)
	305	+ if (type && type->has_nand_tree_disable)
308	306	kszphy_nand_tree_disable(phydev);
309	307
310	308	return kszphy_config_reset(phydev);
311	309	}
312	310
313		-static int ksz8041_config_init(struct phy_device *phydev)
	311	+static int ksz8041_fiber_mode(struct phy_device *phydev)
314	312	{
315	313	struct device_node *of_node = phydev->mdio.dev.of_node;
316	314
	315	+ return of_property_read_bool(of_node, "micrel,fiber-mode");
	316	+}
	317	+
	318	+static int ksz8041_config_init(struct phy_device *phydev)
	319	+{
	320	+ __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
	321	+
317	322	/* Limit supported and advertised modes in fiber mode */
318		- if (of_property_read_bool(of_node, "micrel,fiber-mode")) {
	323	+ if (ksz8041_fiber_mode(phydev)) {
319	324	phydev->dev_flags \|= MICREL_PHY_FXEN;
320		- phydev->supported &= SUPPORTED_100baseT_Full \|
321		- SUPPORTED_100baseT_Half;
322		- phydev->supported \|= SUPPORTED_FIBRE;
323		- phydev->advertising &= ADVERTISED_100baseT_Full \|
324		- ADVERTISED_100baseT_Half;
325		- phydev->advertising \|= ADVERTISED_FIBRE;
	325	+ linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask);
	326	+ linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask);
	327	+
	328	+ linkmode_and(phydev->supported, phydev->supported, mask);
	329	+ linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
	330	+ phydev->supported);
	331	+ linkmode_and(phydev->advertising, phydev->advertising, mask);
	332	+ linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
	333	+ phydev->advertising);
326	334	phydev->autoneg = AUTONEG_DISABLE;
327	335	}
328	336
..	..	@@ -340,6 +348,47 @@
340	348	return genphy_config_aneg(phydev);
341	349	}
342	350
	351	+static int ksz8051_ksz8795_match_phy_device(struct phy_device *phydev,
	352	+ const bool ksz_8051)
	353	+{
	354	+ int ret;
	355	+
	356	+ if ((phydev->phy_id & MICREL_PHY_ID_MASK) != PHY_ID_KSZ8051)
	357	+ return 0;
	358	+
	359	+ ret = phy_read(phydev, MII_BMSR);
	360	+ if (ret < 0)
	361	+ return ret;
	362	+
	363	+ /* KSZ8051 PHY and KSZ8794/KSZ8795/KSZ8765 switch share the same
	364	+ * exact PHY ID. However, they can be told apart by the extended
	365	+ * capability registers presence. The KSZ8051 PHY has them while
	366	+ * the switch does not.
	367	+ */
	368	+ ret &= BMSR_ERCAP;
	369	+ if (ksz_8051)
	370	+ return ret;
	371	+ else
	372	+ return !ret;
	373	+}
	374	+
	375	+static int ksz8051_match_phy_device(struct phy_device *phydev)
	376	+{
	377	+ return ksz8051_ksz8795_match_phy_device(phydev, true);
	378	+}
	379	+
	380	+static int ksz8081_config_init(struct phy_device *phydev)
	381	+{
	382	+ /* KSZPHY_OMSO_FACTORY_TEST is set at de-assertion of the reset line
	383	+ * based on the RXER (KSZ8081RNA/RND) or TXC (KSZ8081MNX/RNB) pin. If a
	384	+ * pull-down is missing, the factory test mode should be cleared by
	385	+ * manually writing a 0.
	386	+ */
	387	+ phy_clear_bits(phydev, MII_KSZPHY_OMSO, KSZPHY_OMSO_FACTORY_TEST);
	388	+
	389	+ return kszphy_config_init(phydev);
	390	+}
	391	+
343	392	static int ksz8061_config_init(struct phy_device *phydev)
344	393	{
345	394	int ret;
..	..	@@ -349,6 +398,11 @@
349	398	return ret;
350	399
351	400	return kszphy_config_init(phydev);
	401	+}
	402	+
	403	+static int ksz8795_match_phy_device(struct phy_device *phydev)
	404	+{
	405	+ return ksz8051_ksz8795_match_phy_device(phydev, false);
352	406	}
353	407
354	408	static int ksz9021_load_values_from_of(struct phy_device *phydev,
..	..	@@ -433,9 +487,6 @@
433	487	return 0;
434	488	}
435	489
436		-#define MII_KSZ9031RN_MMD_CTRL_REG 0x0d
437		-#define MII_KSZ9031RN_MMD_REGDATA_REG 0x0e
438		-#define OP_DATA 1
439	490	#define KSZ9031_PS_TO_REG 60
440	491
441	492	/* Extended registers */
..	..	@@ -445,36 +496,60 @@
445	496
446	497	/* MMD Address 0x2 */
447	498	#define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
	499	+#define MII_KSZ9031RN_RX_CTL_M GENMASK(7, 4)
	500	+#define MII_KSZ9031RN_TX_CTL_M GENMASK(3, 0)
	501	+
448	502	#define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
	503	+#define MII_KSZ9031RN_RXD3 GENMASK(15, 12)
	504	+#define MII_KSZ9031RN_RXD2 GENMASK(11, 8)
	505	+#define MII_KSZ9031RN_RXD1 GENMASK(7, 4)
	506	+#define MII_KSZ9031RN_RXD0 GENMASK(3, 0)
	507	+
449	508	#define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
	509	+#define MII_KSZ9031RN_TXD3 GENMASK(15, 12)
	510	+#define MII_KSZ9031RN_TXD2 GENMASK(11, 8)
	511	+#define MII_KSZ9031RN_TXD1 GENMASK(7, 4)
	512	+#define MII_KSZ9031RN_TXD0 GENMASK(3, 0)
	513	+
450	514	#define MII_KSZ9031RN_CLK_PAD_SKEW 8
	515	+#define MII_KSZ9031RN_GTX_CLK GENMASK(9, 5)
	516	+#define MII_KSZ9031RN_RX_CLK GENMASK(4, 0)
	517	+
	518	+/* KSZ9031 has internal RGMII_IDRX = 1.2ns and RGMII_IDTX = 0ns. To
	519	+ * provide different RGMII options we need to configure delay offset
	520	+ * for each pad relative to build in delay.
	521	+ */
	522	+/* keep rx as "No delay adjustment" and set rx_clk to +0.60ns to get delays of
	523	+ * 1.80ns
	524	+ */
	525	+#define RX_ID 0x7
	526	+#define RX_CLK_ID 0x19
	527	+
	528	+/* set rx to +0.30ns and rx_clk to -0.90ns to compensate the
	529	+ * internal 1.2ns delay.
	530	+ */
	531	+#define RX_ND 0xc
	532	+#define RX_CLK_ND 0x0
	533	+
	534	+/* set tx to -0.42ns and tx_clk to +0.96ns to get 1.38ns delay */
	535	+#define TX_ID 0x0
	536	+#define TX_CLK_ID 0x1f
	537	+
	538	+/* set tx and tx_clk to "No delay adjustment" to keep 0ns
	539	+ * dealy
	540	+ */
	541	+#define TX_ND 0x7
	542	+#define TX_CLK_ND 0xf
451	543
452	544	/* MMD Address 0x1C */
453	545	#define MII_KSZ9031RN_EDPD 0x23
454	546	#define MII_KSZ9031RN_EDPD_ENABLE BIT(0)
455	547
456		-static int ksz9031_extended_write(struct phy_device *phydev,
457		- u8 mode, u32 dev_addr, u32 regnum, u16 val)
458		-{
459		- phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
460		- phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
461		- phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) \| dev_addr);
462		- return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val);
463		-}
464		-
465		-static int ksz9031_extended_read(struct phy_device *phydev,
466		- u8 mode, u32 dev_addr, u32 regnum)
467		-{
468		- phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
469		- phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
470		- phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) \| dev_addr);
471		- return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG);
472		-}
473		-
474	548	static int ksz9031_of_load_skew_values(struct phy_device *phydev,
475	549	const struct device_node *of_node,
476	550	u16 reg, size_t field_sz,
477		- const char *field[], u8 numfields)
	551	+ const char *field[], u8 numfields,
	552	+ bool *update)
478	553	{
479	554	int val[4] = {-1, -2, -3, -4};
480	555	int matches = 0;
..	..	@@ -490,8 +565,10 @@
490	565	if (!matches)
491	566	return 0;
492	567
	568	+ *update \|= true;
	569	+
493	570	if (matches < numfields)
494		- newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg);
	571	+ newval = phy_read_mmd(phydev, 2, reg);
495	572	else
496	573	newval = 0;
497	574
..	..	@@ -505,7 +582,7 @@
505	582	<< (field_sz * i));
506	583	}
507	584
508		- return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
	585	+ return phy_write_mmd(phydev, 2, reg, newval);
509	586	}
510	587
511	588	/* Center KSZ9031RNX FLP timing at 16ms. */
..	..	@@ -513,13 +590,13 @@
513	590	{
514	591	int result;
515	592
516		- result = ksz9031_extended_write(phydev, OP_DATA, 0,
517		- MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006);
	593	+ result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_HI,
	594	+ 0x0006);
518	595	if (result)
519	596	return result;
520	597
521		- result = ksz9031_extended_write(phydev, OP_DATA, 0,
522		- MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80);
	598	+ result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_LO,
	599	+ 0x1A80);
523	600	if (result)
524	601	return result;
525	602
..	..	@@ -531,11 +608,72 @@
531	608	{
532	609	int reg;
533	610
534		- reg = ksz9031_extended_read(phydev, OP_DATA, 0x1C, MII_KSZ9031RN_EDPD);
	611	+ reg = phy_read_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD);
535	612	if (reg < 0)
536	613	return reg;
537		- return ksz9031_extended_write(phydev, OP_DATA, 0x1C, MII_KSZ9031RN_EDPD,
538		- reg \| MII_KSZ9031RN_EDPD_ENABLE);
	614	+ return phy_write_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD,
	615	+ reg \| MII_KSZ9031RN_EDPD_ENABLE);
	616	+}
	617	+
	618	+static int ksz9031_config_rgmii_delay(struct phy_device *phydev)
	619	+{
	620	+ u16 rx, tx, rx_clk, tx_clk;
	621	+ int ret;
	622	+
	623	+ switch (phydev->interface) {
	624	+ case PHY_INTERFACE_MODE_RGMII:
	625	+ tx = TX_ND;
	626	+ tx_clk = TX_CLK_ND;
	627	+ rx = RX_ND;
	628	+ rx_clk = RX_CLK_ND;
	629	+ break;
	630	+ case PHY_INTERFACE_MODE_RGMII_ID:
	631	+ tx = TX_ID;
	632	+ tx_clk = TX_CLK_ID;
	633	+ rx = RX_ID;
	634	+ rx_clk = RX_CLK_ID;
	635	+ break;
	636	+ case PHY_INTERFACE_MODE_RGMII_RXID:
	637	+ tx = TX_ND;
	638	+ tx_clk = TX_CLK_ND;
	639	+ rx = RX_ID;
	640	+ rx_clk = RX_CLK_ID;
	641	+ break;
	642	+ case PHY_INTERFACE_MODE_RGMII_TXID:
	643	+ tx = TX_ID;
	644	+ tx_clk = TX_CLK_ID;
	645	+ rx = RX_ND;
	646	+ rx_clk = RX_CLK_ND;
	647	+ break;
	648	+ default:
	649	+ return 0;
	650	+ }
	651	+
	652	+ ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_CONTROL_PAD_SKEW,
	653	+ FIELD_PREP(MII_KSZ9031RN_RX_CTL_M, rx) \|
	654	+ FIELD_PREP(MII_KSZ9031RN_TX_CTL_M, tx));
	655	+ if (ret < 0)
	656	+ return ret;
	657	+
	658	+ ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_RX_DATA_PAD_SKEW,
	659	+ FIELD_PREP(MII_KSZ9031RN_RXD3, rx) \|
	660	+ FIELD_PREP(MII_KSZ9031RN_RXD2, rx) \|
	661	+ FIELD_PREP(MII_KSZ9031RN_RXD1, rx) \|
	662	+ FIELD_PREP(MII_KSZ9031RN_RXD0, rx));
	663	+ if (ret < 0)
	664	+ return ret;
	665	+
	666	+ ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_TX_DATA_PAD_SKEW,
	667	+ FIELD_PREP(MII_KSZ9031RN_TXD3, tx) \|
	668	+ FIELD_PREP(MII_KSZ9031RN_TXD2, tx) \|
	669	+ FIELD_PREP(MII_KSZ9031RN_TXD1, tx) \|
	670	+ FIELD_PREP(MII_KSZ9031RN_TXD0, tx));
	671	+ if (ret < 0)
	672	+ return ret;
	673	+
	674	+ return phy_write_mmd(phydev, 2, MII_KSZ9031RN_CLK_PAD_SKEW,
	675	+ FIELD_PREP(MII_KSZ9031RN_GTX_CLK, tx_clk) \|
	676	+ FIELD_PREP(MII_KSZ9031RN_RX_CLK, rx_clk));
539	677	}
540	678
541	679	static int ksz9031_config_init(struct phy_device *phydev)
..	..	@@ -570,21 +708,33 @@
570	708	} while (!of_node && dev_walker);
571	709
572	710	if (of_node) {
	711	+ bool update = false;
	712	+
	713	+ if (phy_interface_is_rgmii(phydev)) {
	714	+ result = ksz9031_config_rgmii_delay(phydev);
	715	+ if (result < 0)
	716	+ return result;
	717	+ }
	718	+
573	719	ksz9031_of_load_skew_values(phydev, of_node,
574	720	MII_KSZ9031RN_CLK_PAD_SKEW, 5,
575		- clk_skews, 2);
	721	+ clk_skews, 2, &update);
576	722
577	723	ksz9031_of_load_skew_values(phydev, of_node,
578	724	MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
579		- control_skews, 2);
	725	+ control_skews, 2, &update);
580	726
581	727	ksz9031_of_load_skew_values(phydev, of_node,
582	728	MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
583		- rx_data_skews, 4);
	729	+ rx_data_skews, 4, &update);
584	730
585	731	ksz9031_of_load_skew_values(phydev, of_node,
586	732	MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
587		- tx_data_skews, 4);
	733	+ tx_data_skews, 4, &update);
	734	+
	735	+ if (update && !phy_interface_is_rgmii(phydev))
	736	+ phydev_warn(phydev,
	737	+ "*-skew-ps values should be used only with RGMII PHY modes\n");
588	738
589	739	/* Silicon Errata Sheet (DS80000691D or DS80000692D):
590	740	* When the device links in the 1000BASE-T slave mode only,
..	..	@@ -621,6 +771,166 @@
621	771	return result;
622	772	}
623	773
	774	+#define KSZ9131_SKEW_5BIT_MAX 2400
	775	+#define KSZ9131_SKEW_4BIT_MAX 800
	776	+#define KSZ9131_OFFSET 700
	777	+#define KSZ9131_STEP 100
	778	+
	779	+static int ksz9131_of_load_skew_values(struct phy_device *phydev,
	780	+ struct device_node *of_node,
	781	+ u16 reg, size_t field_sz,
	782	+ char *field[], u8 numfields)
	783	+{
	784	+ int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET),
	785	+ -(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)};
	786	+ int skewval, skewmax = 0;
	787	+ int matches = 0;
	788	+ u16 maxval;
	789	+ u16 newval;
	790	+ u16 mask;
	791	+ int i;
	792	+
	793	+ /* psec properties in dts should mean x pico seconds */
	794	+ if (field_sz == 5)
	795	+ skewmax = KSZ9131_SKEW_5BIT_MAX;
	796	+ else
	797	+ skewmax = KSZ9131_SKEW_4BIT_MAX;
	798	+
	799	+ for (i = 0; i < numfields; i++)
	800	+ if (!of_property_read_s32(of_node, field[i], &skewval)) {
	801	+ if (skewval < -KSZ9131_OFFSET)
	802	+ skewval = -KSZ9131_OFFSET;
	803	+ else if (skewval > skewmax)
	804	+ skewval = skewmax;
	805	+
	806	+ val[i] = skewval + KSZ9131_OFFSET;
	807	+ matches++;
	808	+ }
	809	+
	810	+ if (!matches)
	811	+ return 0;
	812	+
	813	+ if (matches < numfields)
	814	+ newval = phy_read_mmd(phydev, 2, reg);
	815	+ else
	816	+ newval = 0;
	817	+
	818	+ maxval = (field_sz == 4) ? 0xf : 0x1f;
	819	+ for (i = 0; i < numfields; i++)
	820	+ if (val[i] != -(i + 1 + KSZ9131_OFFSET)) {
	821	+ mask = 0xffff;
	822	+ mask ^= maxval << (field_sz * i);
	823	+ newval = (newval & mask) \|
	824	+ (((val[i] / KSZ9131_STEP) & maxval)
	825	+ << (field_sz * i));
	826	+ }
	827	+
	828	+ return phy_write_mmd(phydev, 2, reg, newval);
	829	+}
	830	+
	831	+#define KSZ9131RN_MMD_COMMON_CTRL_REG 2
	832	+#define KSZ9131RN_RXC_DLL_CTRL 76
	833	+#define KSZ9131RN_TXC_DLL_CTRL 77
	834	+#define KSZ9131RN_DLL_CTRL_BYPASS BIT_MASK(12)
	835	+#define KSZ9131RN_DLL_ENABLE_DELAY 0
	836	+#define KSZ9131RN_DLL_DISABLE_DELAY BIT(12)
	837	+
	838	+static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
	839	+{
	840	+ u16 rxcdll_val, txcdll_val;
	841	+ int ret;
	842	+
	843	+ switch (phydev->interface) {
	844	+ case PHY_INTERFACE_MODE_RGMII:
	845	+ rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
	846	+ txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
	847	+ break;
	848	+ case PHY_INTERFACE_MODE_RGMII_ID:
	849	+ rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
	850	+ txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
	851	+ break;
	852	+ case PHY_INTERFACE_MODE_RGMII_RXID:
	853	+ rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
	854	+ txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
	855	+ break;
	856	+ case PHY_INTERFACE_MODE_RGMII_TXID:
	857	+ rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
	858	+ txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
	859	+ break;
	860	+ default:
	861	+ return 0;
	862	+ }
	863	+
	864	+ ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
	865	+ KSZ9131RN_RXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
	866	+ rxcdll_val);
	867	+ if (ret < 0)
	868	+ return ret;
	869	+
	870	+ return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
	871	+ KSZ9131RN_TXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
	872	+ txcdll_val);
	873	+}
	874	+
	875	+static int ksz9131_config_init(struct phy_device *phydev)
	876	+{
	877	+ const struct device *dev = &phydev->mdio.dev;
	878	+ struct device_node *of_node = dev->of_node;
	879	+ char *clk_skews[2] = {"rxc-skew-psec", "txc-skew-psec"};
	880	+ char *rx_data_skews[4] = {
	881	+ "rxd0-skew-psec", "rxd1-skew-psec",
	882	+ "rxd2-skew-psec", "rxd3-skew-psec"
	883	+ };
	884	+ char *tx_data_skews[4] = {
	885	+ "txd0-skew-psec", "txd1-skew-psec",
	886	+ "txd2-skew-psec", "txd3-skew-psec"
	887	+ };
	888	+ char *control_skews[2] = {"txen-skew-psec", "rxdv-skew-psec"};
	889	+ const struct device *dev_walker;
	890	+ int ret;
	891	+
	892	+ dev_walker = &phydev->mdio.dev;
	893	+ do {
	894	+ of_node = dev_walker->of_node;
	895	+ dev_walker = dev_walker->parent;
	896	+ } while (!of_node && dev_walker);
	897	+
	898	+ if (!of_node)
	899	+ return 0;
	900	+
	901	+ if (phy_interface_is_rgmii(phydev)) {
	902	+ ret = ksz9131_config_rgmii_delay(phydev);
	903	+ if (ret < 0)
	904	+ return ret;
	905	+ }
	906	+
	907	+ ret = ksz9131_of_load_skew_values(phydev, of_node,
	908	+ MII_KSZ9031RN_CLK_PAD_SKEW, 5,
	909	+ clk_skews, 2);
	910	+ if (ret < 0)
	911	+ return ret;
	912	+
	913	+ ret = ksz9131_of_load_skew_values(phydev, of_node,
	914	+ MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
	915	+ control_skews, 2);
	916	+ if (ret < 0)
	917	+ return ret;
	918	+
	919	+ ret = ksz9131_of_load_skew_values(phydev, of_node,
	920	+ MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
	921	+ rx_data_skews, 4);
	922	+ if (ret < 0)
	923	+ return ret;
	924	+
	925	+ ret = ksz9131_of_load_skew_values(phydev, of_node,
	926	+ MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
	927	+ tx_data_skews, 4);
	928	+ if (ret < 0)
	929	+ return ret;
	930	+
	931	+ return 0;
	932	+}
	933	+
624	934	#define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
625	935	#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6)
626	936	#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4)
..	..	@@ -645,6 +955,33 @@
645	955
646	956	phydev->link = 1;
647	957	phydev->pause = phydev->asym_pause = 0;
	958	+
	959	+ return 0;
	960	+}
	961	+
	962	+static int ksz9031_get_features(struct phy_device *phydev)
	963	+{
	964	+ int ret;
	965	+
	966	+ ret = genphy_read_abilities(phydev);
	967	+ if (ret < 0)
	968	+ return ret;
	969	+
	970	+ /* Silicon Errata Sheet (DS80000691D or DS80000692D):
	971	+ * Whenever the device's Asymmetric Pause capability is set to 1,
	972	+ * link-up may fail after a link-up to link-down transition.
	973	+ *
	974	+ * The Errata Sheet is for ksz9031, but ksz9021 has the same issue
	975	+ *
	976	+ * Workaround:
	977	+ * Do not enable the Asymmetric Pause capability bit.
	978	+ */
	979	+ linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);
	980	+
	981	+ /* We force setting the Pause capability as the core will force the
	982	+ * Asymmetric Pause capability to 1 otherwise.
	983	+ */
	984	+ linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
648	985
649	986	return 0;
650	987	}
..	..	@@ -775,7 +1112,7 @@
775	1112
776	1113	priv->type = type;
777	1114
778		- if (type->led_mode_reg) {
	1115	+ if (type && type->led_mode_reg) {
779	1116	ret = of_property_read_u32(np, "micrel,led-mode",
780	1117	&priv->led_mode);
781	1118	if (ret)
..	..	@@ -796,7 +1133,8 @@
796	1133	unsigned long rate = clk_get_rate(clk);
797	1134	bool rmii_ref_clk_sel_25_mhz;
798	1135
799		- priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
	1136	+ if (type)
	1137	+ priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
800	1138	rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
801	1139	"micrel,rmii-reference-clock-select-25-mhz");
802	1140
..	..	@@ -810,6 +1148,9 @@
810	1148	return -EINVAL;
811	1149	}
812	1150	}
	1151	+
	1152	+ if (ksz8041_fiber_mode(phydev))
	1153	+ phydev->port = PORT_FIBRE;
813	1154
814	1155	/* Support legacy board-file configuration */
815	1156	if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
..	..	@@ -825,8 +1166,7 @@
825	1166	.phy_id = PHY_ID_KS8737,
826	1167	.phy_id_mask = MICREL_PHY_ID_MASK,
827	1168	.name = "Micrel KS8737",
828		- .features = PHY_BASIC_FEATURES,
829		- .flags = PHY_HAS_INTERRUPT,
	1169	+ /* PHY_BASIC_FEATURES */
830	1170	.driver_data = &ks8737_type,
831	1171	.config_init = kszphy_config_init,
832	1172	.ack_interrupt = kszphy_ack_interrupt,
..	..	@@ -837,8 +1177,7 @@
837	1177	.phy_id = PHY_ID_KSZ8021,
838	1178	.phy_id_mask = 0x00ffffff,
839	1179	.name = "Micrel KSZ8021 or KSZ8031",
840		- .features = PHY_BASIC_FEATURES,
841		- .flags = PHY_HAS_INTERRUPT,
	1180	+ /* PHY_BASIC_FEATURES */
842	1181	.driver_data = &ksz8021_type,
843	1182	.probe = kszphy_probe,
844	1183	.config_init = kszphy_config_init,
..	..	@@ -853,8 +1192,7 @@
853	1192	.phy_id = PHY_ID_KSZ8031,
854	1193	.phy_id_mask = 0x00ffffff,
855	1194	.name = "Micrel KSZ8031",
856		- .features = PHY_BASIC_FEATURES,
857		- .flags = PHY_HAS_INTERRUPT,
	1195	+ /* PHY_BASIC_FEATURES */
858	1196	.driver_data = &ksz8021_type,
859	1197	.probe = kszphy_probe,
860	1198	.config_init = kszphy_config_init,
..	..	@@ -869,8 +1207,7 @@
869	1207	.phy_id = PHY_ID_KSZ8041,
870	1208	.phy_id_mask = MICREL_PHY_ID_MASK,
871	1209	.name = "Micrel KSZ8041",
872		- .features = PHY_BASIC_FEATURES,
873		- .flags = PHY_HAS_INTERRUPT,
	1210	+ /* PHY_BASIC_FEATURES */
874	1211	.driver_data = &ksz8041_type,
875	1212	.probe = kszphy_probe,
876	1213	.config_init = ksz8041_config_init,
..	..	@@ -887,8 +1224,7 @@
887	1224	.phy_id = PHY_ID_KSZ8041RNLI,
888	1225	.phy_id_mask = MICREL_PHY_ID_MASK,
889	1226	.name = "Micrel KSZ8041RNLI",
890		- .features = PHY_BASIC_FEATURES,
891		- .flags = PHY_HAS_INTERRUPT,
	1227	+ /* PHY_BASIC_FEATURES */
892	1228	.driver_data = &ksz8041_type,
893	1229	.probe = kszphy_probe,
894	1230	.config_init = kszphy_config_init,
..	..	@@ -900,11 +1236,8 @@
900	1236	.suspend = genphy_suspend,
901	1237	.resume = genphy_resume,
902	1238	}, {
903		- .phy_id = PHY_ID_KSZ8051,
904		- .phy_id_mask = MICREL_PHY_ID_MASK,
905	1239	.name = "Micrel KSZ8051",
906		- .features = PHY_BASIC_FEATURES,
907		- .flags = PHY_HAS_INTERRUPT,
	1240	+ /* PHY_BASIC_FEATURES */
908	1241	.driver_data = &ksz8051_type,
909	1242	.probe = kszphy_probe,
910	1243	.config_init = kszphy_config_init,
..	..	@@ -913,14 +1246,14 @@
913	1246	.get_sset_count = kszphy_get_sset_count,
914	1247	.get_strings = kszphy_get_strings,
915	1248	.get_stats = kszphy_get_stats,
	1249	+ .match_phy_device = ksz8051_match_phy_device,
916	1250	.suspend = genphy_suspend,
917	1251	.resume = genphy_resume,
918	1252	}, {
919	1253	.phy_id = PHY_ID_KSZ8001,
920	1254	.name = "Micrel KSZ8001 or KS8721",
921	1255	.phy_id_mask = 0x00fffffc,
922		- .features = PHY_BASIC_FEATURES,
923		- .flags = PHY_HAS_INTERRUPT,
	1256	+ /* PHY_BASIC_FEATURES */
924	1257	.driver_data = &ksz8041_type,
925	1258	.probe = kszphy_probe,
926	1259	.config_init = kszphy_config_init,
..	..	@@ -935,12 +1268,12 @@
935	1268	.phy_id = PHY_ID_KSZ8081,
936	1269	.name = "Micrel KSZ8081 or KSZ8091",
937	1270	.phy_id_mask = MICREL_PHY_ID_MASK,
938		- .features = PHY_BASIC_FEATURES,
939		- .flags = PHY_HAS_INTERRUPT,
	1271	+ /* PHY_BASIC_FEATURES */
940	1272	.driver_data = &ksz8081_type,
941	1273	.probe = kszphy_probe,
942		- .config_init = kszphy_config_init,
	1274	+ .config_init = ksz8081_config_init,
943	1275	.ack_interrupt = kszphy_ack_interrupt,
	1276	+ .soft_reset = genphy_soft_reset,
944	1277	.config_intr = kszphy_config_intr,
945	1278	.get_sset_count = kszphy_get_sset_count,
946	1279	.get_strings = kszphy_get_strings,
..	..	@@ -951,8 +1284,7 @@
951	1284	.phy_id = PHY_ID_KSZ8061,
952	1285	.name = "Micrel KSZ8061",
953	1286	.phy_id_mask = MICREL_PHY_ID_MASK,
954		- .features = PHY_BASIC_FEATURES,
955		- .flags = PHY_HAS_INTERRUPT,
	1287	+ /* PHY_BASIC_FEATURES */
956	1288	.config_init = ksz8061_config_init,
957	1289	.ack_interrupt = kszphy_ack_interrupt,
958	1290	.config_intr = kszphy_config_intr,
..	..	@@ -962,10 +1294,10 @@
962	1294	.phy_id = PHY_ID_KSZ9021,
963	1295	.phy_id_mask = 0x000ffffe,
964	1296	.name = "Micrel KSZ9021 Gigabit PHY",
965		- .features = PHY_GBIT_FEATURES,
966		- .flags = PHY_HAS_INTERRUPT,
	1297	+ /* PHY_GBIT_FEATURES */
967	1298	.driver_data = &ksz9021_type,
968	1299	.probe = kszphy_probe,
	1300	+ .get_features = ksz9031_get_features,
969	1301	.config_init = ksz9021_config_init,
970	1302	.ack_interrupt = kszphy_ack_interrupt,
971	1303	.config_intr = kszphy_config_intr,
..	..	@@ -980,10 +1312,9 @@
980	1312	.phy_id = PHY_ID_KSZ9031,
981	1313	.phy_id_mask = MICREL_PHY_ID_MASK,
982	1314	.name = "Micrel KSZ9031 Gigabit PHY",
983		- .features = PHY_GBIT_FEATURES,
984		- .flags = PHY_HAS_INTERRUPT,
985	1315	.driver_data = &ksz9021_type,
986	1316	.probe = kszphy_probe,
	1317	+ .get_features = ksz9031_get_features,
987	1318	.config_init = ksz9031_config_init,
988	1319	.soft_reset = genphy_soft_reset,
989	1320	.read_status = ksz9031_read_status,
..	..	@@ -995,9 +1326,39 @@
995	1326	.suspend = genphy_suspend,
996	1327	.resume = kszphy_resume,
997	1328	}, {
	1329	+ .phy_id = PHY_ID_LAN8814,
	1330	+ .phy_id_mask = MICREL_PHY_ID_MASK,
	1331	+ .name = "Microchip INDY Gigabit Quad PHY",
	1332	+ .driver_data = &ksz9021_type,
	1333	+ .probe = kszphy_probe,
	1334	+ .soft_reset = genphy_soft_reset,
	1335	+ .read_status = ksz9031_read_status,
	1336	+ .get_sset_count = kszphy_get_sset_count,
	1337	+ .get_strings = kszphy_get_strings,
	1338	+ .get_stats = kszphy_get_stats,
	1339	+ .suspend = genphy_suspend,
	1340	+ .resume = kszphy_resume,
	1341	+}, {
	1342	+ .phy_id = PHY_ID_KSZ9131,
	1343	+ .phy_id_mask = MICREL_PHY_ID_MASK,
	1344	+ .name = "Microchip KSZ9131 Gigabit PHY",
	1345	+ /* PHY_GBIT_FEATURES */
	1346	+ .driver_data = &ksz9021_type,
	1347	+ .probe = kszphy_probe,
	1348	+ .config_init = ksz9131_config_init,
	1349	+ .read_status = genphy_read_status,
	1350	+ .ack_interrupt = kszphy_ack_interrupt,
	1351	+ .config_intr = kszphy_config_intr,
	1352	+ .get_sset_count = kszphy_get_sset_count,
	1353	+ .get_strings = kszphy_get_strings,
	1354	+ .get_stats = kszphy_get_stats,
	1355	+ .suspend = genphy_suspend,
	1356	+ .resume = kszphy_resume,
	1357	+}, {
998	1358	.phy_id = PHY_ID_KSZ8873MLL,
999	1359	.phy_id_mask = MICREL_PHY_ID_MASK,
1000	1360	.name = "Micrel KSZ8873MLL Switch",
	1361	+ /* PHY_BASIC_FEATURES */
1001	1362	.config_init = kszphy_config_init,
1002	1363	.config_aneg = ksz8873mll_config_aneg,
1003	1364	.read_status = ksz8873mll_read_status,
..	..	@@ -1007,27 +1368,22 @@
1007	1368	.phy_id = PHY_ID_KSZ886X,
1008	1369	.phy_id_mask = MICREL_PHY_ID_MASK,
1009	1370	.name = "Micrel KSZ886X Switch",
1010		- .features = PHY_BASIC_FEATURES,
1011		- .flags = PHY_HAS_INTERRUPT,
	1371	+ /* PHY_BASIC_FEATURES */
1012	1372	.config_init = kszphy_config_init,
1013	1373	.suspend = genphy_suspend,
1014	1374	.resume = genphy_resume,
1015	1375	}, {
1016		- .phy_id = PHY_ID_KSZ8795,
1017		- .phy_id_mask = MICREL_PHY_ID_MASK,
1018		- .name = "Micrel KSZ8795",
1019		- .features = PHY_BASIC_FEATURES,
1020		- .flags = PHY_HAS_INTERRUPT,
	1376	+ .name = "Micrel KSZ87XX Switch",
	1377	+ /* PHY_BASIC_FEATURES */
1021	1378	.config_init = kszphy_config_init,
1022		- .config_aneg = ksz8873mll_config_aneg,
1023		- .read_status = ksz8873mll_read_status,
	1379	+ .match_phy_device = ksz8795_match_phy_device,
1024	1380	.suspend = genphy_suspend,
1025	1381	.resume = genphy_resume,
1026	1382	}, {
1027	1383	.phy_id = PHY_ID_KSZ9477,
1028	1384	.phy_id_mask = MICREL_PHY_ID_MASK,
1029	1385	.name = "Microchip KSZ9477",
1030		- .features = PHY_GBIT_FEATURES,
	1386	+ /* PHY_GBIT_FEATURES */
1031	1387	.config_init = kszphy_config_init,
1032	1388	.suspend = genphy_suspend,
1033	1389	.resume = genphy_resume,
..	..	@@ -1042,6 +1398,7 @@
1042	1398	static struct mdio_device_id __maybe_unused micrel_tbl[] = {
1043	1399	{ PHY_ID_KSZ9021, 0x000ffffe },
1044	1400	{ PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
	1401	+ { PHY_ID_KSZ9131, MICREL_PHY_ID_MASK },
1045	1402	{ PHY_ID_KSZ8001, 0x00fffffc },
1046	1403	{ PHY_ID_KS8737, MICREL_PHY_ID_MASK },
1047	1404	{ PHY_ID_KSZ8021, 0x00ffffff },
..	..	@@ -1052,6 +1409,7 @@
1052	1409	{ PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
1053	1410	{ PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
1054	1411	{ PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
	1412	+ { PHY_ID_LAN8814, MICREL_PHY_ID_MASK },
1055	1413	{ }
1056	1414	};
1057	1415