hc
2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390
kernel/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
....@@ -2009,6 +2009,11 @@
20092009 goto cleanup_clk;
20102010 }
20112011
2012
+ /* Reset core now that clocks are enabled, prior to accessing MDIO */
2013
+ ret = __axienet_device_reset(lp);
2014
+ if (ret)
2015
+ goto cleanup_clk;
2016
+
20122017 /* Autodetect the need for 64-bit DMA pointers.
20132018 * When the IP is configured for a bus width bigger than 32 bits,
20142019 * writing the MSB registers is mandatory, even if they are all 0.
....@@ -2054,11 +2059,6 @@
20542059
20552060 lp->coalesce_count_rx = XAXIDMA_DFT_RX_THRESHOLD;
20562061 lp->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD;
2057
-
2058
- /* Reset core now that clocks are enabled, prior to accessing MDIO */
2059
- ret = __axienet_device_reset(lp);
2060
- if (ret)
2061
- goto cleanup_clk;
20622062
20632063 ret = axienet_mdio_setup(lp);
20642064 if (ret)