.. | .. |
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2009 | 2009 | goto cleanup_clk; |
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2010 | 2010 | } |
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2011 | 2011 | |
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| 2012 | + /* Reset core now that clocks are enabled, prior to accessing MDIO */ |
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| 2013 | + ret = __axienet_device_reset(lp); |
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| 2014 | + if (ret) |
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| 2015 | + goto cleanup_clk; |
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| 2016 | + |
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2012 | 2017 | /* Autodetect the need for 64-bit DMA pointers. |
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2013 | 2018 | * When the IP is configured for a bus width bigger than 32 bits, |
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2014 | 2019 | * writing the MSB registers is mandatory, even if they are all 0. |
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.. | .. |
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2054 | 2059 | |
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2055 | 2060 | lp->coalesce_count_rx = XAXIDMA_DFT_RX_THRESHOLD; |
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2056 | 2061 | lp->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD; |
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2057 | | - |
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2058 | | - /* Reset core now that clocks are enabled, prior to accessing MDIO */ |
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2059 | | - ret = __axienet_device_reset(lp); |
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2060 | | - if (ret) |
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2061 | | - goto cleanup_clk; |
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2062 | 2062 | |
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2063 | 2063 | ret = axienet_mdio_setup(lp); |
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2064 | 2064 | if (ret) |
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