change wifi driver to cypress

hc

2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390

 kernel/drivers/net/ethernet/mellanox/mlx5/core/accel/tls.h
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@@ -37,7 +37,66 @@
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 #include <linux/mlx5/driver.h>
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 #include <linux/tls.h>
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-#ifdef CONFIG_MLX5_ACCEL
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+#ifdef CONFIG_MLX5_TLS
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+int mlx5_ktls_create_key(struct mlx5_core_dev *mdev,
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+			 struct tls_crypto_info *crypto_info,
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+			 u32 *p_key_id);
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+void mlx5_ktls_destroy_key(struct mlx5_core_dev *mdev, u32 key_id);
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+
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+static inline bool mlx5_accel_is_ktls_tx(struct mlx5_core_dev *mdev)
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+{
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+	return MLX5_CAP_GEN(mdev, tls_tx);
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+}
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+
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+static inline bool mlx5_accel_is_ktls_rx(struct mlx5_core_dev *mdev)
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+{
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+	return MLX5_CAP_GEN(mdev, tls_rx);
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+}
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+
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+static inline bool mlx5_accel_is_ktls_device(struct mlx5_core_dev *mdev)
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+{
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+	if (!mlx5_accel_is_ktls_tx(mdev) &&
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+	    !mlx5_accel_is_ktls_rx(mdev))
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+		return false;
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+
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+	if (!MLX5_CAP_GEN(mdev, log_max_dek))
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+		return false;
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+
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+	return MLX5_CAP_TLS(mdev, tls_1_2_aes_gcm_128);
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+}
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+
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+static inline bool mlx5e_ktls_type_check(struct mlx5_core_dev *mdev,
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+					 struct tls_crypto_info *crypto_info)
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+{
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+	switch (crypto_info->cipher_type) {
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+	case TLS_CIPHER_AES_GCM_128:
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+		if (crypto_info->version == TLS_1_2_VERSION)
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+			return MLX5_CAP_TLS(mdev,  tls_1_2_aes_gcm_128);
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+		break;
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+	}
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+
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+	return false;
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+}
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+#else
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+static inline bool mlx5_accel_is_ktls_tx(struct mlx5_core_dev *mdev)
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+{ return false; }
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+
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+static inline bool mlx5_accel_is_ktls_rx(struct mlx5_core_dev *mdev)
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+{ return false; }
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+
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+static inline int
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+mlx5_ktls_create_key(struct mlx5_core_dev *mdev,
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+		     struct tls_crypto_info *crypto_info,
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+		     u32 *p_key_id) { return -ENOTSUPP; }
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+static inline void
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+mlx5_ktls_destroy_key(struct mlx5_core_dev *mdev, u32 key_id) {}
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+
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+static inline bool
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+mlx5_accel_is_ktls_device(struct mlx5_core_dev *mdev) { return false; }
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+static inline bool
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+mlx5e_ktls_type_check(struct mlx5_core_dev *mdev,
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+		      struct tls_crypto_info *crypto_info) { return false; }
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+#endif
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 enum {
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 	MLX5_ACCEL_TLS_TX = BIT(0),
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@@ -60,14 +119,15 @@
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 	u8         reserved_at_2[0x1e];
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 };
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+#ifdef CONFIG_MLX5_FPGA_TLS
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 int mlx5_accel_tls_add_flow(struct mlx5_core_dev *mdev, void *flow,
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 			    struct tls_crypto_info *crypto_info,
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 			    u32 start_offload_tcp_sn, u32 *p_swid,
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 			    bool direction_sx);
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 void mlx5_accel_tls_del_flow(struct mlx5_core_dev *mdev, u32 swid,
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 			     bool direction_sx);
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-int mlx5_accel_tls_resync_rx(struct mlx5_core_dev *mdev, u32 handle, u32 seq,
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-			     u64 rcd_sn);
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+int mlx5_accel_tls_resync_rx(struct mlx5_core_dev *mdev, __be32 handle,
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+			     u32 seq, __be64 rcd_sn);
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 bool mlx5_accel_is_tls_device(struct mlx5_core_dev *mdev);
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 u32 mlx5_accel_tls_device_caps(struct mlx5_core_dev *mdev);
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 int mlx5_accel_tls_init(struct mlx5_core_dev *mdev);
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@@ -82,13 +142,15 @@
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 			bool direction_sx) { return -ENOTSUPP; }
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 static inline void mlx5_accel_tls_del_flow(struct mlx5_core_dev *mdev, u32 swid,
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 					   bool direction_sx) { }
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-static inline int mlx5_accel_tls_resync_rx(struct mlx5_core_dev *mdev, u32 handle,
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-					   u32 seq, u64 rcd_sn) { return 0; }
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-static inline bool mlx5_accel_is_tls_device(struct mlx5_core_dev *mdev) { return false; }
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+static inline int mlx5_accel_tls_resync_rx(struct mlx5_core_dev *mdev, __be32 handle,
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+					   u32 seq, __be64 rcd_sn) { return 0; }
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+static inline bool mlx5_accel_is_tls_device(struct mlx5_core_dev *mdev)
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+{
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+	return mlx5_accel_is_ktls_device(mdev);
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+}
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 static inline u32 mlx5_accel_tls_device_caps(struct mlx5_core_dev *mdev) { return 0; }
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 static inline int mlx5_accel_tls_init(struct mlx5_core_dev *mdev) { return 0; }
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 static inline void mlx5_accel_tls_cleanup(struct mlx5_core_dev *mdev) { }
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-
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 #endif
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 #endif	/* __MLX5_ACCEL_TLS_H__ */