change wifi driver to cypress

hc

2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390

 kernel/drivers/net/ethernet/hisilicon/hns3/hclge_mbx.h
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@@ -7,8 +7,6 @@
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 #include <linux/mutex.h>
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 #include <linux/types.h>
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-#define HCLGE_MBX_VF_MSG_DATA_NUM	16
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-
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 enum HCLGE_MBX_OPCODE {
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 	HCLGE_MBX_RESET = 0x01,		/* (VF -> PF) assert reset */
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 	HCLGE_MBX_ASSERTING_RESET,	/* (PF -> VF) PF is asserting reset*/
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@@ -21,11 +19,12 @@
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 	HCLGE_MBX_SET_MACVLAN,		/* (VF -> PF) set unicast filter */
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 	HCLGE_MBX_API_NEGOTIATE,	/* (VF -> PF) negotiate API version */
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 	HCLGE_MBX_GET_QINFO,		/* (VF -> PF) get queue config */
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+	HCLGE_MBX_GET_QDEPTH,		/* (VF -> PF) get queue depth */
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 	HCLGE_MBX_GET_TCINFO,		/* (VF -> PF) get TC config */
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 	HCLGE_MBX_GET_RETA,		/* (VF -> PF) get RETA */
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 	HCLGE_MBX_GET_RSS_KEY,		/* (VF -> PF) get RSS key */
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 	HCLGE_MBX_GET_MAC_ADDR,		/* (VF -> PF) get MAC addr */
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-	HCLGE_MBX_PF_VF_RESP,		/* (PF -> VF) generate respone to VF */
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+	HCLGE_MBX_PF_VF_RESP,		/* (PF -> VF) generate response to VF */
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 	HCLGE_MBX_GET_BDNUM,		/* (VF -> PF) get BD num */
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 	HCLGE_MBX_GET_BUFSIZE,		/* (VF -> PF) get buffer size */
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 	HCLGE_MBX_GET_STREAMID,		/* (VF -> PF) get stream id */
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@@ -36,6 +35,21 @@
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 	HCLGE_MBX_BIND_FUNC_QUEUE,	/* (VF -> PF) bind function and queue */
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 	HCLGE_MBX_GET_LINK_STATUS,	/* (VF -> PF) get link status */
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 	HCLGE_MBX_QUEUE_RESET,		/* (VF -> PF) reset queue */
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+	HCLGE_MBX_KEEP_ALIVE,		/* (VF -> PF) send keep alive cmd */
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+	HCLGE_MBX_SET_ALIVE,		/* (VF -> PF) set alive state */
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+	HCLGE_MBX_SET_MTU,		/* (VF -> PF) set mtu */
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+	HCLGE_MBX_GET_QID_IN_PF,	/* (VF -> PF) get queue id in pf */
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+	HCLGE_MBX_LINK_STAT_MODE,	/* (PF -> VF) link mode has changed */
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+	HCLGE_MBX_GET_LINK_MODE,	/* (VF -> PF) get the link mode of pf */
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+	HCLGE_MBX_PUSH_VLAN_INFO,	/* (PF -> VF) push port base vlan */
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+	HCLGE_MBX_GET_MEDIA_TYPE,       /* (VF -> PF) get media type */
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+	HCLGE_MBX_PUSH_PROMISC_INFO,	/* (PF -> VF) push vf promisc info */
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+	HCLGE_MBX_VF_UNINIT,            /* (VF -> PF) vf is unintializing */
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+	HCLGE_MBX_HANDLE_VF_TBL,	/* (VF -> PF) store/clear hw table */
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+
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+	HCLGE_MBX_GET_VF_FLR_STATUS = 200, /* (M7 -> PF) get vf flr status */
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+	HCLGE_MBX_PUSH_LINK_STATUS,	/* (M7 -> PF) get port link status */
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+	HCLGE_MBX_NCSI_ERROR,		/* (M7 -> PF) receive a NCSI error */
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 };
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 /* below are per-VF mac-vlan subcodes */
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@@ -46,9 +60,6 @@
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 	HCLGE_MBX_MAC_VLAN_MC_MODIFY,		/* modify MC mac addr */
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 	HCLGE_MBX_MAC_VLAN_MC_ADD,		/* add new MC mac addr */
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 	HCLGE_MBX_MAC_VLAN_MC_REMOVE,		/* remove MC mac addr */
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-	HCLGE_MBX_MAC_VLAN_MC_FUNC_MTA_ENABLE,	/* config func MTA enable */
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-	HCLGE_MBX_MAC_VLAN_MTA_TYPE_READ,	/* read func MTA type */
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-	HCLGE_MBX_MAC_VLAN_MTA_STATUS_UPDATE,	/* update MTA status */
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 };
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 /* below are per-VF vlan cfg subcodes */
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@@ -56,12 +67,23 @@
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 	HCLGE_MBX_VLAN_FILTER = 0,	/* set vlan filter */
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 	HCLGE_MBX_VLAN_TX_OFF_CFG,	/* set tx side vlan offload */
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 	HCLGE_MBX_VLAN_RX_OFF_CFG,	/* set rx side vlan offload */
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+	HCLGE_MBX_PORT_BASE_VLAN_CFG,	/* set port based vlan configuration */
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+	HCLGE_MBX_GET_PORT_BASE_VLAN_STATE,	/* get port based vlan state */
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 };
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-#define HCLGE_MBX_MAX_MSG_SIZE	16
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-#define HCLGE_MBX_MAX_RESP_DATA_SIZE	8
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-#define HCLGE_MBX_RING_MAP_BASIC_MSG_NUM	3
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-#define HCLGE_MBX_RING_NODE_VARIABLE_NUM	3
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+enum hclge_mbx_tbl_cfg_subcode {
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+	HCLGE_MBX_VPORT_LIST_CLEAR,
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+};
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+
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+#define HCLGE_MBX_MAX_MSG_SIZE	14
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+#define HCLGE_MBX_MAX_RESP_DATA_SIZE	8U
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+#define HCLGE_MBX_MAX_RING_CHAIN_PARAM_NUM	4
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+
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+struct hclge_ring_chain_param {
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+	u8 ring_type;
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+	u8 tqp_index;
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+	u8 int_gl_index;
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+};
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 struct hclgevf_mbx_resp_status {
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 	struct mutex mbx_mutex; /* protects against contending sync cmd resp */
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@@ -71,21 +93,67 @@
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 	u8 additional_info[HCLGE_MBX_MAX_RESP_DATA_SIZE];
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 };
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+struct hclge_respond_to_vf_msg {
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+	int status;
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+	u8 data[HCLGE_MBX_MAX_RESP_DATA_SIZE];
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+	u16 len;
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+};
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+
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+struct hclge_vf_to_pf_msg {
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+	u8 code;
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+	union {
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+		struct {
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+			u8 subcode;
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+			u8 data[HCLGE_MBX_MAX_MSG_SIZE];
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+		};
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+		struct {
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+			u8 en_bc;
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+			u8 en_uc;
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+			u8 en_mc;
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+		};
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+		struct {
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+			u8 vector_id;
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+			u8 ring_num;
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+			struct hclge_ring_chain_param
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+				param[HCLGE_MBX_MAX_RING_CHAIN_PARAM_NUM];
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+		};
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+	};
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+};
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+
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+struct hclge_pf_to_vf_msg {
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+	u16 code;
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+	u16 vf_mbx_msg_code;
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+	u16 vf_mbx_msg_subcode;
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+	u16 resp_status;
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+	u8 resp_data[HCLGE_MBX_MAX_RESP_DATA_SIZE];
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+};
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+
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 struct hclge_mbx_vf_to_pf_cmd {
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 	u8 rsv;
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 	u8 mbx_src_vfid; /* Auto filled by IMP */
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-	u8 rsv1[2];
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+	u8 mbx_need_resp;
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+	u8 rsv1[1];
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 	u8 msg_len;
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-	u8 rsv2[3];
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-	u8 msg[HCLGE_MBX_MAX_MSG_SIZE];
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+	u8 rsv2;
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+	u16 match_id;
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+	struct hclge_vf_to_pf_msg msg;
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 };
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+
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+#define HCLGE_MBX_NEED_RESP_B		0
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 struct hclge_mbx_pf_to_vf_cmd {
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 	u8 dest_vfid;
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 	u8 rsv[3];
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 	u8 msg_len;
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-	u8 rsv1[3];
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-	u16 msg[8];
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+	u8 rsv1;
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+	u16 match_id;
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+	struct hclge_pf_to_vf_msg msg;
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+};
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+
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+struct hclge_vf_rst_cmd {
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+	u8 dest_vfid;
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+	u8 vf_rst;
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+	u8 rsv[22];
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 };
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 /* used by VF to store the received Async responses from PF */
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@@ -95,7 +163,7 @@
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 	struct hclgevf_dev *hdev;
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 	u32 head;
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 	u32 tail;
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-	u32 count;
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+	atomic_t count;
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 	u16 msg_q[HCLGE_MBX_MAX_ARQ_MSG_NUM][HCLGE_MBX_MAX_ARQ_MSG_SIZE];
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 };
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