.. | .. |
---|
1044 | 1044 | dispatch = &oct->dispatch.dlist[i].list; |
---|
1045 | 1045 | while (dispatch->next != dispatch) { |
---|
1046 | 1046 | temp = dispatch->next; |
---|
1047 | | - list_del(temp); |
---|
1048 | | - list_add_tail(temp, &freelist); |
---|
| 1047 | + list_move_tail(temp, &freelist); |
---|
1049 | 1048 | } |
---|
1050 | 1049 | |
---|
1051 | 1050 | oct->dispatch.dlist[i].opcode = 0; |
---|
.. | .. |
---|
1057 | 1056 | |
---|
1058 | 1057 | list_for_each_safe(temp, tmp2, &freelist) { |
---|
1059 | 1058 | list_del(temp); |
---|
1060 | | - vfree(temp); |
---|
| 1059 | + kfree(temp); |
---|
1061 | 1060 | } |
---|
1062 | 1061 | } |
---|
1063 | 1062 | |
---|
.. | .. |
---|
1153 | 1152 | |
---|
1154 | 1153 | dev_dbg(&oct->pci_dev->dev, |
---|
1155 | 1154 | "Adding opcode to dispatch list linked list\n"); |
---|
1156 | | - dispatch = (struct octeon_dispatch *) |
---|
1157 | | - vmalloc(sizeof(struct octeon_dispatch)); |
---|
1158 | | - if (!dispatch) { |
---|
1159 | | - dev_err(&oct->pci_dev->dev, |
---|
1160 | | - "No memory to add dispatch function\n"); |
---|
| 1155 | + dispatch = kmalloc(sizeof(*dispatch), GFP_KERNEL); |
---|
| 1156 | + if (!dispatch) |
---|
1161 | 1157 | return 1; |
---|
1162 | | - } |
---|
| 1158 | + |
---|
1163 | 1159 | dispatch->opcode = combined_opcode; |
---|
1164 | 1160 | dispatch->dispatch_fn = fn; |
---|
1165 | 1161 | dispatch->arg = fn_arg; |
---|
.. | .. |
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1311 | 1307 | /* scratch register address is same in all the OCT-II and CN70XX models */ |
---|
1312 | 1308 | #define CNXX_SLI_SCRATCH1 0x3C0 |
---|
1313 | 1309 | |
---|
1314 | | -/** Get the octeon device pointer. |
---|
| 1310 | +/* Get the octeon device pointer. |
---|
1315 | 1311 | * @param octeon_id - The id for which the octeon device pointer is required. |
---|
1316 | 1312 | * @return Success: Octeon device pointer. |
---|
1317 | 1313 | * @return Failure: NULL. |
---|
.. | .. |
---|
1328 | 1324 | { |
---|
1329 | 1325 | u64 val64; |
---|
1330 | 1326 | unsigned long flags; |
---|
1331 | | - u32 val32, addrhi; |
---|
| 1327 | + u32 addrhi; |
---|
1332 | 1328 | |
---|
1333 | 1329 | spin_lock_irqsave(&oct->pci_win_lock, flags); |
---|
1334 | 1330 | |
---|
.. | .. |
---|
1343 | 1339 | writel(addrhi, oct->reg_list.pci_win_rd_addr_hi); |
---|
1344 | 1340 | |
---|
1345 | 1341 | /* Read back to preserve ordering of writes */ |
---|
1346 | | - val32 = readl(oct->reg_list.pci_win_rd_addr_hi); |
---|
| 1342 | + readl(oct->reg_list.pci_win_rd_addr_hi); |
---|
1347 | 1343 | |
---|
1348 | 1344 | writel(addr & 0xffffffff, oct->reg_list.pci_win_rd_addr_lo); |
---|
1349 | | - val32 = readl(oct->reg_list.pci_win_rd_addr_lo); |
---|
| 1345 | + readl(oct->reg_list.pci_win_rd_addr_lo); |
---|
1350 | 1346 | |
---|
1351 | 1347 | val64 = readq(oct->reg_list.pci_win_rd_data); |
---|
1352 | 1348 | |
---|
.. | .. |
---|
1359 | 1355 | u64 val, |
---|
1360 | 1356 | u64 addr) |
---|
1361 | 1357 | { |
---|
1362 | | - u32 val32; |
---|
1363 | 1358 | unsigned long flags; |
---|
1364 | 1359 | |
---|
1365 | 1360 | spin_lock_irqsave(&oct->pci_win_lock, flags); |
---|
.. | .. |
---|
1369 | 1364 | /* The write happens when the LSB is written. So write MSB first. */ |
---|
1370 | 1365 | writel(val >> 32, oct->reg_list.pci_win_wr_data_hi); |
---|
1371 | 1366 | /* Read the MSB to ensure ordering of writes. */ |
---|
1372 | | - val32 = readl(oct->reg_list.pci_win_wr_data_hi); |
---|
| 1367 | + readl(oct->reg_list.pci_win_wr_data_hi); |
---|
1373 | 1368 | |
---|
1374 | 1369 | writel(val & 0xffffffff, oct->reg_list.pci_win_wr_data_lo); |
---|
1375 | 1370 | |
---|
.. | .. |
---|
1415 | 1410 | return ret; |
---|
1416 | 1411 | } |
---|
1417 | 1412 | |
---|
1418 | | -/** Get the octeon id assigned to the octeon device passed as argument. |
---|
| 1413 | +/* Get the octeon id assigned to the octeon device passed as argument. |
---|
1419 | 1414 | * This function is exported to other modules. |
---|
1420 | 1415 | * @param dev - octeon device pointer passed as a void *. |
---|
1421 | 1416 | * @return octeon device id |
---|
.. | .. |
---|
1440 | 1435 | /* the whole thing needs to be atomic, ideally */ |
---|
1441 | 1436 | if (droq) { |
---|
1442 | 1437 | pkts_pend = (u32)atomic_read(&droq->pkts_pending); |
---|
1443 | | - spin_lock_bh(&droq->lock); |
---|
1444 | 1438 | writel(droq->pkt_count - pkts_pend, droq->pkts_sent_reg); |
---|
1445 | 1439 | droq->pkt_count = pkts_pend; |
---|
1446 | | - /* this write needs to be flushed before we release the lock */ |
---|
1447 | | - mmiowb(); |
---|
1448 | | - spin_unlock_bh(&droq->lock); |
---|
1449 | 1440 | oct = droq->oct_dev; |
---|
1450 | 1441 | } |
---|
1451 | 1442 | if (iq) { |
---|
.. | .. |
---|
1454 | 1445 | iq->pkt_in_done -= iq->pkts_processed; |
---|
1455 | 1446 | iq->pkts_processed = 0; |
---|
1456 | 1447 | /* this write needs to be flushed before we release the lock */ |
---|
1457 | | - mmiowb(); |
---|
1458 | 1448 | spin_unlock_bh(&iq->lock); |
---|
1459 | 1449 | oct = iq->oct_dev; |
---|
1460 | 1450 | } |
---|