forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390
kernel/drivers/net/ethernet/cavium/liquidio/octeon_device.c
....@@ -1044,8 +1044,7 @@
10441044 dispatch = &oct->dispatch.dlist[i].list;
10451045 while (dispatch->next != dispatch) {
10461046 temp = dispatch->next;
1047
- list_del(temp);
1048
- list_add_tail(temp, &freelist);
1047
+ list_move_tail(temp, &freelist);
10491048 }
10501049
10511050 oct->dispatch.dlist[i].opcode = 0;
....@@ -1057,7 +1056,7 @@
10571056
10581057 list_for_each_safe(temp, tmp2, &freelist) {
10591058 list_del(temp);
1060
- vfree(temp);
1059
+ kfree(temp);
10611060 }
10621061 }
10631062
....@@ -1153,13 +1152,10 @@
11531152
11541153 dev_dbg(&oct->pci_dev->dev,
11551154 "Adding opcode to dispatch list linked list\n");
1156
- dispatch = (struct octeon_dispatch *)
1157
- vmalloc(sizeof(struct octeon_dispatch));
1158
- if (!dispatch) {
1159
- dev_err(&oct->pci_dev->dev,
1160
- "No memory to add dispatch function\n");
1155
+ dispatch = kmalloc(sizeof(*dispatch), GFP_KERNEL);
1156
+ if (!dispatch)
11611157 return 1;
1162
- }
1158
+
11631159 dispatch->opcode = combined_opcode;
11641160 dispatch->dispatch_fn = fn;
11651161 dispatch->arg = fn_arg;
....@@ -1311,7 +1307,7 @@
13111307 /* scratch register address is same in all the OCT-II and CN70XX models */
13121308 #define CNXX_SLI_SCRATCH1 0x3C0
13131309
1314
-/** Get the octeon device pointer.
1310
+/* Get the octeon device pointer.
13151311 * @param octeon_id - The id for which the octeon device pointer is required.
13161312 * @return Success: Octeon device pointer.
13171313 * @return Failure: NULL.
....@@ -1328,7 +1324,7 @@
13281324 {
13291325 u64 val64;
13301326 unsigned long flags;
1331
- u32 val32, addrhi;
1327
+ u32 addrhi;
13321328
13331329 spin_lock_irqsave(&oct->pci_win_lock, flags);
13341330
....@@ -1343,10 +1339,10 @@
13431339 writel(addrhi, oct->reg_list.pci_win_rd_addr_hi);
13441340
13451341 /* Read back to preserve ordering of writes */
1346
- val32 = readl(oct->reg_list.pci_win_rd_addr_hi);
1342
+ readl(oct->reg_list.pci_win_rd_addr_hi);
13471343
13481344 writel(addr & 0xffffffff, oct->reg_list.pci_win_rd_addr_lo);
1349
- val32 = readl(oct->reg_list.pci_win_rd_addr_lo);
1345
+ readl(oct->reg_list.pci_win_rd_addr_lo);
13501346
13511347 val64 = readq(oct->reg_list.pci_win_rd_data);
13521348
....@@ -1359,7 +1355,6 @@
13591355 u64 val,
13601356 u64 addr)
13611357 {
1362
- u32 val32;
13631358 unsigned long flags;
13641359
13651360 spin_lock_irqsave(&oct->pci_win_lock, flags);
....@@ -1369,7 +1364,7 @@
13691364 /* The write happens when the LSB is written. So write MSB first. */
13701365 writel(val >> 32, oct->reg_list.pci_win_wr_data_hi);
13711366 /* Read the MSB to ensure ordering of writes. */
1372
- val32 = readl(oct->reg_list.pci_win_wr_data_hi);
1367
+ readl(oct->reg_list.pci_win_wr_data_hi);
13731368
13741369 writel(val & 0xffffffff, oct->reg_list.pci_win_wr_data_lo);
13751370
....@@ -1415,7 +1410,7 @@
14151410 return ret;
14161411 }
14171412
1418
-/** Get the octeon id assigned to the octeon device passed as argument.
1413
+/* Get the octeon id assigned to the octeon device passed as argument.
14191414 * This function is exported to other modules.
14201415 * @param dev - octeon device pointer passed as a void *.
14211416 * @return octeon device id
....@@ -1440,12 +1435,8 @@
14401435 /* the whole thing needs to be atomic, ideally */
14411436 if (droq) {
14421437 pkts_pend = (u32)atomic_read(&droq->pkts_pending);
1443
- spin_lock_bh(&droq->lock);
14441438 writel(droq->pkt_count - pkts_pend, droq->pkts_sent_reg);
14451439 droq->pkt_count = pkts_pend;
1446
- /* this write needs to be flushed before we release the lock */
1447
- mmiowb();
1448
- spin_unlock_bh(&droq->lock);
14491440 oct = droq->oct_dev;
14501441 }
14511442 if (iq) {
....@@ -1454,7 +1445,6 @@
14541445 iq->pkt_in_done -= iq->pkts_processed;
14551446 iq->pkts_processed = 0;
14561447 /* this write needs to be flushed before we release the lock */
1457
- mmiowb();
14581448 spin_unlock_bh(&iq->lock);
14591449 oct = iq->oct_dev;
14601450 }