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2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390 
 kernel/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h
....@@ -1,10 +1,8 @@
1
-/*
2
- * aQuantia Corporation Network Driver
3
- * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
1
+/* SPDX-License-Identifier: GPL-2.0-only */
2
+/* Atlantic Network Driver
43  *
5
- * This program is free software; you can redistribute it and/or modify it
6
- * under the terms and conditions of the GNU General Public License,
7
- * version 2, as published by the Free Software Foundation.
4
+ * Copyright (C) 2014-2019 aQuantia Corporation
5
+ * Copyright (C) 2019-2020 Marvell International Ltd.
86  */
97 
108 /* File hw_atl_llh_internal.h: Preprocessor definitions
....@@ -13,6 +11,36 @@
1311 
1412 #ifndef HW_ATL_LLH_INTERNAL_H
1513 #define HW_ATL_LLH_INTERNAL_H
14
+
15
+/* COM Temperature Sense Reset Bitfield Definitions */
16
+#define HW_ATL_TS_RESET_ADR 0x00003100
17
+#define HW_ATL_TS_RESET_MSK 0x00000004
18
+#define HW_ATL_TS_RESET_SHIFT 2
19
+#define HW_ATL_TS_RESET_WIDTH 1
20
+
21
+/* COM Temperature Sense Power Down Bitfield Definitions */
22
+#define HW_ATL_TS_POWER_DOWN_ADR 0x00003100
23
+#define HW_ATL_TS_POWER_DOWN_MSK 0x00000001
24
+#define HW_ATL_TS_POWER_DOWN_SHIFT 0
25
+#define HW_ATL_TS_POWER_DOWN_WIDTH 1
26
+
27
+/* COM Temperature Sense Ready Bitfield Definitions */
28
+#define HW_ATL_TS_READY_ADR 0x00003120
29
+#define HW_ATL_TS_READY_MSK 0x80000000
30
+#define HW_ATL_TS_READY_SHIFT 31
31
+#define HW_ATL_TS_READY_WIDTH 1
32
+
33
+/*  COM Temperature Sense Ready Latch High Bitfield Definitions */
34
+#define HW_ATL_TS_READY_LATCH_HIGH_ADR 0x00003120
35
+#define HW_ATL_TS_READY_LATCH_HIGH_MSK 0x40000000
36
+#define HW_ATL_TS_READY_LATCH_HIGH_SHIFT 30
37
+#define HW_ATL_TS_READY_LATCH_HIGH_WIDTH 1
38
+
39
+/* COM Temperature Sense Data Out [B:0] Bitfield Definitions */
40
+#define HW_ATL_TS_DATA_OUT_ADR 0x00003120
41
+#define HW_ATL_TS_DATA_OUT_MSK 0x00000FFF
42
+#define HW_ATL_TS_DATA_OUT_SHIFT 0
43
+#define HW_ATL_TS_DATA_OUT_WIDTH 12
1644 
1745 /* global microprocessor semaphore  definitions
1846  * base address: 0x000003a0
....@@ -58,9 +86,6 @@
5886 /* preprocessor definitions for msm rx unicast octets counter register 0 */
5987 #define HW_ATL_MAC_MSM_RX_UCST_OCTETS_COUNTER0_ADR 0x000001b8u
6088 
61
-/* preprocessor definitions for rx dma statistics counter 7 */
62
-#define HW_ATL_RX_DMA_STAT_COUNTER7_ADR 0x00006818u
63
-
6489 /* preprocessor definitions for msm tx unicast frames counter register */
6590 #define HW_ATL_MAC_MSM_TX_UCST_FRM_CNT_ADR 0x00000108u
6691 
....@@ -95,6 +120,19 @@
95120 #define HW_ATL_ITR_RES_MSK 0x80000000
96121 /* lower bit position of bitfield itr_reset */
97122 #define HW_ATL_ITR_RES_SHIFT 31
123
+
124
+/* register address for bitfield  rsc_en */
125
+#define HW_ATL_ITR_RSC_EN_ADR 0x00002200
126
+
127
+/* register address for bitfield  rsc_delay */
128
+#define HW_ATL_ITR_RSC_DELAY_ADR 0x00002204
129
+/* bitmask for bitfield  rsc_delay */
130
+#define HW_ATL_ITR_RSC_DELAY_MSK 0x0000000f
131
+/* width of bitfield  rsc_delay */
132
+#define HW_ATL_ITR_RSC_DELAY_WIDTH 4
133
+/* lower bit position of bitfield  rsc_delay */
134
+#define HW_ATL_ITR_RSC_DELAY_SHIFT 0
135
+
98136 /* register address for bitfield dca{d}_cpuid[7:0] */
99137 #define HW_ATL_RDM_DCADCPUID_ADR(dca) (0x00006100 + (dca) * 0x4)
100138 /* bitmask for bitfield dca{d}_cpuid[7:0] */
....@@ -310,6 +348,25 @@
310348 #define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_WIDTH 32
311349 /* default value of bitfield rdm_desc_init_i */
312350 #define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_DEFAULT 0x0
351
+
352
+/* rdm_desc_init_done_i bitfield definitions
353
+ * preprocessor definitions for the bitfield rdm_desc_init_done_i.
354
+ * port="pif_rdm_desc_init_done_i"
355
+ */
356
+
357
+/* register address for bitfield rdm_desc_init_done_i */
358
+#define RDM_RX_DMA_DESC_CACHE_INIT_DONE_ADR 0x00005a10
359
+/* bitmask for bitfield rdm_desc_init_done_i */
360
+#define RDM_RX_DMA_DESC_CACHE_INIT_DONE_MSK 0x00000001U
361
+/* inverted bitmask for bitfield rdm_desc_init_done_i */
362
+#define RDM_RX_DMA_DESC_CACHE_INIT_DONE_MSKN 0xfffffffe
363
+/* lower bit position of bitfield  rdm_desc_init_done_i */
364
+#define RDM_RX_DMA_DESC_CACHE_INIT_DONE_SHIFT 0U
365
+/* width of bitfield rdm_desc_init_done_i */
366
+#define RDM_RX_DMA_DESC_CACHE_INIT_DONE_WIDTH 1
367
+/* default value of bitfield rdm_desc_init_done_i */
368
+#define RDM_RX_DMA_DESC_CACHE_INIT_DONE_DEFAULT 0x0
369
+
313370 
314371 /* rx int_desc_wrb_en bitfield definitions
315372  * preprocessor definitions for the bitfield "int_desc_wrb_en".
....@@ -527,6 +584,24 @@
527584 #define HW_ATL_RPB_DMA_SYS_LBK_WIDTH 1
528585 /* default value of bitfield dma_sys_loopback */
529586 #define HW_ATL_RPB_DMA_SYS_LBK_DEFAULT 0x0
587
+
588
+/* rx dma_net_loopback bitfield definitions
589
+ * preprocessor definitions for the bitfield "dma_net_loopback".
590
+ * port="pif_rpb_dma_net_lbk_i"
591
+ */
592
+
593
+/* register address for bitfield dma_net_loopback */
594
+#define HW_ATL_RPB_DMA_NET_LBK_ADR 0x00005000
595
+/* bitmask for bitfield dma_net_loopback */
596
+#define HW_ATL_RPB_DMA_NET_LBK_MSK 0x00000010
597
+/* inverted bitmask for bitfield dma_net_loopback */
598
+#define HW_ATL_RPB_DMA_NET_LBK_MSKN 0xffffffef
599
+/* lower bit position of bitfield dma_net_loopback */
600
+#define HW_ATL_RPB_DMA_NET_LBK_SHIFT 4
601
+/* width of bitfield dma_net_loopback */
602
+#define HW_ATL_RPB_DMA_NET_LBK_WIDTH 1
603
+/* default value of bitfield dma_net_loopback */
604
+#define HW_ATL_RPB_DMA_NET_LBK_DEFAULT 0x0
530605 
531606 /* rx rx_tc_mode bitfield definitions
532607  * preprocessor definitions for the bitfield "rx_tc_mode".
....@@ -1092,24 +1167,43 @@
10921167 /* Default value of bitfield vl_id{F}[B:0] */
10931168 #define HW_ATL_RPF_VL_ID_F_DEFAULT 0x0
10941169 
1095
-/* RX et_en{F} Bitfield Definitions
1096
- * Preprocessor definitions for the bitfield "et_en{F}".
1170
+/* RX vl_rxq_en{F} Bitfield Definitions
1171
+ * Preprocessor definitions for the bitfield "vl_rxq{F}".
10971172  * Parameter: filter {F} | stride size 0x4 | range [0, 15]
1098
- * PORT="pif_rpf_et_en_i[0]"
1173
+ * PORT="pif_rpf_vl_rxq_en_i"
10991174  */
11001175 
1101
-/* Register address for bitfield et_en{F} */
1102
-#define HW_ATL_RPF_ET_EN_F_ADR(filter) (0x00005300 + (filter) * 0x4)
1103
-/* Bitmask for bitfield et_en{F} */
1104
-#define HW_ATL_RPF_ET_EN_F_MSK 0x80000000
1105
-/* Inverted bitmask for bitfield et_en{F} */
1106
-#define HW_ATL_RPF_ET_EN_F_MSKN 0x7FFFFFFF
1107
-/* Lower bit position of bitfield et_en{F} */
1108
-#define HW_ATL_RPF_ET_EN_F_SHIFT 31
1109
-/* Width of bitfield et_en{F} */
1110
-#define HW_ATL_RPF_ET_EN_F_WIDTH 1
1111
-/* Default value of bitfield et_en{F} */
1112
-#define HW_ATL_RPF_ET_EN_F_DEFAULT 0x0
1176
+/* Register address for bitfield vl_rxq_en{F} */
1177
+#define HW_ATL_RPF_VL_RXQ_EN_F_ADR(filter) (0x00005290 + (filter) * 0x4)
1178
+/* Bitmask for bitfield vl_rxq_en{F} */
1179
+#define HW_ATL_RPF_VL_RXQ_EN_F_MSK 0x10000000
1180
+/* Inverted bitmask for bitfield vl_rxq_en{F}[ */
1181
+#define HW_ATL_RPF_VL_RXQ_EN_F_MSKN 0xEFFFFFFF
1182
+/* Lower bit position of bitfield vl_rxq_en{F} */
1183
+#define HW_ATL_RPF_VL_RXQ_EN_F_SHIFT 28
1184
+/* Width of bitfield vl_rxq_en{F} */
1185
+#define HW_ATL_RPF_VL_RXQ_EN_F_WIDTH 1
1186
+/* Default value of bitfield vl_rxq_en{F} */
1187
+#define HW_ATL_RPF_VL_RXQ_EN_F_DEFAULT 0x0
1188
+
1189
+/* RX vl_rxq{F}[4:0] Bitfield Definitions
1190
+ * Preprocessor definitions for the bitfield "vl_rxq{F}[4:0]".
1191
+ * Parameter: filter {F} | stride size 0x4 | range [0, 15]
1192
+ * PORT="pif_rpf_vl_rxq0_i[4:0]"
1193
+ */
1194
+
1195
+/* Register address for bitfield vl_rxq{F}[4:0] */
1196
+#define HW_ATL_RPF_VL_RXQ_F_ADR(filter) (0x00005290 + (filter) * 0x4)
1197
+/* Bitmask for bitfield vl_rxq{F}[4:0] */
1198
+#define HW_ATL_RPF_VL_RXQ_F_MSK 0x01F00000
1199
+/* Inverted bitmask for bitfield vl_rxq{F}[4:0] */
1200
+#define HW_ATL_RPF_VL_RXQ_F_MSKN 0xFE0FFFFF
1201
+/* Lower bit position of bitfield vl_rxq{F}[4:0] */
1202
+#define HW_ATL_RPF_VL_RXQ_F_SHIFT 20
1203
+/* Width of bitfield vl_rxw{F}[4:0] */
1204
+#define HW_ATL_RPF_VL_RXQ_F_WIDTH 5
1205
+/* Default value of bitfield vl_rxq{F}[4:0] */
1206
+#define HW_ATL_RPF_VL_RXQ_F_DEFAULT 0x0
11131207 
11141208 /* rx et_en{f} bitfield definitions
11151209  * preprocessor definitions for the bitfield "et_en{f}".
....@@ -1263,6 +1357,90 @@
12631357 /* default value of bitfield et_val{f}[f:0] */
12641358 #define HW_ATL_RPF_ET_VALF_DEFAULT 0x0
12651359 
1360
+/* RX l3_l4_en{F} Bitfield Definitions
1361
+ * Preprocessor definitions for the bitfield "l3_l4_en{F}".
1362
+ * Parameter: filter {F} | stride size 0x4 | range [0, 7]
1363
+ * PORT="pif_rpf_l3_l4_en_i[0]"
1364
+ */
1365
+
1366
+#define HW_ATL_RPF_L3_REG_CTRL_ADR(filter) (0x00005380 + (filter) * 0x4)
1367
+
1368
+/* RX rpf_l3_sa{D}[1F:0] Bitfield Definitions
1369
+ * Preprocessor definitions for the bitfield "l3_sa{D}[1F:0]".
1370
+ * Parameter: location {D} | stride size 0x4 | range [0, 7]
1371
+ * PORT="pif_rpf_l3_sa0_i[31:0]"
1372
+ */
1373
+
1374
+/* Register address for bitfield pif_rpf_l3_sa0_i[31:0] */
1375
+#define HW_ATL_RPF_L3_SRCA_ADR(filter) (0x000053B0 + (filter) * 0x4)
1376
+/* Bitmask for bitfield l3_sa0[1F:0] */
1377
+#define HW_ATL_RPF_L3_SRCA_MSK 0xFFFFFFFFu
1378
+/* Inverted bitmask for bitfield l3_sa0[1F:0] */
1379
+#define HW_ATL_RPF_L3_SRCA_MSKN 0xFFFFFFFFu
1380
+/* Lower bit position of bitfield l3_sa0[1F:0] */
1381
+#define HW_ATL_RPF_L3_SRCA_SHIFT 0
1382
+/* Width of bitfield l3_sa0[1F:0] */
1383
+#define HW_ATL_RPF_L3_SRCA_WIDTH 32
1384
+/* Default value of bitfield l3_sa0[1F:0] */
1385
+#define HW_ATL_RPF_L3_SRCA_DEFAULT 0x0
1386
+
1387
+/* RX rpf_l3_da{D}[1F:0] Bitfield Definitions
1388
+ * Preprocessor definitions for the bitfield "l3_da{D}[1F:0]".
1389
+ * Parameter: location {D} | stride size 0x4 | range [0, 7]
1390
+ * PORT="pif_rpf_l3_da0_i[31:0]"
1391
+ */
1392
+
1393
+ /* Register address for bitfield pif_rpf_l3_da0_i[31:0] */
1394
+#define HW_ATL_RPF_L3_DSTA_ADR(filter) (0x000053D0 + (filter) * 0x4)
1395
+/* Bitmask for bitfield l3_da0[1F:0] */
1396
+#define HW_ATL_RPF_L3_DSTA_MSK 0xFFFFFFFFu
1397
+/* Inverted bitmask for bitfield l3_da0[1F:0] */
1398
+#define HW_ATL_RPF_L3_DSTA_MSKN 0xFFFFFFFFu
1399
+/* Lower bit position of bitfield l3_da0[1F:0] */
1400
+#define HW_ATL_RPF_L3_DSTA_SHIFT 0
1401
+/* Width of bitfield l3_da0[1F:0] */
1402
+#define HW_ATL_RPF_L3_DSTA_WIDTH 32
1403
+/* Default value of bitfield l3_da0[1F:0] */
1404
+#define HW_ATL_RPF_L3_DSTA_DEFAULT 0x0
1405
+
1406
+/* RX l4_sp{D}[F:0] Bitfield Definitions
1407
+ * Preprocessor definitions for the bitfield "l4_sp{D}[F:0]".
1408
+ * Parameter: srcport {D} | stride size 0x4 | range [0, 7]
1409
+ * PORT="pif_rpf_l4_sp0_i[15:0]"
1410
+ */
1411
+
1412
+/* Register address for bitfield l4_sp{D}[F:0] */
1413
+#define HW_ATL_RPF_L4_SPD_ADR(srcport) (0x00005400u + (srcport) * 0x4)
1414
+/* Bitmask for bitfield l4_sp{D}[F:0] */
1415
+#define HW_ATL_RPF_L4_SPD_MSK 0x0000FFFFu
1416
+/* Inverted bitmask for bitfield l4_sp{D}[F:0] */
1417
+#define HW_ATL_RPF_L4_SPD_MSKN 0xFFFF0000u
1418
+/* Lower bit position of bitfield l4_sp{D}[F:0] */
1419
+#define HW_ATL_RPF_L4_SPD_SHIFT 0
1420
+/* Width of bitfield l4_sp{D}[F:0] */
1421
+#define HW_ATL_RPF_L4_SPD_WIDTH 16
1422
+/* Default value of bitfield l4_sp{D}[F:0] */
1423
+#define HW_ATL_RPF_L4_SPD_DEFAULT 0x0
1424
+
1425
+/* RX l4_dp{D}[F:0] Bitfield Definitions
1426
+ * Preprocessor definitions for the bitfield "l4_dp{D}[F:0]".
1427
+ * Parameter: destport {D} | stride size 0x4 | range [0, 7]
1428
+ * PORT="pif_rpf_l4_dp0_i[15:0]"
1429
+ */
1430
+
1431
+/* Register address for bitfield l4_dp{D}[F:0] */
1432
+#define HW_ATL_RPF_L4_DPD_ADR(destport) (0x00005420u + (destport) * 0x4)
1433
+/* Bitmask for bitfield l4_dp{D}[F:0] */
1434
+#define HW_ATL_RPF_L4_DPD_MSK 0x0000FFFFu
1435
+/* Inverted bitmask for bitfield l4_dp{D}[F:0] */
1436
+#define HW_ATL_RPF_L4_DPD_MSKN 0xFFFF0000u
1437
+/* Lower bit position of bitfield l4_dp{D}[F:0] */
1438
+#define HW_ATL_RPF_L4_DPD_SHIFT 0
1439
+/* Width of bitfield l4_dp{D}[F:0] */
1440
+#define HW_ATL_RPF_L4_DPD_WIDTH 16
1441
+/* Default value of bitfield l4_dp{D}[F:0] */
1442
+#define HW_ATL_RPF_L4_DPD_DEFAULT 0x0
1443
+
12661444 /* rx ipv4_chk_en bitfield definitions
12671445  * preprocessor definitions for the bitfield "ipv4_chk_en".
12681446  * port="pif_rpo_ipv4_chk_en_i"
....@@ -1318,6 +1496,24 @@
13181496 #define HW_ATL_RPOL4CHK_EN_WIDTH 1
13191497 /* default value of bitfield l4_chk_en */
13201498 #define HW_ATL_RPOL4CHK_EN_DEFAULT 0x0
1499
+
1500
+/* RX outer_vl_ins_mode Bitfield Definitions
1501
+ * Preprocessor definitions for the bitfield "outer_vl_ins_mode".
1502
+ * PORT="pif_rpo_outer_vl_mode_i"
1503
+ */
1504
+
1505
+/* Register address for bitfield outer_vl_ins_mode */
1506
+#define HW_ATL_RPO_OUTER_VL_INS_MODE_ADR 0x00005580
1507
+/* Bitmask for bitfield outer_vl_ins_mode */
1508
+#define HW_ATL_RPO_OUTER_VL_INS_MODE_MSK 0x00000004
1509
+/* Inverted bitmask for bitfield outer_vl_ins_mode */
1510
+#define HW_ATL_RPO_OUTER_VL_INS_MODE_MSKN 0xFFFFFFFB
1511
+/* Lower bit position of bitfield outer_vl_ins_mode */
1512
+#define HW_ATL_RPO_OUTER_VL_INS_MODE_SHIFT 2
1513
+/* Width of bitfield outer_vl_ins_mode */
1514
+#define HW_ATL_RPO_OUTER_VL_INS_MODE_WIDTH 1
1515
+/* Default value of bitfield outer_vl_ins_mode */
1516
+#define HW_ATL_RPO_OUTER_VL_INS_MODE_DEFAULT 0x0
13211517 
13221518 /* rx reg_res_dsbl bitfield definitions
13231519  * preprocessor definitions for the bitfield "reg_res_dsbl".
....@@ -1873,6 +2069,42 @@
18732069 /* default value of bitfield lso_tcp_flag_mid[b:0] */
18742070 #define HW_ATL_THM_LSO_TCP_FLAG_MID_DEFAULT 0x0
18752071 
2072
+/* tx tx_tc_mode bitfield definitions
2073
+ * preprocessor definitions for the bitfield "tx_tc_mode".
2074
+ * port="pif_tpb_tx_tc_mode_i,pif_tps_tx_tc_mode_i"
2075
+ */
2076
+
2077
+/* register address for bitfield tx_tc_mode */
2078
+#define HW_ATL_TPB_TX_TC_MODE_ADDR 0x00007900
2079
+/* bitmask for bitfield tx_tc_mode */
2080
+#define HW_ATL_TPB_TX_TC_MODE_MSK 0x00000100
2081
+/* inverted bitmask for bitfield tx_tc_mode */
2082
+#define HW_ATL_TPB_TX_TC_MODE_MSKN 0xFFFFFEFF
2083
+/* lower bit position of bitfield tx_tc_mode */
2084
+#define HW_ATL_TPB_TX_TC_MODE_SHIFT 8
2085
+/* width of bitfield tx_tc_mode */
2086
+#define HW_ATL_TPB_TX_TC_MODE_WIDTH 1
2087
+/* default value of bitfield tx_tc_mode */
2088
+#define HW_ATL_TPB_TX_TC_MODE_DEFAULT 0x0
2089
+
2090
+/* tx tx_desc_rate_mode bitfield definitions
2091
+ * preprocessor definitions for the bitfield "tx_desc_rate_mode".
2092
+ * port="pif_tps_desc_rate_mode_i"
2093
+ */
2094
+
2095
+/* register address for bitfield tx_desc_rate_mode */
2096
+#define HW_ATL_TPS_TX_DESC_RATE_MODE_ADR 0x00007900
2097
+/* bitmask for bitfield tx_desc_rate_mode */
2098
+#define HW_ATL_TPS_TX_DESC_RATE_MODE_MSK 0x00000080
2099
+/* inverted bitmask for bitfield tx_desc_rate_mode */
2100
+#define HW_ATL_TPS_TX_DESC_RATE_MODE_MSKN 0xFFFFFF7F
2101
+/* lower bit position of bitfield tx_desc_rate_mode */
2102
+#define HW_ATL_TPS_TX_DESC_RATE_MODE_SHIFT 7
2103
+/* width of bitfield tx_desc_rate_mode */
2104
+#define HW_ATL_TPS_TX_DESC_RATE_MODE_WIDTH 1
2105
+/* default value of bitfield tx_desc_rate_mode */
2106
+#define HW_ATL_TPS_TX_DESC_RATE_MODE_DEFAULT 0x0
2107
+
18762108 /* tx tx_buf_en bitfield definitions
18772109  * preprocessor definitions for the bitfield "tx_buf_en".
18782110  * port="pif_tpb_tx_buf_en_i"
....@@ -1947,6 +2179,24 @@
19472179 /* default value of bitfield dma_sys_loopback */
19482180 #define HW_ATL_TPB_DMA_SYS_LBK_DEFAULT 0x0
19492181 
2182
+/* tx dma_net_loopback bitfield definitions
2183
+ * preprocessor definitions for the bitfield "dma_net_loopback".
2184
+ * port="pif_tpb_dma_net_lbk_i"
2185
+ */
2186
+
2187
+/* register address for bitfield dma_net_loopback */
2188
+#define HW_ATL_TPB_DMA_NET_LBK_ADR 0x00007000
2189
+/* bitmask for bitfield dma_net_loopback */
2190
+#define HW_ATL_TPB_DMA_NET_LBK_MSK 0x00000010
2191
+/* inverted bitmask for bitfield dma_net_loopback */
2192
+#define HW_ATL_TPB_DMA_NET_LBK_MSKN 0xffffffef
2193
+/* lower bit position of bitfield dma_net_loopback */
2194
+#define HW_ATL_TPB_DMA_NET_LBK_SHIFT 4
2195
+/* width of bitfield dma_net_loopback */
2196
+#define HW_ATL_TPB_DMA_NET_LBK_WIDTH 1
2197
+/* default value of bitfield dma_net_loopback */
2198
+#define HW_ATL_TPB_DMA_NET_LBK_DEFAULT 0x0
2199
+
19502200 /* tx tx{b}_buf_size[7:0] bitfield definitions
19512201  * preprocessor definitions for the bitfield "tx{b}_buf_size[7:0]".
19522202  * parameter: buffer {b} | stride size 0x10 | range [0, 7]
....@@ -1983,6 +2233,24 @@
19832233 #define HW_ATL_TPB_TX_SCP_INS_EN_WIDTH 1
19842234 /* default value of bitfield tx_scp_ins_en */
19852235 #define HW_ATL_TPB_TX_SCP_INS_EN_DEFAULT 0x0
2236
+
2237
+/* tx tx_clk_gate_en bitfield definitions
2238
+ * preprocessor definitions for the bitfield "tx_clk_gate_en".
2239
+ * port="pif_tpb_clk_gate_en_i"
2240
+ */
2241
+
2242
+/* register address for bitfield tx_clk_gate_en */
2243
+#define HW_ATL_TPB_TX_CLK_GATE_EN_ADR 0x00007900
2244
+/* bitmask for bitfield tx_clk_gate_en */
2245
+#define HW_ATL_TPB_TX_CLK_GATE_EN_MSK 0x00000010
2246
+/* inverted bitmask for bitfield tx_clk_gate_en */
2247
+#define HW_ATL_TPB_TX_CLK_GATE_EN_MSKN 0xffffffef
2248
+/* lower bit position of bitfield tx_clk_gate_en */
2249
+#define HW_ATL_TPB_TX_CLK_GATE_EN_SHIFT 4
2250
+/* width of bitfield tx_clk_gate_en */
2251
+#define HW_ATL_TPB_TX_CLK_GATE_EN_WIDTH 1
2252
+/* default value of bitfield tx_clk_gate_en */
2253
+#define HW_ATL_TPB_TX_CLK_GATE_EN_DEFAULT 0x1
19862254 
19872255 /* tx ipv4_chk_en bitfield definitions
19882256  * preprocessor definitions for the bitfield "ipv4_chk_en".
....@@ -2055,6 +2323,58 @@
20552323 #define HW_ATL_TPS_DATA_TC_ARB_MODE_WIDTH 1
20562324 /* default value of bitfield data_tc_arb_mode */
20572325 #define HW_ATL_TPS_DATA_TC_ARB_MODE_DEFAULT 0x0
2326
+
2327
+/* tx desc{r}_rate_en bitfield definitions
2328
+ * preprocessor definitions for the bitfield "desc{r}_rate_en".
2329
+ * port="pif_tps_desc_rate_en_i[0]"
2330
+ */
2331
+
2332
+/* register address for bitfield desc{r}_rate_en */
2333
+#define HW_ATL_TPS_DESC_RATE_EN_ADR(desc) (0x00007408 + (desc) * 0x10)
2334
+/* bitmask for bitfield desc{r}_rate_en */
2335
+#define HW_ATL_TPS_DESC_RATE_EN_MSK 0x80000000
2336
+/* inverted bitmask for bitfield desc{r}_rate_en */
2337
+#define HW_ATL_TPS_DESC_RATE_EN_MSKN 0x7FFFFFFF
2338
+/* lower bit position of bitfield desc{r}_rate_en */
2339
+#define HW_ATL_TPS_DESC_RATE_EN_SHIFT 31
2340
+/* width of bitfield desc{r}_rate_en */
2341
+#define HW_ATL_TPS_DESC_RATE_EN_WIDTH 1
2342
+/* default value of bitfield desc{r}_rate_en */
2343
+#define HW_ATL_TPS_DESC_RATE_EN_DEFAULT 0x0
2344
+
2345
+/* tx desc{r}_rate_x bitfield definitions
2346
+ * preprocessor definitions for the bitfield "desc{r}_rate_x".
2347
+ * port="pif_tps_desc0_rate_x"
2348
+ */
2349
+/* register address for bitfield desc{r}_rate_x */
2350
+#define HW_ATL_TPS_DESC_RATE_X_ADR(desc) (0x00007408 + (desc) * 0x10)
2351
+/* bitmask for bitfield desc{r}_rate_x */
2352
+#define HW_ATL_TPS_DESC_RATE_X_MSK 0x03FF0000
2353
+/* inverted bitmask for bitfield desc{r}_rate_x */
2354
+#define HW_ATL_TPS_DESC_RATE_X_MSKN 0xFC00FFFF
2355
+/* lower bit position of bitfield desc{r}_rate_x */
2356
+#define HW_ATL_TPS_DESC_RATE_X_SHIFT 16
2357
+/* width of bitfield desc{r}_rate_x */
2358
+#define HW_ATL_TPS_DESC_RATE_X_WIDTH 10
2359
+/* default value of bitfield desc{r}_rate_x */
2360
+#define HW_ATL_TPS_DESC_RATE_X_DEFAULT 0x0
2361
+
2362
+/* tx desc{r}_rate_y bitfield definitions
2363
+ * preprocessor definitions for the bitfield "desc{r}_rate_y".
2364
+ * port="pif_tps_desc0_rate_y"
2365
+ */
2366
+/* register address for bitfield desc{r}_rate_y */
2367
+#define HW_ATL_TPS_DESC_RATE_Y_ADR(desc) (0x00007408 + (desc) * 0x10)
2368
+/* bitmask for bitfield desc{r}_rate_y */
2369
+#define HW_ATL_TPS_DESC_RATE_Y_MSK 0x00003FFF
2370
+/* inverted bitmask for bitfield desc{r}_rate_y */
2371
+#define HW_ATL_TPS_DESC_RATE_Y_MSKN 0xFFFFC000
2372
+/* lower bit position of bitfield desc{r}_rate_y */
2373
+#define HW_ATL_TPS_DESC_RATE_Y_SHIFT 0
2374
+/* width of bitfield desc{r}_rate_y */
2375
+#define HW_ATL_TPS_DESC_RATE_Y_WIDTH 14
2376
+/* default value of bitfield desc{r}_rate_y */
2377
+#define HW_ATL_TPS_DESC_RATE_Y_DEFAULT 0x0
20582378 
20592379 /* tx desc_rate_ta_rst bitfield definitions
20602380  * preprocessor definitions for the bitfield "desc_rate_ta_rst".
....@@ -2326,6 +2646,22 @@
23262646 /* default value of bitfield register write strobe */
23272647 #define HW_ATL_MSM_REG_WR_STROBE_DEFAULT 0x0
23282648 
2649
+/* register address for bitfield PTP Digital Clock Read Enable */
2650
+#define HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_ADR 0x00004628
2651
+/* bitmask for bitfield PTP Digital Clock Read Enable */
2652
+#define HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_MSK 0x00000010
2653
+/* inverted bitmask for bitfield PTP Digital Clock Read Enable */
2654
+#define HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_MSKN 0xFFFFFFEF
2655
+/* lower bit position of bitfield PTP Digital Clock Read Enable */
2656
+#define HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_SHIFT 4
2657
+/* width of bitfield PTP Digital Clock Read Enable */
2658
+#define HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_WIDTH 1
2659
+/* default value of bitfield PTP Digital Clock Read Enable */
2660
+#define HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_DEFAULT 0x0
2661
+
2662
+/* register address for ptp counter reading */
2663
+#define HW_ATL_PCS_PTP_TS_VAL_ADDR(index) (0x00004900 + (index) * 0x4)
2664
+
23292665 /* mif soft reset bitfield definitions
23302666  * preprocessor definitions for the bitfield "soft reset".
23312667  * port="pif_glb_res_i"
....@@ -2418,4 +2754,125 @@
24182754 /* default value of bitfield uP Force Interrupt */
24192755 #define HW_ATL_MCP_UP_FORCE_INTERRUPT_DEFAULT 0x0
24202756 
2757
+/* Preprocessor definitions for Global MDIO Interfaces
2758
+ * Address: 0x00000280 + 0x4 * Number of interface
2759
+ */
2760
+#define HW_ATL_GLB_MDIO_IFACE_ADDR_BEGIN   0x00000280u
2761
+
2762
+#define HW_ATL_GLB_MDIO_IFACE_N_ADR(number) \
2763
+	(HW_ATL_GLB_MDIO_IFACE_ADDR_BEGIN + (((number) - 1) * 0x4))
2764
+
2765
+/* MIF MDIO Busy Bitfield Definitions
2766
+ * Preprocessor definitions for the bitfield "MDIO Busy".
2767
+ * PORT="mdio_pif_busy_o"
2768
+ */
2769
+
2770
+/* Register address for bitfield MDIO Busy */
2771
+#define HW_ATL_MDIO_BUSY_ADR 0x00000284
2772
+/* Bitmask for bitfield MDIO Busy */
2773
+#define HW_ATL_MDIO_BUSY_MSK 0x80000000
2774
+/* Inverted bitmask for bitfield MDIO Busy */
2775
+#define HW_ATL_MDIO_BUSY_MSKN 0x7FFFFFFF
2776
+/* Lower bit position of bitfield MDIO Busy */
2777
+#define HW_ATL_MDIO_BUSY_SHIFT 31
2778
+/* Width of bitfield MDIO Busy */
2779
+#define HW_ATL_MDIO_BUSY_WIDTH 1
2780
+
2781
+/* MIF MDIO Execute Operation Bitfield Definitions
2782
+ * Preprocessor definitions for the bitfield "MDIO Execute Operation".
2783
+ * PORT="pif_mdio_op_start_i"
2784
+ */
2785
+
2786
+/* Register address for bitfield MDIO Execute Operation */
2787
+#define HW_ATL_MDIO_EXECUTE_OPERATION_ADR 0x00000284
2788
+/* Bitmask for bitfield MDIO Execute Operation */
2789
+#define HW_ATL_MDIO_EXECUTE_OPERATION_MSK 0x00008000
2790
+/* Inverted bitmask for bitfield MDIO Execute Operation */
2791
+#define HW_ATL_MDIO_EXECUTE_OPERATION_MSKN 0xFFFF7FFF
2792
+/* Lower bit position of bitfield MDIO Execute Operation */
2793
+#define HW_ATL_MDIO_EXECUTE_OPERATION_SHIFT 15
2794
+/* Width of bitfield MDIO Execute Operation */
2795
+#define HW_ATL_MDIO_EXECUTE_OPERATION_WIDTH 1
2796
+/* Default value of bitfield MDIO Execute Operation */
2797
+#define HW_ATL_MDIO_EXECUTE_OPERATION_DEFAULT 0x0
2798
+
2799
+/* MIF Op Mode [1:0] Bitfield Definitions
2800
+ * Preprocessor definitions for the bitfield "Op Mode [1:0]".
2801
+ * PORT="pif_mdio_mode_i[1:0]"
2802
+ */
2803
+
2804
+/* Register address for bitfield Op Mode [1:0] */
2805
+#define HW_ATL_MDIO_OP_MODE_ADR 0x00000284
2806
+/* Bitmask for bitfield Op Mode [1:0] */
2807
+#define HW_ATL_MDIO_OP_MODE_MSK 0x00003000
2808
+/* Inverted bitmask for bitfield Op Mode [1:0] */
2809
+#define HW_ATL_MDIO_OP_MODE_MSKN 0xFFFFCFFF
2810
+/* Lower bit position of bitfield Op Mode [1:0] */
2811
+#define HW_ATL_MDIO_OP_MODE_SHIFT 12
2812
+/* Width of bitfield Op Mode [1:0] */
2813
+#define HW_ATL_MDIO_OP_MODE_WIDTH 2
2814
+/* Default value of bitfield Op Mode [1:0] */
2815
+#define HW_ATL_MDIO_OP_MODE_DEFAULT 0x0
2816
+
2817
+/* MIF PHY address Bitfield Definitions
2818
+ * Preprocessor definitions for the bitfield "PHY address".
2819
+ * PORT="pif_mdio_phy_addr_i[9:0]"
2820
+ */
2821
+
2822
+/* Register address for bitfield PHY address */
2823
+#define HW_ATL_MDIO_PHY_ADDRESS_ADR 0x00000284
2824
+/* Bitmask for bitfield PHY address */
2825
+#define HW_ATL_MDIO_PHY_ADDRESS_MSK 0x000003FF
2826
+/* Inverted bitmask for bitfield PHY address */
2827
+#define HW_ATL_MDIO_PHY_ADDRESS_MSKN 0xFFFFFC00
2828
+/* Lower bit position of bitfield PHY address */
2829
+#define HW_ATL_MDIO_PHY_ADDRESS_SHIFT 0
2830
+/* Width of bitfield PHY address */
2831
+#define HW_ATL_MDIO_PHY_ADDRESS_WIDTH 10
2832
+/* Default value of bitfield PHY address */
2833
+#define HW_ATL_MDIO_PHY_ADDRESS_DEFAULT 0x0
2834
+
2835
+/* MIF MDIO WriteData [F:0] Bitfield Definitions
2836
+ * Preprocessor definitions for the bitfield "MDIO WriteData [F:0]".
2837
+ * PORT="pif_mdio_wdata_i[15:0]"
2838
+ */
2839
+
2840
+/* Register address for bitfield MDIO WriteData [F:0] */
2841
+#define HW_ATL_MDIO_WRITE_DATA_ADR 0x00000288
2842
+/* Bitmask for bitfield MDIO WriteData [F:0] */
2843
+#define HW_ATL_MDIO_WRITE_DATA_MSK 0x0000FFFF
2844
+/* Inverted bitmask for bitfield MDIO WriteData [F:0] */
2845
+#define HW_ATL_MDIO_WRITE_DATA_MSKN 0xFFFF0000
2846
+/* Lower bit position of bitfield MDIO WriteData [F:0] */
2847
+#define HW_ATL_MDIO_WRITE_DATA_SHIFT 0
2848
+/* Width of bitfield MDIO WriteData [F:0] */
2849
+#define HW_ATL_MDIO_WRITE_DATA_WIDTH 16
2850
+/* Default value of bitfield MDIO WriteData [F:0] */
2851
+#define HW_ATL_MDIO_WRITE_DATA_DEFAULT 0x0
2852
+
2853
+/* MIF MDIO Address [F:0] Bitfield Definitions
2854
+ * Preprocessor definitions for the bitfield "MDIO Address [F:0]".
2855
+ * PORT="pif_mdio_addr_i[15:0]"
2856
+ */
2857
+
2858
+/* Register address for bitfield MDIO Address [F:0] */
2859
+#define HW_ATL_MDIO_ADDRESS_ADR 0x0000028C
2860
+/* Bitmask for bitfield MDIO Address [F:0] */
2861
+#define HW_ATL_MDIO_ADDRESS_MSK 0x0000FFFF
2862
+/* Inverted bitmask for bitfield MDIO Address [F:0] */
2863
+#define HW_ATL_MDIO_ADDRESS_MSKN 0xFFFF0000
2864
+/* Lower bit position of bitfield MDIO Address [F:0] */
2865
+#define HW_ATL_MDIO_ADDRESS_SHIFT 0
2866
+/* Width of bitfield MDIO Address [F:0] */
2867
+#define HW_ATL_MDIO_ADDRESS_WIDTH 16
2868
+/* Default value of bitfield MDIO Address [F:0] */
2869
+#define HW_ATL_MDIO_ADDRESS_DEFAULT 0x0
2870
+
2871
+#define HW_ATL_MIF_RESET_TIMEOUT_ADR 0x00000348
2872
+
2873
+#define HW_ATL_FW_SM_MDIO       0x0U
2874
+#define HW_ATL_FW_SM_RAM        0x2U
2875
+#define HW_ATL_FW_SM_RESET1     0x3U
2876
+#define HW_ATL_FW_SM_RESET2     0x4U
2877
+
24212878 #endif /* HW_ATL_LLH_INTERNAL_H */