change wifi driver to cypress

hc

2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390

 kernel/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h
..
..
@@ -1,10 +1,8 @@
1
-/*
2
- * aQuantia Corporation Network Driver
3
- * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
1
+/* SPDX-License-Identifier: GPL-2.0-only */
2
+/* Atlantic Network Driver
4
3
  *
5
- * This program is free software; you can redistribute it and/or modify it
6
- * under the terms and conditions of the GNU General Public License,
7
- * version 2, as published by the Free Software Foundation.
4
+ * Copyright (C) 2014-2019 aQuantia Corporation
5
+ * Copyright (C) 2019-2020 Marvell International Ltd.
8
6
  */
9
7
 
10
8
 /* File hw_atl_llh.h: Declarations of bitfield and register access functions for
..
..
@@ -17,6 +15,24 @@
17
15
 #include <linux/types.h>
18
16
 
19
17
 struct aq_hw_s;
18
+
19
+/* set temperature sense reset */
20
+void hw_atl_ts_reset_set(struct aq_hw_s *aq_hw, u32 val);
21
+
22
+/* set temperature sense power down */
23
+void hw_atl_ts_power_down_set(struct aq_hw_s *aq_hw, u32 val);
24
+
25
+/* get temperature sense power down */
26
+u32 hw_atl_ts_power_down_get(struct aq_hw_s *aq_hw);
27
+
28
+/* get temperature sense ready */
29
+u32 hw_atl_ts_ready_get(struct aq_hw_s *aq_hw);
30
+
31
+/* get temperature sense ready latch high */
32
+u32 hw_atl_ts_ready_latch_high_get(struct aq_hw_s *aq_hw);
33
+
34
+/* get temperature sense data */
35
+u32 hw_atl_ts_data_get(struct aq_hw_s *aq_hw);
20
36
 
21
37
 /* global */
22
38
 
..
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@@ -40,29 +56,17 @@
40
56
 
41
57
 u32 hw_atl_rpb_rx_dma_drop_pkt_cnt_get(struct aq_hw_s *aq_hw);
42
58
 
43
-/* get rx dma good octet counter lsw */
44
-u32 hw_atl_stats_rx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw);
59
+/* get rx dma good octet counter */
60
+u64 hw_atl_stats_rx_dma_good_octet_counter_get(struct aq_hw_s *aq_hw);
45
61
 
46
-/* get rx dma good packet counter lsw */
47
-u32 hw_atl_stats_rx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw);
62
+/* get rx dma good packet counter */
63
+u64 hw_atl_stats_rx_dma_good_pkt_counter_get(struct aq_hw_s *aq_hw);
48
64
 
49
-/* get tx dma good octet counter lsw */
50
-u32 hw_atl_stats_tx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw);
65
+/* get tx dma good octet counter */
66
+u64 hw_atl_stats_tx_dma_good_octet_counter_get(struct aq_hw_s *aq_hw);
51
67
 
52
-/* get tx dma good packet counter lsw */
53
-u32 hw_atl_stats_tx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw);
54
-
55
-/* get rx dma good octet counter msw */
56
-u32 hw_atl_stats_rx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw);
57
-
58
-/* get rx dma good packet counter msw */
59
-u32 hw_atl_stats_rx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw);
60
-
61
-/* get tx dma good octet counter msw */
62
-u32 hw_atl_stats_tx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw);
63
-
64
-/* get tx dma good packet counter msw */
65
-u32 hw_atl_stats_tx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw);
68
+/* get tx dma good packet counter */
69
+u64 hw_atl_stats_tx_dma_good_pkt_counter_get(struct aq_hw_s *aq_hw);
66
70
 
67
71
 /* get msm rx errors counter register */
68
72
 u32 hw_atl_reg_mac_msm_rx_errs_cnt_get(struct aq_hw_s *aq_hw);
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@@ -81,9 +85,6 @@
81
85
 
82
86
 /* get msm rx unicast octets counter register 0 */
83
87
 u32 hw_atl_reg_mac_msm_rx_ucst_octets_counter0get(struct aq_hw_s *aq_hw);
84
-
85
-/* get rx dma statistics counter 7 */
86
-u32 hw_atl_reg_rx_dma_stat_counter7get(struct aq_hw_s *aq_hw);
87
88
 
88
89
 /* get msm tx errors counter register */
89
90
 u32 hw_atl_reg_mac_msm_tx_errs_cnt_get(struct aq_hw_s *aq_hw);
..
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@@ -151,6 +152,12 @@
151
152
 
152
153
 /* set reset interrupt */
153
154
 void hw_atl_itr_res_irq_set(struct aq_hw_s *aq_hw, u32 res_irq);
155
+
156
+/* set RSC interrupt */
157
+void hw_atl_itr_rsc_en_set(struct aq_hw_s *aq_hw, u32 enable);
158
+
159
+/* set RSC delay */
160
+void hw_atl_itr_rsc_delay_set(struct aq_hw_s *aq_hw, u32 delay);
154
161
 
155
162
 /* rdm */
156
163
 
..
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@@ -300,9 +307,15 @@
300
307
 /* set dma system loopback */
301
308
 void hw_atl_rpb_dma_sys_lbk_set(struct aq_hw_s *aq_hw, u32 dma_sys_lbk);
302
309
 
310
+/* set dma network loopback */
311
+void hw_atl_rpb_dma_net_lbk_set(struct aq_hw_s *aq_hw, u32 dma_net_lbk);
312
+
303
313
 /* set rx traffic class mode */
304
314
 void hw_atl_rpb_rpf_rx_traf_class_mode_set(struct aq_hw_s *aq_hw,
305
315
 					   u32 rx_traf_class_mode);
316
+
317
+/* get rx traffic class mode */
318
+u32 hw_atl_rpb_rpf_rx_traf_class_mode_get(struct aq_hw_s *aq_hw);
306
319
 
307
320
 /* set rx buffer enable */
308
321
 void hw_atl_rpb_rx_buff_en_set(struct aq_hw_s *aq_hw, u32 rx_buff_en);
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@@ -318,18 +331,23 @@
318
331
 					 u32 buffer);
319
332
 
320
333
 /* set rx flow control mode */
321
-void hw_atl_rpb_rx_flow_ctl_mode_set(struct aq_hw_s *aq_hw, u32 rx_flow_ctl_mode);
334
+void hw_atl_rpb_rx_flow_ctl_mode_set(struct aq_hw_s *aq_hw,
335
+				     u32 rx_flow_ctl_mode);
322
336
 
323
337
 /* set rx packet buffer size (per tc) */
324
338
 void hw_atl_rpb_rx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
325
339
 					    u32 rx_pkt_buff_size_per_tc,
326
340
 					    u32 buffer);
327
341
 
328
-/* set rdm rx dma descriptor cache init */
329
-void hw_atl_rdm_rx_dma_desc_cache_init_set(struct aq_hw_s *aq_hw, u32 init);
342
+/* toggle rdm rx dma descriptor cache init */
343
+void hw_atl_rdm_rx_dma_desc_cache_init_tgl(struct aq_hw_s *aq_hw);
344
+
345
+/* get rdm rx dma descriptor cache init done */
346
+u32 hw_atl_rdm_rx_dma_desc_cache_init_done_get(struct aq_hw_s *aq_hw);
330
347
 
331
348
 /* set rx xoff enable (per tc) */
332
-void hw_atl_rpb_rx_xoff_en_per_tc_set(struct aq_hw_s *aq_hw, u32 rx_xoff_en_per_tc,
349
+void hw_atl_rpb_rx_xoff_en_per_tc_set(struct aq_hw_s *aq_hw,
350
+				      u32 rx_xoff_en_per_tc,
333
351
 				      u32 buffer);
334
352
 
335
353
 /* rpf */
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@@ -349,6 +367,9 @@
349
367
 void hw_atl_rpfl2multicast_flr_en_set(struct aq_hw_s *aq_hw,
350
368
 				      u32 l2multicast_flr_en,
351
369
 				      u32 filter);
370
+
371
+/* get l2 promiscuous mode enable */
372
+u32 hw_atl_rpfl2promiscuous_mode_en_get(struct aq_hw_s *aq_hw);
352
373
 
353
374
 /* set l2 promiscuous mode enable */
354
375
 void hw_atl_rpfl2promiscuous_mode_en_set(struct aq_hw_s *aq_hw,
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@@ -421,6 +442,9 @@
421
442
 void hw_atl_rpf_vlan_prom_mode_en_set(struct aq_hw_s *aq_hw,
422
443
 				      u32 vlan_prom_mode_en);
423
444
 
445
+/* Get VLAN promiscuous mode enable */
446
+u32 hw_atl_rpf_vlan_prom_mode_en_get(struct aq_hw_s *aq_hw);
447
+
424
448
 /* Set VLAN untagged action */
425
449
 void hw_atl_rpf_vlan_untagged_act_set(struct aq_hw_s *aq_hw,
426
450
 				      u32 vlan_untagged_act);
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@@ -440,6 +464,14 @@
440
464
 /* Set VLAN ID Filter */
441
465
 void hw_atl_rpf_vlan_id_flr_set(struct aq_hw_s *aq_hw, u32 vlan_id_flr,
442
466
 				u32 filter);
467
+
468
+/* Set VLAN RX queue assignment enable */
469
+void hw_atl_rpf_vlan_rxq_en_flr_set(struct aq_hw_s *aq_hw, u32 vlan_rxq_en,
470
+				    u32 filter);
471
+
472
+/* Set VLAN RX queue */
473
+void hw_atl_rpf_vlan_rxq_flr_set(struct aq_hw_s *aq_hw, u32 vlan_rxq,
474
+				 u32 filter);
443
475
 
444
476
 /* set ethertype filter enable */
445
477
 void hw_atl_rpf_etht_flr_en_set(struct aq_hw_s *aq_hw, u32 etht_flr_en,
..
..
@@ -475,6 +507,12 @@
475
507
 /* set ethertype filter */
476
508
 void hw_atl_rpf_etht_flr_set(struct aq_hw_s *aq_hw, u32 etht_flr, u32 filter);
477
509
 
510
+/* set L4 source port */
511
+void hw_atl_rpf_l4_spd_set(struct aq_hw_s *aq_hw, u32 val, u32 filter);
512
+
513
+/* set L4 destination port */
514
+void hw_atl_rpf_l4_dpd_set(struct aq_hw_s *aq_hw, u32 val, u32 filter);
515
+
478
516
 /* rpo */
479
517
 
480
518
 /* set ipv4 header checksum offload enable */
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@@ -485,6 +523,11 @@
485
523
 void hw_atl_rpo_rx_desc_vlan_stripping_set(struct aq_hw_s *aq_hw,
486
524
 					   u32 rx_desc_vlan_stripping,
487
525
 					   u32 descriptor);
526
+
527
+void hw_atl_rpo_outer_vlan_tag_mode_set(void *context,
528
+					u32 outervlantagmode);
529
+
530
+u32 hw_atl_rpo_outer_vlan_tag_mode_get(void *context);
488
531
 
489
532
 /* set tcp/udp checksum offload enable */
490
533
 void hw_atl_rpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
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..
@@ -591,6 +634,13 @@
591
634
 
592
635
 /* tpb */
593
636
 
637
+/* set TX Traffic Class Mode */
638
+void hw_atl_tpb_tps_tx_tc_mode_set(struct aq_hw_s *aq_hw,
639
+				   u32 tx_traf_class_mode);
640
+
641
+/* get TX Traffic Class Mode */
642
+u32 hw_atl_tpb_tps_tx_tc_mode_get(struct aq_hw_s *aq_hw);
643
+
594
644
 /* set tx buffer enable */
595
645
 void hw_atl_tpb_tx_buff_en_set(struct aq_hw_s *aq_hw, u32 tx_buff_en);
596
646
 
..
..
@@ -607,9 +657,18 @@
607
657
 /* set tx dma system loopback enable */
608
658
 void hw_atl_tpb_tx_dma_sys_lbk_en_set(struct aq_hw_s *aq_hw, u32 tx_dma_sys_lbk_en);
609
659
 
660
+/* set tx dma network loopback enable */
661
+void hw_atl_tpb_tx_dma_net_lbk_en_set(struct aq_hw_s *aq_hw,
662
+				      u32 tx_dma_net_lbk_en);
663
+
664
+/* set tx clock gating enable */
665
+void hw_atl_tpb_tx_tx_clk_gate_en_set(struct aq_hw_s *aq_hw,
666
+				      u32 tx_clk_gate_en);
667
+
610
668
 /* set tx packet buffer size (per tc) */
611
669
 void hw_atl_tpb_tx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
612
-					    u32 tx_pkt_buff_size_per_tc, u32 buffer);
670
+					    u32 tx_pkt_buff_size_per_tc,
671
+					    u32 buffer);
613
672
 
614
673
 /* set tx path pad insert enable */
615
674
 void hw_atl_tpb_tx_path_scp_ins_en_set(struct aq_hw_s *aq_hw, u32 tx_path_scp_ins_en);
..
..
@@ -648,13 +707,13 @@
648
707
 
649
708
 /* set tx packet scheduler descriptor tc max credit */
650
709
 void hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(struct aq_hw_s *aq_hw,
651
-						   u32 max_credit,
652
-					    u32 tc);
710
+						   const u32 tc,
711
+						   const u32 max_credit);
653
712
 
654
713
 /* set tx packet scheduler descriptor tc weight */
655
714
 void hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(struct aq_hw_s *aq_hw,
656
-					       u32 tx_pkt_shed_desc_tc_weight,
657
-					u32 tc);
715
+					       const u32 tc,
716
+					       const u32 weight);
658
717
 
659
718
 /* set tx packet scheduler descriptor vm arbitration mode */
660
719
 void hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(struct aq_hw_s *aq_hw,
..
..
@@ -662,13 +721,29 @@
662
721
 
663
722
 /* set tx packet scheduler tc data max credit */
664
723
 void hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw,
665
-						   u32 max_credit,
666
-					    u32 tc);
724
+						   const u32 tc,
725
+						   const u32 max_credit);
667
726
 
668
727
 /* set tx packet scheduler tc data weight */
669
728
 void hw_atl_tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw,
670
-					       u32 tx_pkt_shed_tc_data_weight,
671
-					u32 tc);
729
+					       const u32 tc,
730
+					       const u32 weight);
731
+
732
+/* set tx descriptor rate mode */
733
+void hw_atl_tps_tx_desc_rate_mode_set(struct aq_hw_s *aq_hw,
734
+				      const u32 rate_mode);
735
+
736
+/* set tx packet scheduler descriptor rate enable */
737
+void hw_atl_tps_tx_desc_rate_en_set(struct aq_hw_s *aq_hw, const u32 desc,
738
+				    const u32 enable);
739
+
740
+/* set tx packet scheduler descriptor rate integral value */
741
+void hw_atl_tps_tx_desc_rate_x_set(struct aq_hw_s *aq_hw, const u32 desc,
742
+				   const u32 rate_int);
743
+
744
+/* set tx packet scheduler descriptor rate fractional value */
745
+void hw_atl_tps_tx_desc_rate_y_set(struct aq_hw_s *aq_hw, const u32 desc,
746
+				   const u32 rate_frac);
672
747
 
673
748
 /* tx */
674
749
 
..
..
@@ -701,7 +776,97 @@
701
776
 /* set pci register reset disable */
702
777
 void hw_atl_pci_pci_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 pci_reg_res_dis);
703
778
 
779
+/* pcs */
780
+void hw_atl_pcs_ptp_clock_read_enable(struct aq_hw_s *aq_hw,
781
+				      u32 ptp_clock_read_enable);
782
+
783
+u32 hw_atl_pcs_ptp_clock_get(struct aq_hw_s *aq_hw, u32 index);
784
+
704
785
 /* set uP Force Interrupt */
705
786
 void hw_atl_mcp_up_force_intr_set(struct aq_hw_s *aq_hw, u32 up_force_intr);
706
787
 
788
+/* clear ipv4 filter destination address */
789
+void hw_atl_rpfl3l4_ipv4_dest_addr_clear(struct aq_hw_s *aq_hw, u8 location);
790
+
791
+/* clear ipv4 filter source address */
792
+void hw_atl_rpfl3l4_ipv4_src_addr_clear(struct aq_hw_s *aq_hw, u8 location);
793
+
794
+/* clear command for filter l3-l4 */
795
+void hw_atl_rpfl3l4_cmd_clear(struct aq_hw_s *aq_hw, u8 location);
796
+
797
+/* clear ipv6 filter destination address */
798
+void hw_atl_rpfl3l4_ipv6_dest_addr_clear(struct aq_hw_s *aq_hw, u8 location);
799
+
800
+/* clear ipv6 filter source address */
801
+void hw_atl_rpfl3l4_ipv6_src_addr_clear(struct aq_hw_s *aq_hw, u8 location);
802
+
803
+/* set ipv4 filter destination address */
804
+void hw_atl_rpfl3l4_ipv4_dest_addr_set(struct aq_hw_s *aq_hw, u8 location,
805
+				       u32 ipv4_dest);
806
+
807
+/* set ipv4 filter source address */
808
+void hw_atl_rpfl3l4_ipv4_src_addr_set(struct aq_hw_s *aq_hw, u8 location,
809
+				      u32 ipv4_src);
810
+
811
+/* set command for filter l3-l4 */
812
+void hw_atl_rpfl3l4_cmd_set(struct aq_hw_s *aq_hw, u8 location, u32 cmd);
813
+
814
+/* set ipv6 filter source address */
815
+void hw_atl_rpfl3l4_ipv6_src_addr_set(struct aq_hw_s *aq_hw, u8 location,
816
+				      u32 *ipv6_src);
817
+
818
+/* set ipv6 filter destination address */
819
+void hw_atl_rpfl3l4_ipv6_dest_addr_set(struct aq_hw_s *aq_hw, u8 location,
820
+				       u32 *ipv6_dest);
821
+
822
+/* set Global MDIO Interface 1 */
823
+void hw_atl_glb_mdio_iface1_set(struct aq_hw_s *hw, u32 value);
824
+
825
+/* get Global MDIO Interface 1 */
826
+u32 hw_atl_glb_mdio_iface1_get(struct aq_hw_s *hw);
827
+
828
+/* set Global MDIO Interface 2 */
829
+void hw_atl_glb_mdio_iface2_set(struct aq_hw_s *hw, u32 value);
830
+
831
+/* get Global MDIO Interface 2 */
832
+u32 hw_atl_glb_mdio_iface2_get(struct aq_hw_s *hw);
833
+
834
+/* set Global MDIO Interface 3 */
835
+void hw_atl_glb_mdio_iface3_set(struct aq_hw_s *hw, u32 value);
836
+
837
+/* get Global MDIO Interface 3 */
838
+u32 hw_atl_glb_mdio_iface3_get(struct aq_hw_s *hw);
839
+
840
+/* set Global MDIO Interface 4 */
841
+void hw_atl_glb_mdio_iface4_set(struct aq_hw_s *hw, u32 value);
842
+
843
+/* get Global MDIO Interface 4 */
844
+u32 hw_atl_glb_mdio_iface4_get(struct aq_hw_s *hw);
845
+
846
+/* set Global MDIO Interface 5 */
847
+void hw_atl_glb_mdio_iface5_set(struct aq_hw_s *hw, u32 value);
848
+
849
+/* get Global MDIO Interface 5 */
850
+u32 hw_atl_glb_mdio_iface5_get(struct aq_hw_s *hw);
851
+
852
+u32 hw_atl_mdio_busy_get(struct aq_hw_s *aq_hw);
853
+
854
+/* get global microprocessor ram semaphore */
855
+u32 hw_atl_sem_ram_get(struct aq_hw_s *self);
856
+
857
+/* get global microprocessor mdio semaphore */
858
+u32 hw_atl_sem_mdio_get(struct aq_hw_s *self);
859
+
860
+u32 hw_atl_sem_reset1_get(struct aq_hw_s *self);
861
+u32 hw_atl_sem_reset2_get(struct aq_hw_s *self);
862
+
863
+/* get global microprocessor scratch pad register */
864
+u32 hw_atl_scrpad_get(struct aq_hw_s *aq_hw, u32 scratch_scp);
865
+
866
+/* get global microprocessor scratch pad 12 register */
867
+u32 hw_atl_scrpad12_get(struct aq_hw_s *self);
868
+
869
+/* get global microprocessor scratch pad 25 register */
870
+u32 hw_atl_scrpad25_get(struct aq_hw_s *self);
871
+
707
872
 #endif /* HW_ATL_LLH_H */