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2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390 
 kernel/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c
....@@ -1,10 +1,8 @@
1
-/*
2
- * aQuantia Corporation Network Driver
3
- * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
1
+// SPDX-License-Identifier: GPL-2.0-only
2
+/* Atlantic Network Driver
43  *
5
- * This program is free software; you can redistribute it and/or modify it
6
- * under the terms and conditions of the GNU General Public License,
7
- * version 2, as published by the Free Software Foundation.
4
+ * Copyright (C) 2014-2019 aQuantia Corporation
5
+ * Copyright (C) 2019-2020 Marvell International Ltd.
86  */
97 
108 /* File hw_atl_llh.c: Definitions of bitfield and register access functions for
....@@ -14,6 +12,50 @@
1412 #include "hw_atl_llh.h"
1513 #include "hw_atl_llh_internal.h"
1614 #include "../aq_hw_utils.h"
15
+
16
+void hw_atl_ts_reset_set(struct aq_hw_s *aq_hw, u32 val)
17
+{
18
+	aq_hw_write_reg_bit(aq_hw, HW_ATL_TS_RESET_ADR,
19
+			    HW_ATL_TS_RESET_MSK,
20
+			    HW_ATL_TS_RESET_SHIFT,
21
+			    val);
22
+}
23
+
24
+void hw_atl_ts_power_down_set(struct aq_hw_s *aq_hw, u32 val)
25
+{
26
+	aq_hw_write_reg_bit(aq_hw, HW_ATL_TS_POWER_DOWN_ADR,
27
+			    HW_ATL_TS_POWER_DOWN_MSK,
28
+			    HW_ATL_TS_POWER_DOWN_SHIFT,
29
+			    val);
30
+}
31
+
32
+u32 hw_atl_ts_power_down_get(struct aq_hw_s *aq_hw)
33
+{
34
+	return aq_hw_read_reg_bit(aq_hw, HW_ATL_TS_POWER_DOWN_ADR,
35
+				  HW_ATL_TS_POWER_DOWN_MSK,
36
+				  HW_ATL_TS_POWER_DOWN_SHIFT);
37
+}
38
+
39
+u32 hw_atl_ts_ready_get(struct aq_hw_s *aq_hw)
40
+{
41
+	return aq_hw_read_reg_bit(aq_hw, HW_ATL_TS_READY_ADR,
42
+				  HW_ATL_TS_READY_MSK,
43
+				  HW_ATL_TS_READY_SHIFT);
44
+}
45
+
46
+u32 hw_atl_ts_ready_latch_high_get(struct aq_hw_s *aq_hw)
47
+{
48
+	return aq_hw_read_reg_bit(aq_hw, HW_ATL_TS_READY_LATCH_HIGH_ADR,
49
+				  HW_ATL_TS_READY_LATCH_HIGH_MSK,
50
+				  HW_ATL_TS_READY_LATCH_HIGH_SHIFT);
51
+}
52
+
53
+u32 hw_atl_ts_data_get(struct aq_hw_s *aq_hw)
54
+{
55
+	return aq_hw_read_reg_bit(aq_hw, HW_ATL_TS_DATA_OUT_ADR,
56
+				  HW_ATL_TS_DATA_OUT_MSK,
57
+				  HW_ATL_TS_DATA_OUT_SHIFT);
58
+}
1759 
1860 /* global */
1961 void hw_atl_reg_glb_cpu_sem_set(struct aq_hw_s *aq_hw, u32 glb_cpu_sem,
....@@ -49,11 +91,6 @@
4991 				  HW_ATL_GLB_SOFT_RES_SHIFT);
5092 }
5193 
52
-u32 hw_atl_reg_rx_dma_stat_counter7get(struct aq_hw_s *aq_hw)
53
-{
54
-	return aq_hw_read_reg(aq_hw, HW_ATL_RX_DMA_STAT_COUNTER7_ADR);
55
-}
56
-
5794 u32 hw_atl_reg_glb_mif_id_get(struct aq_hw_s *aq_hw)
5895 {
5996 	return aq_hw_read_reg(aq_hw, HW_ATL_GLB_MIF_ID_ADR);
....@@ -65,44 +102,24 @@
65102 	return aq_hw_read_reg(aq_hw, HW_ATL_RPB_RX_DMA_DROP_PKT_CNT_ADR);
66103 }
67104 
68
-u32 hw_atl_stats_rx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw)
105
+u64 hw_atl_stats_rx_dma_good_octet_counter_get(struct aq_hw_s *aq_hw)
69106 {
70
-	return aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERLSW);
107
+	return aq_hw_read_reg64(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERLSW);
71108 }
72109 
73
-u32 hw_atl_stats_rx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw)
110
+u64 hw_atl_stats_rx_dma_good_pkt_counter_get(struct aq_hw_s *aq_hw)
74111 {
75
-	return aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERLSW);
112
+	return aq_hw_read_reg64(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERLSW);
76113 }
77114 
78
-u32 hw_atl_stats_tx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw)
115
+u64 hw_atl_stats_tx_dma_good_octet_counter_get(struct aq_hw_s *aq_hw)
79116 {
80
-	return aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERLSW);
117
+	return aq_hw_read_reg64(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERLSW);
81118 }
82119 
83
-u32 hw_atl_stats_tx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw)
120
+u64 hw_atl_stats_tx_dma_good_pkt_counter_get(struct aq_hw_s *aq_hw)
84121 {
85
-	return aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERLSW);
86
-}
87
-
88
-u32 hw_atl_stats_rx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw)
89
-{
90
-	return aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERMSW);
91
-}
92
-
93
-u32 hw_atl_stats_rx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw)
94
-{
95
-	return aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERMSW);
96
-}
97
-
98
-u32 hw_atl_stats_tx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw)
99
-{
100
-	return aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERMSW);
101
-}
102
-
103
-u32 hw_atl_stats_tx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw)
104
-{
105
-	return aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERMSW);
122
+	return aq_hw_read_reg64(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERLSW);
106123 }
107124 
108125 /* interrupt */
....@@ -313,6 +330,21 @@
313330 {
314331 	aq_hw_write_reg_bit(aq_hw, HW_ATL_ITR_RES_ADR, HW_ATL_ITR_RES_MSK,
315332 			    HW_ATL_ITR_RES_SHIFT, res_irq);
333
+}
334
+
335
+/* set RSC interrupt */
336
+void hw_atl_itr_rsc_en_set(struct aq_hw_s *aq_hw, u32 enable)
337
+{
338
+	aq_hw_write_reg(aq_hw, HW_ATL_ITR_RSC_EN_ADR, enable);
339
+}
340
+
341
+/* set RSC delay */
342
+void hw_atl_itr_rsc_delay_set(struct aq_hw_s *aq_hw, u32 delay)
343
+{
344
+	aq_hw_write_reg_bit(aq_hw, HW_ATL_ITR_RSC_DELAY_ADR,
345
+			    HW_ATL_ITR_RSC_DELAY_MSK,
346
+			    HW_ATL_ITR_RSC_DELAY_SHIFT,
347
+			    delay);
316348 }
317349 
318350 /* rdm */
....@@ -576,6 +608,13 @@
576608 			    HW_ATL_RPB_DMA_SYS_LBK_SHIFT, dma_sys_lbk);
577609 }
578610 
611
+void hw_atl_rpb_dma_net_lbk_set(struct aq_hw_s *aq_hw, u32 dma_net_lbk)
612
+{
613
+	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_DMA_NET_LBK_ADR,
614
+			    HW_ATL_RPB_DMA_NET_LBK_MSK,
615
+			    HW_ATL_RPB_DMA_NET_LBK_SHIFT, dma_net_lbk);
616
+}
617
+
579618 void hw_atl_rpb_rpf_rx_traf_class_mode_set(struct aq_hw_s *aq_hw,
580619 					   u32 rx_traf_class_mode)
581620 {
....@@ -583,6 +622,13 @@
583622 			    HW_ATL_RPB_RPF_RX_TC_MODE_MSK,
584623 			    HW_ATL_RPB_RPF_RX_TC_MODE_SHIFT,
585624 			    rx_traf_class_mode);
625
+}
626
+
627
+u32 hw_atl_rpb_rpf_rx_traf_class_mode_get(struct aq_hw_s *aq_hw)
628
+{
629
+	return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPB_RPF_RX_TC_MODE_ADR,
630
+			HW_ATL_RPB_RPF_RX_TC_MODE_MSK,
631
+			HW_ATL_RPB_RPF_RX_TC_MODE_SHIFT);
586632 }
587633 
588634 void hw_atl_rpb_rx_buff_en_set(struct aq_hw_s *aq_hw, u32 rx_buff_en)
....@@ -619,12 +665,25 @@
619665 			    HW_ATL_RPB_RX_FC_MODE_SHIFT, rx_flow_ctl_mode);
620666 }
621667 
622
-void hw_atl_rdm_rx_dma_desc_cache_init_set(struct aq_hw_s *aq_hw, u32 init)
668
+void hw_atl_rdm_rx_dma_desc_cache_init_tgl(struct aq_hw_s *aq_hw)
623669 {
670
+	u32 val;
671
+
672
+	val = aq_hw_read_reg_bit(aq_hw, HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_ADR,
673
+				 HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_MSK,
674
+				 HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_SHIFT);
675
+
624676 	aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_ADR,
625677 			    HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_MSK,
626678 			    HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_SHIFT,
627
-			    init);
679
+			    val ^ 1);
680
+}
681
+
682
+u32 hw_atl_rdm_rx_dma_desc_cache_init_done_get(struct aq_hw_s *aq_hw)
683
+{
684
+	return aq_hw_read_reg_bit(aq_hw, RDM_RX_DMA_DESC_CACHE_INIT_DONE_ADR,
685
+				  RDM_RX_DMA_DESC_CACHE_INIT_DONE_MSK,
686
+				  RDM_RX_DMA_DESC_CACHE_INIT_DONE_SHIFT);
628687 }
629688 
630689 void hw_atl_rpb_rx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
....@@ -636,8 +695,8 @@
636695 			    rx_pkt_buff_size_per_tc);
637696 }
638697 
639
-void hw_atl_rpb_rx_xoff_en_per_tc_set(struct aq_hw_s *aq_hw, u32 rx_xoff_en_per_tc,
640
-				      u32 buffer)
698
+void hw_atl_rpb_rx_xoff_en_per_tc_set(struct aq_hw_s *aq_hw,
699
+				      u32 rx_xoff_en_per_tc, u32 buffer)
641700 {
642701 	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBXOFF_EN_ADR(buffer),
643702 			    HW_ATL_RPB_RXBXOFF_EN_MSK,
....@@ -677,6 +736,13 @@
677736 	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2MC_ENF_ADR(filter),
678737 			    HW_ATL_RPFL2MC_ENF_MSK,
679738 			    HW_ATL_RPFL2MC_ENF_SHIFT, l2multicast_flr_en);
739
+}
740
+
741
+u32 hw_atl_rpfl2promiscuous_mode_en_get(struct aq_hw_s *aq_hw)
742
+{
743
+	return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPFL2PROMIS_MODE_ADR,
744
+				  HW_ATL_RPFL2PROMIS_MODE_MSK,
745
+				  HW_ATL_RPFL2PROMIS_MODE_SHIFT);
680746 }
681747 
682748 void hw_atl_rpfl2promiscuous_mode_en_set(struct aq_hw_s *aq_hw,
....@@ -733,7 +799,7 @@
733799 }
734800 
735801 void hw_atl_rpf_rpb_user_priority_tc_map_set(struct aq_hw_s *aq_hw,
736
-					     u32 user_priority_tc_map, u32 tc)
802
+					     u32 user_priority, u32 tc)
737803 {
738804 /* register address for bitfield rx_tc_up{t}[2:0] */
739805 	static u32 rpf_rpb_rx_tc_upt_adr[8] = {
....@@ -752,10 +818,9 @@
752818 			0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U
753819 		};
754820 
755
-	aq_hw_write_reg_bit(aq_hw, rpf_rpb_rx_tc_upt_adr[tc],
756
-			    rpf_rpb_rx_tc_upt_msk[tc],
757
-			    rpf_rpb_rx_tc_upt_shft[tc],
758
-			    user_priority_tc_map);
821
+	aq_hw_write_reg_bit(aq_hw, rpf_rpb_rx_tc_upt_adr[user_priority],
822
+			    rpf_rpb_rx_tc_upt_msk[user_priority],
823
+			    rpf_rpb_rx_tc_upt_shft[user_priority], tc);
759824 }
760825 
761826 void hw_atl_rpf_rss_key_addr_set(struct aq_hw_s *aq_hw, u32 rss_key_addr)
....@@ -853,6 +918,13 @@
853918 			    vlan_prom_mode_en);
854919 }
855920 
921
+u32 hw_atl_rpf_vlan_prom_mode_en_get(struct aq_hw_s *aq_hw)
922
+{
923
+	return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPF_VL_PROMIS_MODE_ADR,
924
+				  HW_ATL_RPF_VL_PROMIS_MODE_MSK,
925
+				  HW_ATL_RPF_VL_PROMIS_MODE_SHIFT);
926
+}
927
+
856928 void hw_atl_rpf_vlan_accept_untagged_packets_set(struct aq_hw_s *aq_hw,
857929 						 u32 vlan_acc_untagged_packets)
858930 {
....@@ -897,6 +969,24 @@
897969 			    HW_ATL_RPF_VL_ID_F_SHIFT,
898970 			    vlan_id_flr);
899971 }
972
+
973
+void hw_atl_rpf_vlan_rxq_en_flr_set(struct aq_hw_s *aq_hw, u32 vlan_rxq_en,
974
+				    u32 filter)
975
+{
976
+	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_RXQ_EN_F_ADR(filter),
977
+			    HW_ATL_RPF_VL_RXQ_EN_F_MSK,
978
+			    HW_ATL_RPF_VL_RXQ_EN_F_SHIFT,
979
+			    vlan_rxq_en);
980
+}
981
+
982
+void hw_atl_rpf_vlan_rxq_flr_set(struct aq_hw_s *aq_hw, u32 vlan_rxq,
983
+				 u32 filter)
984
+{
985
+	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_RXQ_F_ADR(filter),
986
+			    HW_ATL_RPF_VL_RXQ_F_MSK,
987
+			    HW_ATL_RPF_VL_RXQ_F_SHIFT,
988
+			    vlan_rxq);
989
+};
900990 
901991 void hw_atl_rpf_etht_flr_en_set(struct aq_hw_s *aq_hw, u32 etht_flr_en,
902992 				u32 filter)
....@@ -965,6 +1055,20 @@
9651055 			    HW_ATL_RPF_ET_VALF_SHIFT, etht_flr);
9661056 }
9671057 
1058
+void hw_atl_rpf_l4_spd_set(struct aq_hw_s *aq_hw, u32 val, u32 filter)
1059
+{
1060
+	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_L4_SPD_ADR(filter),
1061
+			    HW_ATL_RPF_L4_SPD_MSK,
1062
+			    HW_ATL_RPF_L4_SPD_SHIFT, val);
1063
+}
1064
+
1065
+void hw_atl_rpf_l4_dpd_set(struct aq_hw_s *aq_hw, u32 val, u32 filter)
1066
+{
1067
+	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_L4_DPD_ADR(filter),
1068
+			    HW_ATL_RPF_L4_DPD_MSK,
1069
+			    HW_ATL_RPF_L4_DPD_SHIFT, val);
1070
+}
1071
+
9681072 /* RPO: rx packet offload */
9691073 void hw_atl_rpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,
9701074 					      u32 ipv4header_crc_offload_en)
....@@ -983,6 +1087,22 @@
9831087 			    HW_ATL_RPO_DESCDVL_STRIP_MSK,
9841088 			    HW_ATL_RPO_DESCDVL_STRIP_SHIFT,
9851089 			    rx_desc_vlan_stripping);
1090
+}
1091
+
1092
+void hw_atl_rpo_outer_vlan_tag_mode_set(void *context,
1093
+					u32 outervlantagmode)
1094
+{
1095
+	aq_hw_write_reg_bit(context, HW_ATL_RPO_OUTER_VL_INS_MODE_ADR,
1096
+			    HW_ATL_RPO_OUTER_VL_INS_MODE_MSK,
1097
+			    HW_ATL_RPO_OUTER_VL_INS_MODE_SHIFT,
1098
+			    outervlantagmode);
1099
+}
1100
+
1101
+u32 hw_atl_rpo_outer_vlan_tag_mode_get(void *context)
1102
+{
1103
+	return aq_hw_read_reg_bit(context, HW_ATL_RPO_OUTER_VL_INS_MODE_ADR,
1104
+				  HW_ATL_RPO_OUTER_VL_INS_MODE_MSK,
1105
+				  HW_ATL_RPO_OUTER_VL_INS_MODE_SHIFT);
9861106 }
9871107 
9881108 void hw_atl_rpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
....@@ -1242,6 +1362,22 @@
12421362 			    HW_ATL_TPB_TX_BUF_EN_SHIFT, tx_buff_en);
12431363 }
12441364 
1365
+u32 hw_atl_tpb_tps_tx_tc_mode_get(struct aq_hw_s *aq_hw)
1366
+{
1367
+	return aq_hw_read_reg_bit(aq_hw, HW_ATL_TPB_TX_TC_MODE_ADDR,
1368
+			HW_ATL_TPB_TX_TC_MODE_MSK,
1369
+			HW_ATL_TPB_TX_TC_MODE_SHIFT);
1370
+}
1371
+
1372
+void hw_atl_tpb_tps_tx_tc_mode_set(struct aq_hw_s *aq_hw,
1373
+				   u32 tx_traf_class_mode)
1374
+{
1375
+	aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_TC_MODE_ADDR,
1376
+			HW_ATL_TPB_TX_TC_MODE_MSK,
1377
+			HW_ATL_TPB_TX_TC_MODE_SHIFT,
1378
+			tx_traf_class_mode);
1379
+}
1380
+
12451381 void hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,
12461382 						u32 tx_buff_hi_threshold_per_tc,
12471383 					 u32 buffer)
....@@ -1270,7 +1406,26 @@
12701406 			    tx_dma_sys_lbk_en);
12711407 }
12721408 
1409
+void hw_atl_tpb_tx_dma_net_lbk_en_set(struct aq_hw_s *aq_hw,
1410
+				      u32 tx_dma_net_lbk_en)
1411
+{
1412
+	aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_DMA_NET_LBK_ADR,
1413
+			    HW_ATL_TPB_DMA_NET_LBK_MSK,
1414
+			    HW_ATL_TPB_DMA_NET_LBK_SHIFT,
1415
+			    tx_dma_net_lbk_en);
1416
+}
1417
+
1418
+void hw_atl_tpb_tx_tx_clk_gate_en_set(struct aq_hw_s *aq_hw,
1419
+				      u32 tx_clk_gate_en)
1420
+{
1421
+	aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_CLK_GATE_EN_ADR,
1422
+			    HW_ATL_TPB_TX_CLK_GATE_EN_MSK,
1423
+			    HW_ATL_TPB_TX_CLK_GATE_EN_SHIFT,
1424
+			    tx_clk_gate_en);
1425
+}
1426
+
12731427 void hw_atl_tpb_tx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
1428
+
12741429 					    u32 tx_pkt_buff_size_per_tc, u32 buffer)
12751430 {
12761431 	aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBBUF_SIZE_ADR(buffer),
....@@ -1353,8 +1508,8 @@
13531508 }
13541509 
13551510 void hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(struct aq_hw_s *aq_hw,
1356
-						   u32 max_credit,
1357
-						   u32 tc)
1511
+						   const u32 tc,
1512
+						   const u32 max_credit)
13581513 {
13591514 	aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TCTCREDIT_MAX_ADR(tc),
13601515 			    HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSK,
....@@ -1363,13 +1518,13 @@
13631518 }
13641519 
13651520 void hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(struct aq_hw_s *aq_hw,
1366
-					       u32 tx_pkt_shed_desc_tc_weight,
1367
-					       u32 tc)
1521
+					       const u32 tc,
1522
+					       const u32 weight)
13681523 {
13691524 	aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TCTWEIGHT_ADR(tc),
13701525 			    HW_ATL_TPS_DESC_TCTWEIGHT_MSK,
13711526 			    HW_ATL_TPS_DESC_TCTWEIGHT_SHIFT,
1372
-			    tx_pkt_shed_desc_tc_weight);
1527
+			    weight);
13731528 }
13741529 
13751530 void hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(struct aq_hw_s *aq_hw,
....@@ -1382,8 +1537,8 @@
13821537 }
13831538 
13841539 void hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw,
1385
-						   u32 max_credit,
1386
-						   u32 tc)
1540
+						   const u32 tc,
1541
+						   const u32 max_credit)
13871542 {
13881543 	aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TCTCREDIT_MAX_ADR(tc),
13891544 			    HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSK,
....@@ -1392,13 +1547,49 @@
13921547 }
13931548 
13941549 void hw_atl_tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw,
1395
-					       u32 tx_pkt_shed_tc_data_weight,
1396
-					       u32 tc)
1550
+					       const u32 tc,
1551
+					       const u32 weight)
13971552 {
13981553 	aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TCTWEIGHT_ADR(tc),
13991554 			    HW_ATL_TPS_DATA_TCTWEIGHT_MSK,
14001555 			    HW_ATL_TPS_DATA_TCTWEIGHT_SHIFT,
1401
-			    tx_pkt_shed_tc_data_weight);
1556
+			    weight);
1557
+}
1558
+
1559
+void hw_atl_tps_tx_desc_rate_mode_set(struct aq_hw_s *aq_hw,
1560
+				      const u32 rate_mode)
1561
+{
1562
+	aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_TX_DESC_RATE_MODE_ADR,
1563
+			    HW_ATL_TPS_TX_DESC_RATE_MODE_MSK,
1564
+			    HW_ATL_TPS_TX_DESC_RATE_MODE_SHIFT,
1565
+			    rate_mode);
1566
+}
1567
+
1568
+void hw_atl_tps_tx_desc_rate_en_set(struct aq_hw_s *aq_hw, const u32 desc,
1569
+				    const u32 enable)
1570
+{
1571
+	aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_EN_ADR(desc),
1572
+			    HW_ATL_TPS_DESC_RATE_EN_MSK,
1573
+			    HW_ATL_TPS_DESC_RATE_EN_SHIFT,
1574
+			    enable);
1575
+}
1576
+
1577
+void hw_atl_tps_tx_desc_rate_x_set(struct aq_hw_s *aq_hw, const u32 desc,
1578
+				   const u32 rate_int)
1579
+{
1580
+	aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_X_ADR(desc),
1581
+			    HW_ATL_TPS_DESC_RATE_X_MSK,
1582
+			    HW_ATL_TPS_DESC_RATE_X_SHIFT,
1583
+			    rate_int);
1584
+}
1585
+
1586
+void hw_atl_tps_tx_desc_rate_y_set(struct aq_hw_s *aq_hw, const u32 desc,
1587
+				   const u32 rate_frac)
1588
+{
1589
+	aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_Y_ADR(desc),
1590
+			    HW_ATL_TPS_DESC_RATE_Y_MSK,
1591
+			    HW_ATL_TPS_DESC_RATE_Y_SHIFT,
1592
+			    rate_frac);
14021593 }
14031594 
14041595 /* tx */
....@@ -1469,6 +1660,20 @@
14691660 			glb_cpu_scratch_scp);
14701661 }
14711662 
1663
+void hw_atl_pcs_ptp_clock_read_enable(struct aq_hw_s *aq_hw,
1664
+				      u32 ptp_clock_read_enable)
1665
+{
1666
+	aq_hw_write_reg_bit(aq_hw, HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_ADR,
1667
+			    HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_MSK,
1668
+			    HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_SHIFT,
1669
+			    ptp_clock_read_enable);
1670
+}
1671
+
1672
+u32 hw_atl_pcs_ptp_clock_get(struct aq_hw_s *aq_hw, u32 index)
1673
+{
1674
+	return aq_hw_read_reg(aq_hw, HW_ATL_PCS_PTP_TS_VAL_ADDR(index));
1675
+}
1676
+
14721677 void hw_atl_mcp_up_force_intr_set(struct aq_hw_s *aq_hw, u32 up_force_intr)
14731678 {
14741679 	aq_hw_write_reg_bit(aq_hw, HW_ATL_MCP_UP_FORCE_INTERRUPT_ADR,
....@@ -1476,3 +1681,173 @@
14761681 			    HW_ATL_MCP_UP_FORCE_INTERRUPT_SHIFT,
14771682 			    up_force_intr);
14781683 }
1684
+
1685
+void hw_atl_rpfl3l4_ipv4_dest_addr_clear(struct aq_hw_s *aq_hw, u8 location)
1686
+{
1687
+	aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_DSTA_ADR(location), 0U);
1688
+}
1689
+
1690
+void hw_atl_rpfl3l4_ipv4_src_addr_clear(struct aq_hw_s *aq_hw, u8 location)
1691
+{
1692
+	aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_SRCA_ADR(location), 0U);
1693
+}
1694
+
1695
+void hw_atl_rpfl3l4_cmd_clear(struct aq_hw_s *aq_hw, u8 location)
1696
+{
1697
+	aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_REG_CTRL_ADR(location), 0U);
1698
+}
1699
+
1700
+void hw_atl_rpfl3l4_ipv6_dest_addr_clear(struct aq_hw_s *aq_hw, u8 location)
1701
+{
1702
+	int i;
1703
+
1704
+	for (i = 0; i < 4; ++i)
1705
+		aq_hw_write_reg(aq_hw,
1706
+				HW_ATL_RPF_L3_DSTA_ADR(location + i),
1707
+				0U);
1708
+}
1709
+
1710
+void hw_atl_rpfl3l4_ipv6_src_addr_clear(struct aq_hw_s *aq_hw, u8 location)
1711
+{
1712
+	int i;
1713
+
1714
+	for (i = 0; i < 4; ++i)
1715
+		aq_hw_write_reg(aq_hw,
1716
+				HW_ATL_RPF_L3_SRCA_ADR(location + i),
1717
+				0U);
1718
+}
1719
+
1720
+void hw_atl_rpfl3l4_ipv4_dest_addr_set(struct aq_hw_s *aq_hw, u8 location,
1721
+				       u32 ipv4_dest)
1722
+{
1723
+	aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_DSTA_ADR(location),
1724
+			ipv4_dest);
1725
+}
1726
+
1727
+void hw_atl_rpfl3l4_ipv4_src_addr_set(struct aq_hw_s *aq_hw, u8 location,
1728
+				      u32 ipv4_src)
1729
+{
1730
+	aq_hw_write_reg(aq_hw,
1731
+			HW_ATL_RPF_L3_SRCA_ADR(location),
1732
+			ipv4_src);
1733
+}
1734
+
1735
+void hw_atl_rpfl3l4_cmd_set(struct aq_hw_s *aq_hw, u8 location, u32 cmd)
1736
+{
1737
+	aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_REG_CTRL_ADR(location), cmd);
1738
+}
1739
+
1740
+void hw_atl_rpfl3l4_ipv6_src_addr_set(struct aq_hw_s *aq_hw, u8 location,
1741
+				      u32 *ipv6_src)
1742
+{
1743
+	int i;
1744
+
1745
+	for (i = 0; i < 4; ++i)
1746
+		aq_hw_write_reg(aq_hw,
1747
+				HW_ATL_RPF_L3_SRCA_ADR(location + i),
1748
+				ipv6_src[3 - i]);
1749
+}
1750
+
1751
+void hw_atl_rpfl3l4_ipv6_dest_addr_set(struct aq_hw_s *aq_hw, u8 location,
1752
+				       u32 *ipv6_dest)
1753
+{
1754
+	int i;
1755
+
1756
+	for (i = 0; i < 4; ++i)
1757
+		aq_hw_write_reg(aq_hw,
1758
+				HW_ATL_RPF_L3_DSTA_ADR(location + i),
1759
+				ipv6_dest[3 - i]);
1760
+}
1761
+
1762
+u32 hw_atl_sem_ram_get(struct aq_hw_s *self)
1763
+{
1764
+	return hw_atl_reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_RAM);
1765
+}
1766
+
1767
+u32 hw_atl_sem_mdio_get(struct aq_hw_s *self)
1768
+{
1769
+	return hw_atl_reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_MDIO);
1770
+}
1771
+
1772
+u32 hw_atl_sem_reset1_get(struct aq_hw_s *self)
1773
+{
1774
+	return hw_atl_reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_RESET1);
1775
+}
1776
+
1777
+u32 hw_atl_sem_reset2_get(struct aq_hw_s *self)
1778
+{
1779
+	return hw_atl_reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_RESET2);
1780
+}
1781
+
1782
+u32 hw_atl_scrpad_get(struct aq_hw_s *aq_hw, u32 scratch_scp)
1783
+{
1784
+	return aq_hw_read_reg(aq_hw,
1785
+			      HW_ATL_GLB_CPU_SCRATCH_SCP_ADR(scratch_scp));
1786
+}
1787
+
1788
+u32 hw_atl_scrpad12_get(struct aq_hw_s *self)
1789
+{
1790
+	return  hw_atl_scrpad_get(self, 0xB);
1791
+}
1792
+
1793
+u32 hw_atl_scrpad25_get(struct aq_hw_s *self)
1794
+{
1795
+	return hw_atl_scrpad_get(self, 0x18);
1796
+}
1797
+
1798
+void hw_atl_glb_mdio_iface1_set(struct aq_hw_s *aq_hw, u32 value)
1799
+{
1800
+	aq_hw_write_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(1), value);
1801
+}
1802
+
1803
+u32 hw_atl_glb_mdio_iface1_get(struct aq_hw_s *aq_hw)
1804
+{
1805
+	return aq_hw_read_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(1));
1806
+}
1807
+
1808
+void hw_atl_glb_mdio_iface2_set(struct aq_hw_s *aq_hw, u32 value)
1809
+{
1810
+	aq_hw_write_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(2), value);
1811
+}
1812
+
1813
+u32 hw_atl_glb_mdio_iface2_get(struct aq_hw_s *aq_hw)
1814
+{
1815
+	return aq_hw_read_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(2));
1816
+}
1817
+
1818
+void hw_atl_glb_mdio_iface3_set(struct aq_hw_s *aq_hw, u32 value)
1819
+{
1820
+	aq_hw_write_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(3), value);
1821
+}
1822
+
1823
+u32 hw_atl_glb_mdio_iface3_get(struct aq_hw_s *aq_hw)
1824
+{
1825
+	return aq_hw_read_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(3));
1826
+}
1827
+
1828
+void hw_atl_glb_mdio_iface4_set(struct aq_hw_s *aq_hw, u32 value)
1829
+{
1830
+	aq_hw_write_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(4), value);
1831
+}
1832
+
1833
+u32 hw_atl_glb_mdio_iface4_get(struct aq_hw_s *aq_hw)
1834
+{
1835
+	return aq_hw_read_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(4));
1836
+}
1837
+
1838
+void hw_atl_glb_mdio_iface5_set(struct aq_hw_s *aq_hw, u32 value)
1839
+{
1840
+	aq_hw_write_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(5), value);
1841
+}
1842
+
1843
+u32 hw_atl_glb_mdio_iface5_get(struct aq_hw_s *aq_hw)
1844
+{
1845
+	return aq_hw_read_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(5));
1846
+}
1847
+
1848
+u32 hw_atl_mdio_busy_get(struct aq_hw_s *aq_hw)
1849
+{
1850
+	return aq_hw_read_reg_bit(aq_hw, HW_ATL_MDIO_BUSY_ADR,
1851
+				  HW_ATL_MDIO_BUSY_MSK,
1852
+				  HW_ATL_MDIO_BUSY_SHIFT);
1853
+}