change wifi driver to cypress

hc

2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390

 kernel/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0_internal.h
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@@ -1,10 +1,7 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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  * aQuantia Corporation Network Driver
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- * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms and conditions of the GNU General Public License,
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- * version 2, as published by the Free Software Foundation.
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+ * Copyright (C) 2014-2019 aQuantia Corporation. All rights reserved
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  */
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 /* File hw_atl_b0_internal.h: Definition of Atlantic B0 chip specific
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@@ -67,24 +64,21 @@
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 #define HW_ATL_B0_MPI_SPEED_MSK         0xFFFFU
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 #define HW_ATL_B0_MPI_SPEED_SHIFT       16U
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-#define HW_ATL_B0_RATE_10G              BIT(0)
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-#define HW_ATL_B0_RATE_5G               BIT(1)
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-#define HW_ATL_B0_RATE_2G5              BIT(3)
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-#define HW_ATL_B0_RATE_1G               BIT(4)
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-#define HW_ATL_B0_RATE_100M             BIT(5)
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+#define HW_ATL_B0_TXBUF_MAX              160U
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+#define HW_ATL_B0_PTP_TXBUF_SIZE           8U
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-#define HW_ATL_B0_TXBUF_MAX  160U
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-#define HW_ATL_B0_RXBUF_MAX  320U
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+#define HW_ATL_B0_RXBUF_MAX              320U
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+#define HW_ATL_B0_PTP_RXBUF_SIZE          16U
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 #define HW_ATL_B0_RSS_REDIRECTION_MAX 64U
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 #define HW_ATL_B0_RSS_REDIRECTION_BITS 3U
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 #define HW_ATL_B0_RSS_HASHKEY_BITS 320U
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 #define HW_ATL_B0_TCRSS_4_8  1
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-#define HW_ATL_B0_TC_MAX 1U
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+#define HW_ATL_B0_TC_MAX 8U
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 #define HW_ATL_B0_RSS_MAX 8U
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-#define HW_ATL_B0_LRO_RXD_MAX 2U
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+#define HW_ATL_B0_LRO_RXD_MAX 16U
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 #define HW_ATL_B0_RS_SLIP_ENABLED  0U
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 /* (256k -1(max pay_len) - 54(header)) */
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@@ -116,10 +110,17 @@
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 #define HW_ATL_B0_RXD_NCEA0 (0x1)
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 #define HW_ATL_B0_RXD_WB_STAT_RSSTYPE (0x0000000F)
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+#define HW_ATL_B0_RXD_WB_STAT_RSSTYPE_SHIFT (0x0)
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 #define HW_ATL_B0_RXD_WB_STAT_PKTTYPE (0x00000FF0)
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+#define HW_ATL_B0_RXD_WB_STAT_PKTTYPE_SHIFT (0x4)
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 #define HW_ATL_B0_RXD_WB_STAT_RXCTRL  (0x00180000)
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+#define HW_ATL_B0_RXD_WB_STAT_RXCTRL_SHIFT (0x13)
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 #define HW_ATL_B0_RXD_WB_STAT_SPLHDR  (0x00200000)
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 #define HW_ATL_B0_RXD_WB_STAT_HDRLEN  (0xFFC00000)
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+#define HW_ATL_B0_RXD_WB_STAT_HDRLEN_SHIFT (0x16)
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+
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+#define HW_ATL_B0_RXD_WB_PKTTYPE_VLAN          BIT(5)
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+#define HW_ATL_B0_RXD_WB_PKTTYPE_VLAN_DOUBLE   BIT(6)
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 #define HW_ATL_B0_RXD_WB_STAT2_DD      (0x0001)
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 #define HW_ATL_B0_RXD_WB_STAT2_EOP     (0x0002)
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@@ -150,6 +151,10 @@
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 #define HW_ATL_B0_MAX_RXD 8184U
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 #define HW_ATL_B0_MAX_TXD 8184U
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+#define HW_ATL_RSS_DISABLED 0x00000000U
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+#define HW_ATL_RSS_ENABLED_8TCS_2INDEX_BITS 0xA2222222U
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+#define HW_ATL_RSS_ENABLED_4TCS_3INDEX_BITS 0x80003333U
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+
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 /* HW layer capabilities */
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 #endif /* HW_ATL_B0_INTERNAL_H */