~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,10 +1,8 @@
1		-/*
2		- * aQuantia Corporation Network Driver
3		- * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
	1	+// SPDX-License-Identifier: GPL-2.0-only
	2	+/* Atlantic Network Driver
4	3	*
5		- * This program is free software; you can redistribute it and/or modify it
6		- * under the terms and conditions of the GNU General Public License,
7		- * version 2, as published by the Free Software Foundation.
	4	+ * Copyright (C) 2014-2019 aQuantia Corporation
	5	+ * Copyright (C) 2019-2020 Marvell International Ltd.
8	6	*/
9	7
10	8	/* File hw_atl_b0.c: Definition of Atlantic hardware specific functions. */
..	..	@@ -13,6 +11,7 @@
13	11	#include "../aq_hw_utils.h"
14	12	#include "../aq_ring.h"
15	13	#include "../aq_nic.h"
	14	+#include "../aq_phy.h"
16	15	#include "hw_atl_b0.h"
17	16	#include "hw_atl_utils.h"
18	17	#include "hw_atl_llh.h"
..	..	@@ -21,10 +20,11 @@
21	20
22	21	#define DEFAULT_B0_BOARD_BASIC_CAPABILITIES \
23	22	.is_64_dma = true, \
24		- .msix_irqs = 4U, \
	23	+ .op64bit = false, \
	24	+ .msix_irqs = 8U, \
25	25	.irq_mask = ~0U, \
26	26	.vecs = HW_ATL_B0_RSS_MAX, \
27		- .tcs = HW_ATL_B0_TC_MAX, \
	27	+ .tcs_max = HW_ATL_B0_TC_MAX, \
28	28	.rxd_alignment = 1U, \
29	29	.rxd_size = HW_ATL_B0_RXD_SIZE, \
30	30	.rxds_max = HW_ATL_B0_MAX_RXD, \
..	..	@@ -41,7 +41,15 @@
41	41	NETIF_F_RXHASH \| \
42	42	NETIF_F_SG \| \
43	43	NETIF_F_TSO \| \
44		- NETIF_F_LRO, \
	44	+ NETIF_F_TSO6 \| \
	45	+ NETIF_F_LRO \| \
	46	+ NETIF_F_NTUPLE \| \
	47	+ NETIF_F_HW_VLAN_CTAG_FILTER \| \
	48	+ NETIF_F_HW_VLAN_CTAG_RX \| \
	49	+ NETIF_F_HW_VLAN_CTAG_TX \| \
	50	+ NETIF_F_GSO_UDP_L4 \| \
	51	+ NETIF_F_GSO_PARTIAL \| \
	52	+ NETIF_F_HW_TC, \
45	53	.hw_priv_flags = IFF_UNICAST_FLT, \
46	54	.flow_control = true, \
47	55	.mtu = HW_ATL_B0_MTU_JUMBO, \
..	..	@@ -51,38 +59,57 @@
51	59	const struct aq_hw_caps_s hw_atl_b0_caps_aqc100 = {
52	60	DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
53	61	.media_type = AQ_HW_MEDIA_TYPE_FIBRE,
54		- .link_speed_msk = HW_ATL_B0_RATE_10G \|
55		- HW_ATL_B0_RATE_5G \|
56		- HW_ATL_B0_RATE_2G5 \|
57		- HW_ATL_B0_RATE_1G \|
58		- HW_ATL_B0_RATE_100M,
	62	+ .link_speed_msk = AQ_NIC_RATE_10G \|
	63	+ AQ_NIC_RATE_5G \|
	64	+ AQ_NIC_RATE_2G5 \|
	65	+ AQ_NIC_RATE_1G \|
	66	+ AQ_NIC_RATE_100M,
59	67	};
60	68
61	69	const struct aq_hw_caps_s hw_atl_b0_caps_aqc107 = {
62	70	DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
63	71	.media_type = AQ_HW_MEDIA_TYPE_TP,
64		- .link_speed_msk = HW_ATL_B0_RATE_10G \|
65		- HW_ATL_B0_RATE_5G \|
66		- HW_ATL_B0_RATE_2G5 \|
67		- HW_ATL_B0_RATE_1G \|
68		- HW_ATL_B0_RATE_100M,
	72	+ .link_speed_msk = AQ_NIC_RATE_10G \|
	73	+ AQ_NIC_RATE_5G \|
	74	+ AQ_NIC_RATE_2G5 \|
	75	+ AQ_NIC_RATE_1G \|
	76	+ AQ_NIC_RATE_100M,
69	77	};
70	78
71	79	const struct aq_hw_caps_s hw_atl_b0_caps_aqc108 = {
72	80	DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
73	81	.media_type = AQ_HW_MEDIA_TYPE_TP,
74		- .link_speed_msk = HW_ATL_B0_RATE_5G \|
75		- HW_ATL_B0_RATE_2G5 \|
76		- HW_ATL_B0_RATE_1G \|
77		- HW_ATL_B0_RATE_100M,
	82	+ .link_speed_msk = AQ_NIC_RATE_5G \|
	83	+ AQ_NIC_RATE_2G5 \|
	84	+ AQ_NIC_RATE_1G \|
	85	+ AQ_NIC_RATE_100M,
78	86	};
79	87
80	88	const struct aq_hw_caps_s hw_atl_b0_caps_aqc109 = {
81	89	DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
82	90	.media_type = AQ_HW_MEDIA_TYPE_TP,
83		- .link_speed_msk = HW_ATL_B0_RATE_2G5 \|
84		- HW_ATL_B0_RATE_1G \|
85		- HW_ATL_B0_RATE_100M,
	91	+ .link_speed_msk = AQ_NIC_RATE_2G5 \|
	92	+ AQ_NIC_RATE_1G \|
	93	+ AQ_NIC_RATE_100M,
	94	+};
	95	+
	96	+const struct aq_hw_caps_s hw_atl_b0_caps_aqc111 = {
	97	+ DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
	98	+ .media_type = AQ_HW_MEDIA_TYPE_TP,
	99	+ .link_speed_msk = AQ_NIC_RATE_5G \|
	100	+ AQ_NIC_RATE_2G5 \|
	101	+ AQ_NIC_RATE_1G \|
	102	+ AQ_NIC_RATE_100M,
	103	+ .quirks = AQ_NIC_QUIRK_BAD_PTP,
	104	+};
	105	+
	106	+const struct aq_hw_caps_s hw_atl_b0_caps_aqc112 = {
	107	+ DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
	108	+ .media_type = AQ_HW_MEDIA_TYPE_TP,
	109	+ .link_speed_msk = AQ_NIC_RATE_2G5 \|
	110	+ AQ_NIC_RATE_1G \|
	111	+ AQ_NIC_RATE_100M,
	112	+ .quirks = AQ_NIC_QUIRK_BAD_PTP,
86	113	};
87	114
88	115	static int hw_atl_b0_hw_reset(struct aq_hw_s *self)
..	..	@@ -100,12 +127,40 @@
100	127	return err;
101	128	}
102	129
	130	+int hw_atl_b0_set_fc(struct aq_hw_s *self, u32 fc, u32 tc)
	131	+{
	132	+ hw_atl_rpb_rx_xoff_en_per_tc_set(self, !!(fc & AQ_NIC_FC_RX), tc);
	133	+
	134	+ return 0;
	135	+}
	136	+
	137	+static int hw_atl_b0_tc_ptp_set(struct aq_hw_s *self)
	138	+{
	139	+ /* Init TC2 for PTP_TX */
	140	+ hw_atl_tpb_tx_pkt_buff_size_per_tc_set(self, HW_ATL_B0_PTP_TXBUF_SIZE,
	141	+ AQ_HW_PTP_TC);
	142	+
	143	+ /* Init TC2 for PTP_RX */
	144	+ hw_atl_rpb_rx_pkt_buff_size_per_tc_set(self, HW_ATL_B0_PTP_RXBUF_SIZE,
	145	+ AQ_HW_PTP_TC);
	146	+ /* No flow control for PTP */
	147	+ hw_atl_rpb_rx_xoff_en_per_tc_set(self, 0U, AQ_HW_PTP_TC);
	148	+
	149	+ return aq_hw_err_from_flags(self);
	150	+}
	151	+
103	152	static int hw_atl_b0_hw_qos_set(struct aq_hw_s *self)
104	153	{
	154	+ struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
	155	+ u32 tx_buff_size = HW_ATL_B0_TXBUF_MAX;
	156	+ u32 rx_buff_size = HW_ATL_B0_RXBUF_MAX;
	157	+ unsigned int prio = 0U;
105	158	u32 tc = 0U;
106		- u32 buff_size = 0U;
107		- unsigned int i_priority = 0U;
108		- bool is_rx_flow_control = false;
	159	+
	160	+ if (cfg->is_ptp) {
	161	+ tx_buff_size -= HW_ATL_B0_PTP_TXBUF_SIZE;
	162	+ rx_buff_size -= HW_ATL_B0_PTP_RXBUF_SIZE;
	163	+ }
109	164
110	165	/* TPS Descriptor rate init */
111	166	hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U);
..	..	@@ -114,58 +169,51 @@
114	169	/* TPS VM init */
115	170	hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U);
116	171
117		- /* TPS TC credits init */
118		- hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U);
119		- hw_atl_tps_tx_pkt_shed_data_arb_mode_set(self, 0U);
	172	+ tx_buff_size /= cfg->tcs;
	173	+ rx_buff_size /= cfg->tcs;
	174	+ for (tc = 0; tc < cfg->tcs; tc++) {
	175	+ u32 threshold = 0U;
120	176
121		- hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(self, 0xFFF, 0U);
122		- hw_atl_tps_tx_pkt_shed_tc_data_weight_set(self, 0x64, 0U);
123		- hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(self, 0x50, 0U);
124		- hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(self, 0x1E, 0U);
	177	+ /* Tx buf size TC0 */
	178	+ hw_atl_tpb_tx_pkt_buff_size_per_tc_set(self, tx_buff_size, tc);
125	179
126		- /* Tx buf size */
127		- buff_size = HW_ATL_B0_TXBUF_MAX;
	180	+ threshold = (tx_buff_size * (1024 / 32U) * 66U) / 100U;
	181	+ hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(self, threshold, tc);
128	182
129		- hw_atl_tpb_tx_pkt_buff_size_per_tc_set(self, buff_size, tc);
130		- hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(self,
131		- (buff_size *
132		- (1024 / 32U) * 66U) /
133		- 100U, tc);
134		- hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(self,
135		- (buff_size *
136		- (1024 / 32U) * 50U) /
137		- 100U, tc);
	183	+ threshold = (tx_buff_size * (1024 / 32U) * 50U) / 100U;
	184	+ hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(self, threshold, tc);
138	185
139		- /* QoS Rx buf size per TC */
140		- tc = 0;
141		- is_rx_flow_control = (AQ_NIC_FC_RX & self->aq_nic_cfg->flow_control);
142		- buff_size = HW_ATL_B0_RXBUF_MAX;
	186	+ /* QoS Rx buf size per TC */
	187	+ hw_atl_rpb_rx_pkt_buff_size_per_tc_set(self, rx_buff_size, tc);
143	188
144		- hw_atl_rpb_rx_pkt_buff_size_per_tc_set(self, buff_size, tc);
145		- hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(self,
146		- (buff_size *
147		- (1024U / 32U) * 66U) /
148		- 100U, tc);
149		- hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(self,
150		- (buff_size *
151		- (1024U / 32U) * 50U) /
152		- 100U, tc);
153		- hw_atl_rpb_rx_xoff_en_per_tc_set(self, is_rx_flow_control ? 1U : 0U, tc);
	189	+ threshold = (rx_buff_size * (1024U / 32U) * 66U) / 100U;
	190	+ hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(self, threshold, tc);
	191	+
	192	+ threshold = (rx_buff_size * (1024U / 32U) * 50U) / 100U;
	193	+ hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(self, threshold, tc);
	194	+
	195	+ hw_atl_b0_set_fc(self, self->aq_nic_cfg->fc.req, tc);
	196	+ }
	197	+
	198	+ if (cfg->is_ptp)
	199	+ hw_atl_b0_tc_ptp_set(self);
154	200
155	201	/* QoS 802.1p priority -> TC mapping */
156		- for (i_priority = 8U; i_priority--;)
157		- hw_atl_rpf_rpb_user_priority_tc_map_set(self, i_priority, 0U);
	202	+ for (prio = 0; prio < 8; ++prio)
	203	+ hw_atl_rpf_rpb_user_priority_tc_map_set(self, prio,
	204	+ cfg->prio_tc_map[prio]);
158	205
159	206	return aq_hw_err_from_flags(self);
160	207	}
161	208
162		-static int hw_atl_b0_hw_rss_hash_set(struct aq_hw_s *self,
163		- struct aq_rss_parameters *rss_params)
	209	+int hw_atl_b0_hw_rss_hash_set(struct aq_hw_s *self,
	210	+ struct aq_rss_parameters *rss_params)
164	211	{
165	212	struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
166		- int err = 0;
167		- unsigned int i = 0U;
168	213	unsigned int addr = 0U;
	214	+ unsigned int i = 0U;
	215	+ int err = 0;
	216	+ u32 val;
169	217
170	218	for (i = 10, addr = 0U; i--; ++addr) {
171	219	u32 key_data = cfg->is_rss ?
..	..	@@ -173,8 +221,9 @@
173	221	hw_atl_rpf_rss_key_wr_data_set(self, key_data);
174	222	hw_atl_rpf_rss_key_addr_set(self, addr);
175	223	hw_atl_rpf_rss_key_wr_en_set(self, 1U);
176		- AQ_HW_WAIT_FOR(hw_atl_rpf_rss_key_wr_en_get(self) == 0,
177		- 1000U, 10U);
	224	+ err = readx_poll_timeout_atomic(hw_atl_rpf_rss_key_wr_en_get,
	225	+ self, val, val == 0,
	226	+ 1000U, 10000U);
178	227	if (err < 0)
179	228	goto err_exit;
180	229	}
..	..	@@ -188,12 +237,13 @@
188	237	static int hw_atl_b0_hw_rss_set(struct aq_hw_s *self,
189	238	struct aq_rss_parameters *rss_params)
190	239	{
191		- u8 *indirection_table = rss_params->indirection_table;
192		- u32 i = 0U;
193	240	u32 num_rss_queues = max(1U, self->aq_nic_cfg->num_rss_queues);
194		- int err = 0;
	241	+ u8 *indirection_table = rss_params->indirection_table;
195	242	u16 bitary[1 + (HW_ATL_B0_RSS_REDIRECTION_MAX *
196	243	HW_ATL_B0_RSS_REDIRECTION_BITS / 16U)];
	244	+ int err = 0;
	245	+ u32 i = 0U;
	246	+ u32 val;
197	247
198	248	memset(bitary, 0, sizeof(bitary));
199	249
..	..	@@ -207,8 +257,9 @@
207	257	hw_atl_rpf_rss_redir_tbl_wr_data_set(self, bitary[i]);
208	258	hw_atl_rpf_rss_redir_tbl_addr_set(self, i);
209	259	hw_atl_rpf_rss_redir_wr_en_set(self, 1U);
210		- AQ_HW_WAIT_FOR(hw_atl_rpf_rss_redir_wr_en_get(self) == 0,
211		- 1000U, 10U);
	260	+ err = readx_poll_timeout_atomic(hw_atl_rpf_rss_redir_wr_en_get,
	261	+ self, val, val == 0,
	262	+ 1000U, 10000U);
212	263	if (err < 0)
213	264	goto err_exit;
214	265	}
..	..	@@ -219,9 +270,10 @@
219	270	return err;
220	271	}
221	272
222		-static int hw_atl_b0_hw_offload_set(struct aq_hw_s *self,
223		- struct aq_nic_cfg_s *aq_nic_cfg)
	273	+int hw_atl_b0_hw_offload_set(struct aq_hw_s *self,
	274	+ struct aq_nic_cfg_s *aq_nic_cfg)
224	275	{
	276	+ u64 rxcsum = !!(aq_nic_cfg->features & NETIF_F_RXCSUM);
225	277	unsigned int i;
226	278
227	279	/* TX checksums offloads*/
..	..	@@ -229,13 +281,16 @@
229	281	hw_atl_tpo_tcp_udp_crc_offload_en_set(self, 1);
230	282
231	283	/* RX checksums offloads*/
232		- hw_atl_rpo_ipv4header_crc_offload_en_set(self, 1);
233		- hw_atl_rpo_tcp_udp_crc_offload_en_set(self, 1);
	284	+ hw_atl_rpo_ipv4header_crc_offload_en_set(self, rxcsum);
	285	+ hw_atl_rpo_tcp_udp_crc_offload_en_set(self, rxcsum);
234	286
235	287	/* LSO offloads*/
236	288	hw_atl_tdm_large_send_offload_en_set(self, 0xFFFFFFFFU);
237	289
238		-/* LRO offloads */
	290	+ /* Outer VLAN tag offload */
	291	+ hw_atl_rpo_outer_vlan_tag_mode_set(self, 1U);
	292	+
	293	+ /* LRO offloads */
239	294	{
240	295	unsigned int val = (8U < HW_ATL_B0_LRO_RXD_MAX) ? 0x3U :
241	296	((4U < HW_ATL_B0_LRO_RXD_MAX) ? 0x2U :
..	..	@@ -246,13 +301,18 @@
246	301
247	302	hw_atl_rpo_lro_time_base_divider_set(self, 0x61AU);
248	303	hw_atl_rpo_lro_inactive_interval_set(self, 0);
249		- hw_atl_rpo_lro_max_coalescing_interval_set(self, 2);
	304	+ /* the LRO timebase divider is 5 uS (0x61a),
	305	+ * which is multiplied by 50(0x32)
	306	+ * to get a maximum coalescing interval of 250 uS,
	307	+ * which is the default value
	308	+ */
	309	+ hw_atl_rpo_lro_max_coalescing_interval_set(self, 50);
250	310
251	311	hw_atl_rpo_lro_qsessions_lim_set(self, 1U);
252	312
253	313	hw_atl_rpo_lro_total_desc_lim_set(self, 2U);
254	314
255		- hw_atl_rpo_lro_patch_optimization_en_set(self, 0U);
	315	+ hw_atl_rpo_lro_patch_optimization_en_set(self, 1U);
256	316
257	317	hw_atl_rpo_lro_min_pay_of_first_pkt_set(self, 10U);
258	318
..	..	@@ -260,12 +320,139 @@
260	320
261	321	hw_atl_rpo_lro_en_set(self,
262	322	aq_nic_cfg->is_lro ? 0xFFFFFFFFU : 0U);
	323	+ hw_atl_itr_rsc_en_set(self,
	324	+ aq_nic_cfg->is_lro ? 0xFFFFFFFFU : 0U);
	325	+
	326	+ hw_atl_itr_rsc_delay_set(self, 1U);
263	327	}
	328	+
	329	+ return aq_hw_err_from_flags(self);
	330	+}
	331	+
	332	+static int hw_atl_b0_hw_init_tx_tc_rate_limit(struct aq_hw_s *self)
	333	+{
	334	+ static const u32 max_weight = BIT(HW_ATL_TPS_DATA_TCTWEIGHT_WIDTH) - 1;
	335	+ /* Scale factor is based on the number of bits in fractional portion */
	336	+ static const u32 scale = BIT(HW_ATL_TPS_DESC_RATE_Y_WIDTH);
	337	+ static const u32 frac_msk = HW_ATL_TPS_DESC_RATE_Y_MSK >>
	338	+ HW_ATL_TPS_DESC_RATE_Y_SHIFT;
	339	+ const u32 link_speed = self->aq_link_status.mbps;
	340	+ struct aq_nic_cfg_s *nic_cfg = self->aq_nic_cfg;
	341	+ unsigned long num_min_rated_tcs = 0;
	342	+ u32 tc_weight[AQ_CFG_TCS_MAX];
	343	+ u32 fixed_max_credit;
	344	+ u8 min_rate_msk = 0;
	345	+ u32 sum_weight = 0;
	346	+ int tc;
	347	+
	348	+ /* By default max_credit is based upon MTU (in unit of 64b) */
	349	+ fixed_max_credit = nic_cfg->aq_hw_caps->mtu / 64;
	350	+
	351	+ if (link_speed) {
	352	+ min_rate_msk = nic_cfg->tc_min_rate_msk &
	353	+ (BIT(nic_cfg->tcs) - 1);
	354	+ num_min_rated_tcs = hweight8(min_rate_msk);
	355	+ }
	356	+
	357	+ /* First, calculate weights where min_rate is specified */
	358	+ if (num_min_rated_tcs) {
	359	+ for (tc = 0; tc != nic_cfg->tcs; tc++) {
	360	+ if (!nic_cfg->tc_min_rate[tc]) {
	361	+ tc_weight[tc] = 0;
	362	+ continue;
	363	+ }
	364	+
	365	+ tc_weight[tc] = (-1L + link_speed +
	366	+ nic_cfg->tc_min_rate[tc] *
	367	+ max_weight) /
	368	+ link_speed;
	369	+ tc_weight[tc] = min(tc_weight[tc], max_weight);
	370	+ sum_weight += tc_weight[tc];
	371	+ }
	372	+ }
	373	+
	374	+ /* WSP, if min_rate is set for at least one TC.
	375	+ * RR otherwise.
	376	+ *
	377	+ * NB! MAC FW sets arb mode itself if PTP is enabled. We shouldn't
	378	+ * overwrite it here in that case.
	379	+ */
	380	+ if (!nic_cfg->is_ptp)
	381	+ hw_atl_tps_tx_pkt_shed_data_arb_mode_set(self, min_rate_msk ? 1U : 0U);
	382	+
	383	+ /* Data TC Arbiter takes precedence over Descriptor TC Arbiter,
	384	+ * leave Descriptor TC Arbiter as RR.
	385	+ */
	386	+ hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U);
	387	+
	388	+ hw_atl_tps_tx_desc_rate_mode_set(self, nic_cfg->is_qos ? 1U : 0U);
	389	+
	390	+ for (tc = 0; tc != nic_cfg->tcs; tc++) {
	391	+ const u32 en = (nic_cfg->tc_max_rate[tc] != 0) ? 1U : 0U;
	392	+ const u32 desc = AQ_NIC_CFG_TCVEC2RING(nic_cfg, tc, 0);
	393	+ u32 weight, max_credit;
	394	+
	395	+ hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(self, tc,
	396	+ fixed_max_credit);
	397	+ hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(self, tc, 0x1E);
	398	+
	399	+ if (num_min_rated_tcs) {
	400	+ weight = tc_weight[tc];
	401	+
	402	+ if (!weight && sum_weight < max_weight)
	403	+ weight = (max_weight - sum_weight) /
	404	+ (nic_cfg->tcs - num_min_rated_tcs);
	405	+ else if (!weight)
	406	+ weight = 0x64;
	407	+
	408	+ max_credit = max(8 * weight, fixed_max_credit);
	409	+ } else {
	410	+ weight = 0x64;
	411	+ max_credit = 0xFFF;
	412	+ }
	413	+
	414	+ hw_atl_tps_tx_pkt_shed_tc_data_weight_set(self, tc, weight);
	415	+ hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(self, tc,
	416	+ max_credit);
	417	+
	418	+ hw_atl_tps_tx_desc_rate_en_set(self, desc, en);
	419	+
	420	+ if (en) {
	421	+ /* Nominal rate is always 10G */
	422	+ const u32 rate = 10000U * scale /
	423	+ nic_cfg->tc_max_rate[tc];
	424	+ const u32 rate_int = rate >>
	425	+ HW_ATL_TPS_DESC_RATE_Y_WIDTH;
	426	+ const u32 rate_frac = rate & frac_msk;
	427	+
	428	+ hw_atl_tps_tx_desc_rate_x_set(self, desc, rate_int);
	429	+ hw_atl_tps_tx_desc_rate_y_set(self, desc, rate_frac);
	430	+ } else {
	431	+ /* A value of 1 indicates the queue is not
	432	+ * rate controlled.
	433	+ */
	434	+ hw_atl_tps_tx_desc_rate_x_set(self, desc, 1U);
	435	+ hw_atl_tps_tx_desc_rate_y_set(self, desc, 0U);
	436	+ }
	437	+ }
	438	+ for (tc = nic_cfg->tcs; tc != AQ_CFG_TCS_MAX; tc++) {
	439	+ const u32 desc = AQ_NIC_CFG_TCVEC2RING(nic_cfg, tc, 0);
	440	+
	441	+ hw_atl_tps_tx_desc_rate_en_set(self, desc, 0U);
	442	+ hw_atl_tps_tx_desc_rate_x_set(self, desc, 1U);
	443	+ hw_atl_tps_tx_desc_rate_y_set(self, desc, 0U);
	444	+ }
	445	+
264	446	return aq_hw_err_from_flags(self);
265	447	}
266	448
267	449	static int hw_atl_b0_hw_init_tx_path(struct aq_hw_s *self)
268	450	{
	451	+ struct aq_nic_cfg_s *nic_cfg = self->aq_nic_cfg;
	452	+
	453	+ /* Tx TC/Queue number config */
	454	+ hw_atl_tpb_tps_tx_tc_mode_set(self, nic_cfg->tc_mode);
	455	+
269	456	hw_atl_thm_lso_tcp_flag_of_first_pkt_set(self, 0x0FF6U);
270	457	hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(self, 0x0FF6U);
271	458	hw_atl_thm_lso_tcp_flag_of_last_pkt_set(self, 0x0F7FU);
..	..	@@ -274,7 +461,7 @@
274	461	hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 1U);
275	462
276	463	/* misc */
277		- aq_hw_write_reg(self, 0x00007040U, IS_CHIP_FEATURE(TPO2) ?
	464	+ aq_hw_write_reg(self, 0x00007040U, ATL_HW_IS_CHIP_FEATURE(self, TPO2) ?
278	465	0x00010000U : 0x00000000U);
279	466	hw_atl_tdm_tx_dca_en_set(self, 0U);
280	467	hw_atl_tdm_tx_dca_mode_set(self, 0U);
..	..	@@ -284,20 +471,32 @@
284	471	return aq_hw_err_from_flags(self);
285	472	}
286	473
	474	+void hw_atl_b0_hw_init_rx_rss_ctrl1(struct aq_hw_s *self)
	475	+{
	476	+ struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
	477	+ u32 rss_ctrl1 = HW_ATL_RSS_DISABLED;
	478	+
	479	+ if (cfg->is_rss)
	480	+ rss_ctrl1 = (cfg->tc_mode == AQ_TC_MODE_8TCS) ?
	481	+ HW_ATL_RSS_ENABLED_8TCS_2INDEX_BITS :
	482	+ HW_ATL_RSS_ENABLED_4TCS_3INDEX_BITS;
	483	+
	484	+ hw_atl_reg_rx_flr_rss_control1set(self, rss_ctrl1);
	485	+}
	486	+
287	487	static int hw_atl_b0_hw_init_rx_path(struct aq_hw_s *self)
288	488	{
289	489	struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
290	490	int i;
291	491
292	492	/* Rx TC/RSS number config */
293		- hw_atl_rpb_rpf_rx_traf_class_mode_set(self, 1U);
	493	+ hw_atl_rpb_rpf_rx_traf_class_mode_set(self, cfg->tc_mode);
294	494
295	495	/* Rx flow control */
296	496	hw_atl_rpb_rx_flow_ctl_mode_set(self, 1U);
297	497
298	498	/* RSS Ring selection */
299		- hw_atl_reg_rx_flr_rss_control1set(self, cfg->is_rss ?
300		- 0xB3333333U : 0x00000000U);
	499	+ hw_atl_b0_hw_init_rx_rss_ctrl1(self);
301	500
302	501	/* Multicast filters */
303	502	for (i = HW_ATL_B0_MAC_MAX; i--;) {
..	..	@@ -312,27 +511,18 @@
312	511	hw_atl_rpf_vlan_outer_etht_set(self, 0x88A8U);
313	512	hw_atl_rpf_vlan_inner_etht_set(self, 0x8100U);
314	513
315		- if (cfg->vlan_id) {
316		- hw_atl_rpf_vlan_flr_act_set(self, 1U, 0U);
317		- hw_atl_rpf_vlan_id_flr_set(self, 0U, 0U);
318		- hw_atl_rpf_vlan_flr_en_set(self, 0U, 0U);
	514	+ hw_atl_rpf_vlan_prom_mode_en_set(self, 1);
319	515
320		- hw_atl_rpf_vlan_accept_untagged_packets_set(self, 1U);
321		- hw_atl_rpf_vlan_untagged_act_set(self, 1U);
322		-
323		- hw_atl_rpf_vlan_flr_act_set(self, 1U, 1U);
324		- hw_atl_rpf_vlan_id_flr_set(self, cfg->vlan_id, 0U);
325		- hw_atl_rpf_vlan_flr_en_set(self, 1U, 1U);
326		- } else {
327		- hw_atl_rpf_vlan_prom_mode_en_set(self, 1);
328		- }
	516	+ // Always accept untagged packets
	517	+ hw_atl_rpf_vlan_accept_untagged_packets_set(self, 1U);
	518	+ hw_atl_rpf_vlan_untagged_act_set(self, 1U);
329	519
330	520	/* Rx Interrupts */
331	521	hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 1U);
332	522
333	523	/* misc */
334		- aq_hw_write_reg(self, 0x00005040U,
335		- IS_CHIP_FEATURE(RPF2) ? 0x000F0000U : 0x00000000U);
	524	+ aq_hw_write_reg(self, 0x00005040U, ATL_HW_IS_CHIP_FEATURE(self, RPF2) ?
	525	+ 0x000F0000U : 0x00000000U);
336	526
337	527	hw_atl_rpfl2broadcast_flr_act_set(self, 1U);
338	528	hw_atl_rpfl2broadcast_count_threshold_set(self, 0xFFFFU & (~0U / 256U));
..	..	@@ -343,11 +533,11 @@
343	533	return aq_hw_err_from_flags(self);
344	534	}
345	535
346		-static int hw_atl_b0_hw_mac_addr_set(struct aq_hw_s self, u8 mac_addr)
	536	+int hw_atl_b0_hw_mac_addr_set(struct aq_hw_s self, u8 mac_addr)
347	537	{
348		- int err = 0;
349	538	unsigned int h = 0U;
350	539	unsigned int l = 0U;
	540	+ int err = 0;
351	541
352	542	if (!mac_addr) {
353	543	err = -EINVAL;
..	..	@@ -371,16 +561,15 @@
371	561	static int hw_atl_b0_hw_init(struct aq_hw_s self, u8 mac_addr)
372	562	{
373	563	static u32 aq_hw_atl_igcr_table_[4][2] = {
374		- { 0x20000000U, 0x20000000U }, /* AQ_IRQ_INVALID */
375		- { 0x20000080U, 0x20000080U }, /* AQ_IRQ_LEGACY */
376		- { 0x20000021U, 0x20000025U }, /* AQ_IRQ_MSI */
377		- { 0x20000022U, 0x20000026U } /* AQ_IRQ_MSIX */
	564	+ [AQ_HW_IRQ_INVALID] = { 0x20000000U, 0x20000000U },
	565	+ [AQ_HW_IRQ_LEGACY] = { 0x20000080U, 0x20000080U },
	566	+ [AQ_HW_IRQ_MSI] = { 0x20000021U, 0x20000025U },
	567	+ [AQ_HW_IRQ_MSIX] = { 0x20000022U, 0x20000026U },
378	568	};
379		-
	569	+ struct aq_nic_cfg_s *aq_nic_cfg = self->aq_nic_cfg;
380	570	int err = 0;
381	571	u32 val;
382	572
383		- struct aq_nic_cfg_s *aq_nic_cfg = self->aq_nic_cfg;
384	573
385	574	hw_atl_b0_hw_init_tx_path(self);
386	575	hw_atl_b0_hw_init_rx_path(self);
..	..	@@ -423,8 +612,15 @@
423	612
424	613	/* Interrupts */
425	614	hw_atl_reg_gen_irq_map_set(self,
426		- ((HW_ATL_B0_ERR_INT << 0x18) \| (1U << 0x1F)) \|
427		- ((HW_ATL_B0_ERR_INT << 0x10) \| (1U << 0x17)), 0U);
	615	+ ((HW_ATL_B0_ERR_INT << 0x18) \|
	616	+ (1U << 0x1F)) \|
	617	+ ((HW_ATL_B0_ERR_INT << 0x10) \|
	618	+ (1U << 0x17)), 0U);
	619	+
	620	+ /* Enable link interrupt */
	621	+ if (aq_nic_cfg->link_irq_vec)
	622	+ hw_atl_reg_gen_irq_map_set(self, BIT(7) \|
	623	+ aq_nic_cfg->link_irq_vec, 3U);
428	624
429	625	hw_atl_b0_hw_offload_set(self, aq_nic_cfg);
430	626
..	..	@@ -432,24 +628,25 @@
432	628	return err;
433	629	}
434	630
435		-static int hw_atl_b0_hw_ring_tx_start(struct aq_hw_s *self,
436		- struct aq_ring_s *ring)
	631	+int hw_atl_b0_hw_ring_tx_start(struct aq_hw_s self, struct aq_ring_s ring)
437	632	{
438	633	hw_atl_tdm_tx_desc_en_set(self, 1, ring->idx);
	634	+
439	635	return aq_hw_err_from_flags(self);
440	636	}
441	637
442		-static int hw_atl_b0_hw_ring_rx_start(struct aq_hw_s *self,
443		- struct aq_ring_s *ring)
	638	+int hw_atl_b0_hw_ring_rx_start(struct aq_hw_s self, struct aq_ring_s ring)
444	639	{
445	640	hw_atl_rdm_rx_desc_en_set(self, 1, ring->idx);
	641	+
446	642	return aq_hw_err_from_flags(self);
447	643	}
448	644
449		-static int hw_atl_b0_hw_start(struct aq_hw_s *self)
	645	+int hw_atl_b0_hw_start(struct aq_hw_s *self)
450	646	{
451	647	hw_atl_tpb_tx_buff_en_set(self, 1);
452	648	hw_atl_rpb_rx_buff_en_set(self, 1);
	649	+
453	650	return aq_hw_err_from_flags(self);
454	651	}
455	652
..	..	@@ -457,18 +654,19 @@
457	654	struct aq_ring_s *ring)
458	655	{
459	656	hw_atl_reg_tx_dma_desc_tail_ptr_set(self, ring->sw_tail, ring->idx);
	657	+
460	658	return 0;
461	659	}
462	660
463		-static int hw_atl_b0_hw_ring_tx_xmit(struct aq_hw_s *self,
464		- struct aq_ring_s *ring,
465		- unsigned int frags)
	661	+int hw_atl_b0_hw_ring_tx_xmit(struct aq_hw_s self, struct aq_ring_s ring,
	662	+ unsigned int frags)
466	663	{
467	664	struct aq_ring_buff_s *buff = NULL;
468	665	struct hw_atl_txd_s *txd = NULL;
469	666	unsigned int buff_pa_len = 0U;
470		- unsigned int pkt_len = 0U;
471	667	unsigned int frag_count = 0U;
	668	+ unsigned int pkt_len = 0U;
	669	+ bool is_vlan = false;
472	670	bool is_gso = false;
473	671
474	672	buff = &ring->buff_ring[ring->sw_tail];
..	..	@@ -483,36 +681,45 @@
483	681
484	682	buff = &ring->buff_ring[ring->sw_tail];
485	683
486		- if (buff->is_txc) {
	684	+ if (buff->is_gso_tcp \|\| buff->is_gso_udp) {
	685	+ if (buff->is_gso_tcp)
	686	+ txd->ctl \|= HW_ATL_B0_TXD_CTL_CMD_TCP;
	687	+ txd->ctl \|= HW_ATL_B0_TXD_CTL_DESC_TYPE_TXC;
487	688	txd->ctl \|= (buff->len_l3 << 31) \|
488		- (buff->len_l2 << 24) \|
489		- HW_ATL_B0_TXD_CTL_CMD_TCP \|
490		- HW_ATL_B0_TXD_CTL_DESC_TYPE_TXC;
491		- txd->ctl2 \|= (buff->mss << 16) \|
492		- (buff->len_l4 << 8) \|
493		- (buff->len_l3 >> 1);
	689	+ (buff->len_l2 << 24);
	690	+ txd->ctl2 \|= (buff->mss << 16);
	691	+ is_gso = true;
494	692
495	693	pkt_len -= (buff->len_l4 +
496	694	buff->len_l3 +
497	695	buff->len_l2);
498		- is_gso = true;
499		-
500	696	if (buff->is_ipv6)
501	697	txd->ctl \|= HW_ATL_B0_TXD_CTL_CMD_IPV6;
502		- } else {
	698	+ txd->ctl2 \|= (buff->len_l4 << 8) \|
	699	+ (buff->len_l3 >> 1);
	700	+ }
	701	+ if (buff->is_vlan) {
	702	+ txd->ctl \|= HW_ATL_B0_TXD_CTL_DESC_TYPE_TXC;
	703	+ txd->ctl \|= buff->vlan_tx_tag << 4;
	704	+ is_vlan = true;
	705	+ }
	706	+ if (!buff->is_gso_tcp && !buff->is_gso_udp && !buff->is_vlan) {
503	707	buff_pa_len = buff->len;
504	708
505	709	txd->buf_addr = buff->pa;
506	710	txd->ctl \|= (HW_ATL_B0_TXD_CTL_BLEN &
507	711	((u32)buff_pa_len << 4));
508	712	txd->ctl \|= HW_ATL_B0_TXD_CTL_DESC_TYPE_TXD;
	713	+
509	714	/* PAY_LEN */
510	715	txd->ctl2 \|= HW_ATL_B0_TXD_CTL2_LEN & (pkt_len << 14);
511	716
512		- if (is_gso) {
513		- txd->ctl \|= HW_ATL_B0_TXD_CTL_CMD_LSO;
	717	+ if (is_gso \|\| is_vlan) {
	718	+ /* enable tx context */
514	719	txd->ctl2 \|= HW_ATL_B0_TXD_CTL2_CTX_EN;
515	720	}
	721	+ if (is_gso)
	722	+ txd->ctl \|= HW_ATL_B0_TXD_CTL_CMD_LSO;
516	723
517	724	/* Tx checksum offloads */
518	725	if (buff->is_ip_cso)
..	..	@@ -521,26 +728,30 @@
521	728	if (buff->is_udp_cso \|\| buff->is_tcp_cso)
522	729	txd->ctl \|= HW_ATL_B0_TXD_CTL_CMD_TUCSO;
523	730
	731	+ if (is_vlan)
	732	+ txd->ctl \|= HW_ATL_B0_TXD_CTL_CMD_VLAN;
	733	+
524	734	if (unlikely(buff->is_eop)) {
525	735	txd->ctl \|= HW_ATL_B0_TXD_CTL_EOP;
526	736	txd->ctl \|= HW_ATL_B0_TXD_CTL_CMD_WB;
527	737	is_gso = false;
	738	+ is_vlan = false;
528	739	}
529	740	}
530		-
531	741	ring->sw_tail = aq_ring_next_dx(ring, ring->sw_tail);
532	742	}
533	743
534	744	hw_atl_b0_hw_tx_ring_tail_update(self, ring);
	745	+
535	746	return aq_hw_err_from_flags(self);
536	747	}
537	748
538		-static int hw_atl_b0_hw_ring_rx_init(struct aq_hw_s *self,
539		- struct aq_ring_s *aq_ring,
540		- struct aq_ring_param_s *aq_ring_param)
	749	+int hw_atl_b0_hw_ring_rx_init(struct aq_hw_s self, struct aq_ring_s aq_ring,
	750	+ struct aq_ring_param_s *aq_ring_param)
541	751	{
542		- u32 dma_desc_addr_lsw = (u32)aq_ring->dx_ring_pa;
543	752	u32 dma_desc_addr_msw = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);
	753	+ u32 vlan_rx_stripping = self->aq_nic_cfg->is_vlan_rx_strip;
	754	+ u32 dma_desc_addr_lsw = (u32)aq_ring->dx_ring_pa;
544	755
545	756	hw_atl_rdm_rx_desc_en_set(self, false, aq_ring->idx);
546	757
..	..	@@ -560,7 +771,8 @@
560	771
561	772	hw_atl_rdm_rx_desc_head_buff_size_set(self, 0U, aq_ring->idx);
562	773	hw_atl_rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
563		- hw_atl_rpo_rx_desc_vlan_stripping_set(self, 0U, aq_ring->idx);
	774	+ hw_atl_rpo_rx_desc_vlan_stripping_set(self, !!vlan_rx_stripping,
	775	+ aq_ring->idx);
564	776
565	777	/* Rx ring set mode */
566	778
..	..	@@ -576,12 +788,11 @@
576	788	return aq_hw_err_from_flags(self);
577	789	}
578	790
579		-static int hw_atl_b0_hw_ring_tx_init(struct aq_hw_s *self,
580		- struct aq_ring_s *aq_ring,
581		- struct aq_ring_param_s *aq_ring_param)
	791	+int hw_atl_b0_hw_ring_tx_init(struct aq_hw_s self, struct aq_ring_s aq_ring,
	792	+ struct aq_ring_param_s *aq_ring_param)
582	793	{
583		- u32 dma_desc_lsw_addr = (u32)aq_ring->dx_ring_pa;
584	794	u32 dma_desc_msw_addr = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);
	795	+ u32 dma_desc_lsw_addr = (u32)aq_ring->dx_ring_pa;
585	796
586	797	hw_atl_reg_tx_dma_desc_base_addresslswset(self, dma_desc_lsw_addr,
587	798	aq_ring->idx);
..	..	@@ -606,9 +817,8 @@
606	817	return aq_hw_err_from_flags(self);
607	818	}
608	819
609		-static int hw_atl_b0_hw_ring_rx_fill(struct aq_hw_s *self,
610		- struct aq_ring_s *ring,
611		- unsigned int sw_tail_old)
	820	+int hw_atl_b0_hw_ring_rx_fill(struct aq_hw_s self, struct aq_ring_s ring,
	821	+ unsigned int sw_tail_old)
612	822	{
613	823	for (; sw_tail_old != ring->sw_tail;
614	824	sw_tail_old = aq_ring_next_dx(ring, sw_tail_old)) {
..	..	@@ -627,16 +837,65 @@
627	837	return aq_hw_err_from_flags(self);
628	838	}
629	839
630		-static int hw_atl_b0_hw_ring_tx_head_update(struct aq_hw_s *self,
631		- struct aq_ring_s *ring)
	840	+static int hw_atl_b0_hw_ring_hwts_rx_fill(struct aq_hw_s *self,
	841	+ struct aq_ring_s *ring)
632	842	{
	843	+ unsigned int i;
	844	+
	845	+ for (i = aq_ring_avail_dx(ring); i--;
	846	+ ring->sw_tail = aq_ring_next_dx(ring, ring->sw_tail)) {
	847	+ struct hw_atl_rxd_s *rxd =
	848	+ (struct hw_atl_rxd_s *)
	849	+ &ring->dx_ring[ring->sw_tail * HW_ATL_B0_RXD_SIZE];
	850	+
	851	+ rxd->buf_addr = ring->dx_ring_pa + ring->size * ring->dx_size;
	852	+ rxd->hdr_addr = 0U;
	853	+ }
	854	+ /* Make sure descriptors are updated before bump tail*/
	855	+ wmb();
	856	+
	857	+ hw_atl_reg_rx_dma_desc_tail_ptr_set(self, ring->sw_tail, ring->idx);
	858	+
	859	+ return aq_hw_err_from_flags(self);
	860	+}
	861	+
	862	+static int hw_atl_b0_hw_ring_hwts_rx_receive(struct aq_hw_s *self,
	863	+ struct aq_ring_s *ring)
	864	+{
	865	+ while (ring->hw_head != ring->sw_tail) {
	866	+ struct hw_atl_rxd_hwts_wb_s *hwts_wb =
	867	+ (struct hw_atl_rxd_hwts_wb_s *)
	868	+ (ring->dx_ring + (ring->hw_head * HW_ATL_B0_RXD_SIZE));
	869	+
	870	+ /* RxD is not done */
	871	+ if (!(hwts_wb->sec_lw0 & 0x1U))
	872	+ break;
	873	+
	874	+ ring->hw_head = aq_ring_next_dx(ring, ring->hw_head);
	875	+ }
	876	+
	877	+ return aq_hw_err_from_flags(self);
	878	+}
	879	+
	880	+int hw_atl_b0_hw_ring_tx_head_update(struct aq_hw_s *self,
	881	+ struct aq_ring_s *ring)
	882	+{
	883	+ unsigned int hw_head_;
633	884	int err = 0;
634		- unsigned int hw_head_ = hw_atl_tdm_tx_desc_head_ptr_get(self, ring->idx);
	885	+
	886	+ hw_head_ = hw_atl_tdm_tx_desc_head_ptr_get(self, ring->idx);
635	887
636	888	if (aq_utils_obj_test(&self->flags, AQ_HW_FLAG_ERR_UNPLUG)) {
637	889	err = -ENXIO;
638	890	goto err_exit;
639	891	}
	892	+
	893	+ /* Validate that the new hw_head_ is reasonable. */
	894	+ if (hw_head_ >= ring->size) {
	895	+ err = -ENXIO;
	896	+ goto err_exit;
	897	+ }
	898	+
640	899	ring->hw_head = hw_head_;
641	900	err = aq_hw_err_from_flags(self);
642	901
..	..	@@ -644,11 +903,8 @@
644	903	return err;
645	904	}
646	905
647		-static int hw_atl_b0_hw_ring_rx_receive(struct aq_hw_s *self,
648		- struct aq_ring_s *ring)
	906	+int hw_atl_b0_hw_ring_rx_receive(struct aq_hw_s self, struct aq_ring_s ring)
649	907	{
650		- struct device *ndev = aq_nic_get_dev(ring->aq_nic);
651		-
652	908	for (; ring->hw_head != ring->sw_tail;
653	909	ring->hw_head = aq_ring_next_dx(ring, ring->hw_head)) {
654	910	struct aq_ring_buff_s *buff = NULL;
..	..	@@ -665,11 +921,15 @@
665	921
666	922	buff = &ring->buff_ring[ring->hw_head];
667	923
	924	+ buff->flags = 0U;
	925	+ buff->is_hash_l4 = 0U;
	926	+
668	927	rx_stat = (0x0000003CU & rxd_wb->status) >> 2;
669	928
670	929	is_rx_check_sum_enabled = (rxd_wb->type >> 19) & 0x3U;
671	930
672		- pkt_type = 0xFFU & (rxd_wb->type >> 4);
	931	+ pkt_type = (rxd_wb->type & HW_ATL_B0_RXD_WB_STAT_PKTTYPE) >>
	932	+ HW_ATL_B0_RXD_WB_STAT_PKTTYPE_SHIFT;
673	933
674	934	if (is_rx_check_sum_enabled & BIT(0) &&
675	935	(0x0U == (pkt_type & 0x3U)))
..	..	@@ -690,7 +950,12 @@
690	950	buff->is_cso_err = 0U;
691	951	}
692	952
693		- dma_unmap_page(ndev, buff->pa, buff->len, DMA_FROM_DEVICE);
	953	+ if (self->aq_nic_cfg->is_vlan_rx_strip &&
	954	+ ((pkt_type & HW_ATL_B0_RXD_WB_PKTTYPE_VLAN) \|\|
	955	+ (pkt_type & HW_ATL_B0_RXD_WB_PKTTYPE_VLAN_DOUBLE))) {
	956	+ buff->is_vlan = 1;
	957	+ buff->vlan_rx_tag = le16_to_cpu(rxd_wb->vlan);
	958	+ }
694	959
695	960	if ((rx_stat & BIT(0)) \|\| rxd_wb->type & 0x1000U) {
696	961	/* MAC error or DMA error */
..	..	@@ -707,6 +972,8 @@
707	972	}
708	973	}
709	974
	975	+ buff->is_lro = !!(HW_ATL_B0_RXD_WB_STAT2_RSCCNT &
	976	+ rxd_wb->status);
710	977	if (HW_ATL_B0_RXD_WB_STAT2_EOP & rxd_wb->status) {
711	978	buff->len = rxd_wb->pkt_len %
712	979	AQ_CFG_RX_FRAME_MAX;
..	..	@@ -719,8 +986,7 @@
719	986	rxd_wb->pkt_len > AQ_CFG_RX_FRAME_MAX ?
720	987	AQ_CFG_RX_FRAME_MAX : rxd_wb->pkt_len;
721	988
722		- if (HW_ATL_B0_RXD_WB_STAT2_RSCCNT &
723		- rxd_wb->status) {
	989	+ if (buff->is_lro) {
724	990	/* LRO */
725	991	buff->next = rxd_wb->next_desc_ptr;
726	992	++ring->stats.rx.lro_packets;
..	..	@@ -737,50 +1003,64 @@
737	1003	return aq_hw_err_from_flags(self);
738	1004	}
739	1005
740		-static int hw_atl_b0_hw_irq_enable(struct aq_hw_s *self, u64 mask)
	1006	+int hw_atl_b0_hw_irq_enable(struct aq_hw_s *self, u64 mask)
741	1007	{
742	1008	hw_atl_itr_irq_msk_setlsw_set(self, LODWORD(mask));
	1009	+
743	1010	return aq_hw_err_from_flags(self);
744	1011	}
745	1012
746		-static int hw_atl_b0_hw_irq_disable(struct aq_hw_s *self, u64 mask)
	1013	+int hw_atl_b0_hw_irq_disable(struct aq_hw_s *self, u64 mask)
747	1014	{
748	1015	hw_atl_itr_irq_msk_clearlsw_set(self, LODWORD(mask));
749	1016	hw_atl_itr_irq_status_clearlsw_set(self, LODWORD(mask));
750	1017
751	1018	atomic_inc(&self->dpc);
	1019	+
752	1020	return aq_hw_err_from_flags(self);
753	1021	}
754	1022
755		-static int hw_atl_b0_hw_irq_read(struct aq_hw_s self, u64 mask)
	1023	+int hw_atl_b0_hw_irq_read(struct aq_hw_s self, u64 mask)
756	1024	{
757	1025	*mask = hw_atl_itr_irq_statuslsw_get(self);
	1026	+
758	1027	return aq_hw_err_from_flags(self);
759	1028	}
760	1029
761	1030	#define IS_FILTER_ENABLED(_F_) ((packet_filter & (_F_)) ? 1U : 0U)
762	1031
763		-static int hw_atl_b0_hw_packet_filter_set(struct aq_hw_s *self,
764		- unsigned int packet_filter)
	1032	+int hw_atl_b0_hw_packet_filter_set(struct aq_hw_s *self,
	1033	+ unsigned int packet_filter)
765	1034	{
	1035	+ struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
766	1036	unsigned int i = 0U;
	1037	+ u32 vlan_promisc;
	1038	+ u32 l2_promisc;
767	1039
768		- hw_atl_rpfl2promiscuous_mode_en_set(self, IS_FILTER_ENABLED(IFF_PROMISC));
	1040	+ l2_promisc = IS_FILTER_ENABLED(IFF_PROMISC) \|\|
	1041	+ !!(cfg->priv_flags & BIT(AQ_HW_LOOPBACK_DMA_NET));
	1042	+ vlan_promisc = l2_promisc \|\| cfg->is_vlan_force_promisc;
	1043	+
	1044	+ hw_atl_rpfl2promiscuous_mode_en_set(self, l2_promisc);
	1045	+
	1046	+ hw_atl_rpf_vlan_prom_mode_en_set(self, vlan_promisc);
	1047	+
769	1048	hw_atl_rpfl2multicast_flr_en_set(self,
770		- IS_FILTER_ENABLED(IFF_ALLMULTI), 0);
	1049	+ IS_FILTER_ENABLED(IFF_ALLMULTI) &&
	1050	+ IS_FILTER_ENABLED(IFF_MULTICAST), 0);
771	1051
772	1052	hw_atl_rpfl2_accept_all_mc_packets_set(self,
773		- IS_FILTER_ENABLED(IFF_ALLMULTI));
	1053	+ IS_FILTER_ENABLED(IFF_ALLMULTI) &&
	1054	+ IS_FILTER_ENABLED(IFF_MULTICAST));
774	1055
775	1056	hw_atl_rpfl2broadcast_en_set(self, IS_FILTER_ENABLED(IFF_BROADCAST));
776	1057
777		- self->aq_nic_cfg->is_mc_list_enabled = IS_FILTER_ENABLED(IFF_MULTICAST);
778	1058
779	1059	for (i = HW_ATL_B0_MAC_MIN; i < HW_ATL_B0_MAC_MAX; ++i)
780	1060	hw_atl_rpfl2_uc_flr_en_set(self,
781		- (self->aq_nic_cfg->is_mc_list_enabled &&
782		- (i <= self->aq_nic_cfg->mc_list_count)) ?
783		- 1U : 0U, i);
	1061	+ (cfg->is_mc_list_enabled &&
	1062	+ (i <= cfg->mc_list_count)) ?
	1063	+ 1U : 0U, i);
784	1064
785	1065	return aq_hw_err_from_flags(self);
786	1066	}
..	..	@@ -794,29 +1074,30 @@
794	1074	u32 count)
795	1075	{
796	1076	int err = 0;
	1077	+ struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
797	1078
798	1079	if (count > (HW_ATL_B0_MAC_MAX - HW_ATL_B0_MAC_MIN)) {
799	1080	err = -EBADRQC;
800	1081	goto err_exit;
801	1082	}
802		- for (self->aq_nic_cfg->mc_list_count = 0U;
803		- self->aq_nic_cfg->mc_list_count < count;
804		- ++self->aq_nic_cfg->mc_list_count) {
805		- u32 i = self->aq_nic_cfg->mc_list_count;
	1083	+ for (cfg->mc_list_count = 0U;
	1084	+ cfg->mc_list_count < count;
	1085	+ ++cfg->mc_list_count) {
	1086	+ u32 i = cfg->mc_list_count;
806	1087	u32 h = (ar_mac[i][0] << 8) \| (ar_mac[i][1]);
807	1088	u32 l = (ar_mac[i][2] << 24) \| (ar_mac[i][3] << 16) \|
808	1089	(ar_mac[i][4] << 8) \| ar_mac[i][5];
809	1090
810	1091	hw_atl_rpfl2_uc_flr_en_set(self, 0U, HW_ATL_B0_MAC_MIN + i);
811	1092
812		- hw_atl_rpfl2unicast_dest_addresslsw_set(self,
813		- l, HW_ATL_B0_MAC_MIN + i);
	1093	+ hw_atl_rpfl2unicast_dest_addresslsw_set(self, l,
	1094	+ HW_ATL_B0_MAC_MIN + i);
814	1095
815		- hw_atl_rpfl2unicast_dest_addressmsw_set(self,
816		- h, HW_ATL_B0_MAC_MIN + i);
	1096	+ hw_atl_rpfl2unicast_dest_addressmsw_set(self, h,
	1097	+ HW_ATL_B0_MAC_MIN + i);
817	1098
818	1099	hw_atl_rpfl2_uc_flr_en_set(self,
819		- (self->aq_nic_cfg->is_mc_list_enabled),
	1100	+ (cfg->is_mc_list_enabled),
820	1101	HW_ATL_B0_MAC_MIN + i);
821	1102	}
822	1103
..	..	@@ -917,34 +1198,467 @@
917	1198
918	1199	static int hw_atl_b0_hw_stop(struct aq_hw_s *self)
919	1200	{
	1201	+ int err;
	1202	+ u32 val;
	1203	+
920	1204	hw_atl_b0_hw_irq_disable(self, HW_ATL_B0_INT_MASK);
921	1205
922	1206	/* Invalidate Descriptor Cache to prevent writing to the cached
923	1207	* descriptors and to the data pointer of those descriptors
924	1208	*/
925		- hw_atl_rdm_rx_dma_desc_cache_init_set(self, 1);
	1209	+ hw_atl_rdm_rx_dma_desc_cache_init_tgl(self);
926	1210
927		- return aq_hw_err_from_flags(self);
	1211	+ err = aq_hw_err_from_flags(self);
	1212	+
	1213	+ if (err)
	1214	+ goto err_exit;
	1215	+
	1216	+ readx_poll_timeout_atomic(hw_atl_rdm_rx_dma_desc_cache_init_done_get,
	1217	+ self, val, val == 1, 1000U, 10000U);
	1218	+
	1219	+err_exit:
	1220	+ return err;
928	1221	}
929	1222
930		-static int hw_atl_b0_hw_ring_tx_stop(struct aq_hw_s *self,
931		- struct aq_ring_s *ring)
	1223	+int hw_atl_b0_hw_ring_tx_stop(struct aq_hw_s self, struct aq_ring_s ring)
932	1224	{
933	1225	hw_atl_tdm_tx_desc_en_set(self, 0U, ring->idx);
	1226	+
934	1227	return aq_hw_err_from_flags(self);
935	1228	}
936	1229
937		-static int hw_atl_b0_hw_ring_rx_stop(struct aq_hw_s *self,
938		- struct aq_ring_s *ring)
	1230	+int hw_atl_b0_hw_ring_rx_stop(struct aq_hw_s self, struct aq_ring_s ring)
939	1231	{
940	1232	hw_atl_rdm_rx_desc_en_set(self, 0U, ring->idx);
	1233	+
941	1234	return aq_hw_err_from_flags(self);
	1235	+}
	1236	+
	1237	+#define get_ptp_ts_val_u64(self, indx) \
	1238	+ ((u64)(hw_atl_pcs_ptp_clock_get(self, indx) & 0xffff))
	1239	+
	1240	+static void hw_atl_b0_get_ptp_ts(struct aq_hw_s self, u64 stamp)
	1241	+{
	1242	+ u64 ns;
	1243	+
	1244	+ hw_atl_pcs_ptp_clock_read_enable(self, 1);
	1245	+ hw_atl_pcs_ptp_clock_read_enable(self, 0);
	1246	+ ns = (get_ptp_ts_val_u64(self, 0) +
	1247	+ (get_ptp_ts_val_u64(self, 1) << 16)) * NSEC_PER_SEC +
	1248	+ (get_ptp_ts_val_u64(self, 3) +
	1249	+ (get_ptp_ts_val_u64(self, 4) << 16));
	1250	+
	1251	+ *stamp = ns + self->ptp_clk_offset;
	1252	+}
	1253	+
	1254	+static void hw_atl_b0_adj_params_get(u64 freq, s64 adj, u32 ns, u32 fns)
	1255	+{
	1256	+ /* For accuracy, the digit is extended */
	1257	+ s64 base_ns = ((adj + NSEC_PER_SEC) * NSEC_PER_SEC);
	1258	+ u64 nsi_frac = 0;
	1259	+ u64 nsi;
	1260	+
	1261	+ base_ns = div64_s64(base_ns, freq);
	1262	+ nsi = div64_u64(base_ns, NSEC_PER_SEC);
	1263	+
	1264	+ if (base_ns != nsi * NSEC_PER_SEC) {
	1265	+ s64 divisor = div64_s64((s64)NSEC_PER_SEC * NSEC_PER_SEC,
	1266	+ base_ns - nsi * NSEC_PER_SEC);
	1267	+ nsi_frac = div64_s64(AQ_FRAC_PER_NS * NSEC_PER_SEC, divisor);
	1268	+ }
	1269	+
	1270	+ *ns = (u32)nsi;
	1271	+ *fns = (u32)nsi_frac;
	1272	+}
	1273	+
	1274	+static void
	1275	+hw_atl_b0_mac_adj_param_calc(struct hw_fw_request_ptp_adj_freq *ptp_adj_freq,
	1276	+ u64 phyfreq, u64 macfreq)
	1277	+{
	1278	+ s64 adj_fns_val;
	1279	+ s64 fns_in_sec_phy = phyfreq * (ptp_adj_freq->fns_phy +
	1280	+ AQ_FRAC_PER_NS * ptp_adj_freq->ns_phy);
	1281	+ s64 fns_in_sec_mac = macfreq * (ptp_adj_freq->fns_mac +
	1282	+ AQ_FRAC_PER_NS * ptp_adj_freq->ns_mac);
	1283	+ s64 fault_in_sec_phy = AQ_FRAC_PER_NS * NSEC_PER_SEC - fns_in_sec_phy;
	1284	+ s64 fault_in_sec_mac = AQ_FRAC_PER_NS * NSEC_PER_SEC - fns_in_sec_mac;
	1285	+ /* MAC MCP counter freq is macfreq / 4 */
	1286	+ s64 diff_in_mcp_overflow = (fault_in_sec_mac - fault_in_sec_phy) *
	1287	+ 4 * AQ_FRAC_PER_NS;
	1288	+
	1289	+ diff_in_mcp_overflow = div64_s64(diff_in_mcp_overflow,
	1290	+ AQ_HW_MAC_COUNTER_HZ);
	1291	+ adj_fns_val = (ptp_adj_freq->fns_mac + AQ_FRAC_PER_NS *
	1292	+ ptp_adj_freq->ns_mac) + diff_in_mcp_overflow;
	1293	+
	1294	+ ptp_adj_freq->mac_ns_adj = div64_s64(adj_fns_val, AQ_FRAC_PER_NS);
	1295	+ ptp_adj_freq->mac_fns_adj = adj_fns_val - ptp_adj_freq->mac_ns_adj *
	1296	+ AQ_FRAC_PER_NS;
	1297	+}
	1298	+
	1299	+static int hw_atl_b0_adj_sys_clock(struct aq_hw_s *self, s64 delta)
	1300	+{
	1301	+ self->ptp_clk_offset += delta;
	1302	+
	1303	+ self->aq_fw_ops->adjust_ptp(self, self->ptp_clk_offset);
	1304	+
	1305	+ return 0;
	1306	+}
	1307	+
	1308	+static int hw_atl_b0_set_sys_clock(struct aq_hw_s *self, u64 time, u64 ts)
	1309	+{
	1310	+ s64 delta = time - (self->ptp_clk_offset + ts);
	1311	+
	1312	+ return hw_atl_b0_adj_sys_clock(self, delta);
	1313	+}
	1314	+
	1315	+static int hw_atl_b0_ts_to_sys_clock(struct aq_hw_s self, u64 ts, u64 time)
	1316	+{
	1317	+ *time = self->ptp_clk_offset + ts;
	1318	+ return 0;
	1319	+}
	1320	+
	1321	+static int hw_atl_b0_adj_clock_freq(struct aq_hw_s *self, s32 ppb)
	1322	+{
	1323	+ struct hw_fw_request_iface fwreq;
	1324	+ size_t size;
	1325	+
	1326	+ memset(&fwreq, 0, sizeof(fwreq));
	1327	+
	1328	+ fwreq.msg_id = HW_AQ_FW_REQUEST_PTP_ADJ_FREQ;
	1329	+ hw_atl_b0_adj_params_get(AQ_HW_MAC_COUNTER_HZ, ppb,
	1330	+ &fwreq.ptp_adj_freq.ns_mac,
	1331	+ &fwreq.ptp_adj_freq.fns_mac);
	1332	+ hw_atl_b0_adj_params_get(AQ_HW_PHY_COUNTER_HZ, ppb,
	1333	+ &fwreq.ptp_adj_freq.ns_phy,
	1334	+ &fwreq.ptp_adj_freq.fns_phy);
	1335	+ hw_atl_b0_mac_adj_param_calc(&fwreq.ptp_adj_freq,
	1336	+ AQ_HW_PHY_COUNTER_HZ,
	1337	+ AQ_HW_MAC_COUNTER_HZ);
	1338	+
	1339	+ size = sizeof(fwreq.msg_id) + sizeof(fwreq.ptp_adj_freq);
	1340	+ return self->aq_fw_ops->send_fw_request(self, &fwreq, size);
	1341	+}
	1342	+
	1343	+static int hw_atl_b0_gpio_pulse(struct aq_hw_s *self, u32 index,
	1344	+ u64 start, u32 period)
	1345	+{
	1346	+ struct hw_fw_request_iface fwreq;
	1347	+ size_t size;
	1348	+
	1349	+ memset(&fwreq, 0, sizeof(fwreq));
	1350	+
	1351	+ fwreq.msg_id = HW_AQ_FW_REQUEST_PTP_GPIO_CTRL;
	1352	+ fwreq.ptp_gpio_ctrl.index = index;
	1353	+ fwreq.ptp_gpio_ctrl.period = period;
	1354	+ /* Apply time offset */
	1355	+ fwreq.ptp_gpio_ctrl.start = start;
	1356	+
	1357	+ size = sizeof(fwreq.msg_id) + sizeof(fwreq.ptp_gpio_ctrl);
	1358	+ return self->aq_fw_ops->send_fw_request(self, &fwreq, size);
	1359	+}
	1360	+
	1361	+static int hw_atl_b0_extts_gpio_enable(struct aq_hw_s *self, u32 index,
	1362	+ u32 enable)
	1363	+{
	1364	+ /* Enable/disable Sync1588 GPIO Timestamping */
	1365	+ aq_phy_write_reg(self, MDIO_MMD_PCS, 0xc611, enable ? 0x71 : 0);
	1366	+
	1367	+ return 0;
	1368	+}
	1369	+
	1370	+static int hw_atl_b0_get_sync_ts(struct aq_hw_s self, u64 ts)
	1371	+{
	1372	+ u64 sec_l;
	1373	+ u64 sec_h;
	1374	+ u64 nsec_l;
	1375	+ u64 nsec_h;
	1376	+
	1377	+ if (!ts)
	1378	+ return -1;
	1379	+
	1380	+ /* PTP external GPIO clock seconds count 15:0 */
	1381	+ sec_l = aq_phy_read_reg(self, MDIO_MMD_PCS, 0xc914);
	1382	+ /* PTP external GPIO clock seconds count 31:16 */
	1383	+ sec_h = aq_phy_read_reg(self, MDIO_MMD_PCS, 0xc915);
	1384	+ /* PTP external GPIO clock nanoseconds count 15:0 */
	1385	+ nsec_l = aq_phy_read_reg(self, MDIO_MMD_PCS, 0xc916);
	1386	+ /* PTP external GPIO clock nanoseconds count 31:16 */
	1387	+ nsec_h = aq_phy_read_reg(self, MDIO_MMD_PCS, 0xc917);
	1388	+
	1389	+ ts = (nsec_h << 16) + nsec_l + ((sec_h << 16) + sec_l) NSEC_PER_SEC;
	1390	+
	1391	+ return 0;
	1392	+}
	1393	+
	1394	+static u16 hw_atl_b0_rx_extract_ts(struct aq_hw_s self, u8 p,
	1395	+ unsigned int len, u64 *timestamp)
	1396	+{
	1397	+ unsigned int offset = 14;
	1398	+ struct ethhdr *eth;
	1399	+ __be64 sec;
	1400	+ __be32 ns;
	1401	+ u8 *ptr;
	1402	+
	1403	+ if (len <= offset \|\| !timestamp)
	1404	+ return 0;
	1405	+
	1406	+ /* The TIMESTAMP in the end of package has following format:
	1407	+ * (big-endian)
	1408	+ * struct {
	1409	+ * uint64_t sec;
	1410	+ * uint32_t ns;
	1411	+ * uint16_t stream_id;
	1412	+ * };
	1413	+ */
	1414	+ ptr = p + (len - offset);
	1415	+ memcpy(&sec, ptr, sizeof(sec));
	1416	+ ptr += sizeof(sec);
	1417	+ memcpy(&ns, ptr, sizeof(ns));
	1418	+
	1419	+ timestamp = (be64_to_cpu(sec) & 0xffffffffffffllu) NSEC_PER_SEC +
	1420	+ be32_to_cpu(ns) + self->ptp_clk_offset;
	1421	+
	1422	+ eth = (struct ethhdr *)p;
	1423	+
	1424	+ return (eth->h_proto == htons(ETH_P_1588)) ? 12 : 14;
	1425	+}
	1426	+
	1427	+static int hw_atl_b0_extract_hwts(struct aq_hw_s self, u8 p, unsigned int len,
	1428	+ u64 *timestamp)
	1429	+{
	1430	+ struct hw_atl_rxd_hwts_wb_s hwts_wb = (struct hw_atl_rxd_hwts_wb_s )p;
	1431	+ u64 tmp, sec, ns;
	1432	+
	1433	+ sec = 0;
	1434	+ tmp = (hwts_wb->sec_lw0 >> 2) & 0x3ff;
	1435	+ sec += tmp;
	1436	+ tmp = (u64)((hwts_wb->sec_lw1 >> 16) & 0xffff) << 10;
	1437	+ sec += tmp;
	1438	+ tmp = (u64)(hwts_wb->sec_hw & 0xfff) << 26;
	1439	+ sec += tmp;
	1440	+ tmp = (u64)((hwts_wb->sec_hw >> 22) & 0x3ff) << 38;
	1441	+ sec += tmp;
	1442	+ ns = sec * NSEC_PER_SEC + hwts_wb->ns;
	1443	+ if (timestamp)
	1444	+ *timestamp = ns + self->ptp_clk_offset;
	1445	+ return 0;
	1446	+}
	1447	+
	1448	+static int hw_atl_b0_hw_fl3l4_clear(struct aq_hw_s *self,
	1449	+ struct aq_rx_filter_l3l4 *data)
	1450	+{
	1451	+ u8 location = data->location;
	1452	+
	1453	+ if (!data->is_ipv6) {
	1454	+ hw_atl_rpfl3l4_cmd_clear(self, location);
	1455	+ hw_atl_rpf_l4_spd_set(self, 0U, location);
	1456	+ hw_atl_rpf_l4_dpd_set(self, 0U, location);
	1457	+ hw_atl_rpfl3l4_ipv4_src_addr_clear(self, location);
	1458	+ hw_atl_rpfl3l4_ipv4_dest_addr_clear(self, location);
	1459	+ } else {
	1460	+ int i;
	1461	+
	1462	+ for (i = 0; i < HW_ATL_RX_CNT_REG_ADDR_IPV6; ++i) {
	1463	+ hw_atl_rpfl3l4_cmd_clear(self, location + i);
	1464	+ hw_atl_rpf_l4_spd_set(self, 0U, location + i);
	1465	+ hw_atl_rpf_l4_dpd_set(self, 0U, location + i);
	1466	+ }
	1467	+ hw_atl_rpfl3l4_ipv6_src_addr_clear(self, location);
	1468	+ hw_atl_rpfl3l4_ipv6_dest_addr_clear(self, location);
	1469	+ }
	1470	+
	1471	+ return aq_hw_err_from_flags(self);
	1472	+}
	1473	+
	1474	+static int hw_atl_b0_hw_fl3l4_set(struct aq_hw_s *self,
	1475	+ struct aq_rx_filter_l3l4 *data)
	1476	+{
	1477	+ u8 location = data->location;
	1478	+
	1479	+ hw_atl_b0_hw_fl3l4_clear(self, data);
	1480	+
	1481	+ if (data->cmd & (HW_ATL_RX_ENABLE_CMP_DEST_ADDR_L3 \|
	1482	+ HW_ATL_RX_ENABLE_CMP_SRC_ADDR_L3)) {
	1483	+ if (!data->is_ipv6) {
	1484	+ hw_atl_rpfl3l4_ipv4_dest_addr_set(self,
	1485	+ location,
	1486	+ data->ip_dst[0]);
	1487	+ hw_atl_rpfl3l4_ipv4_src_addr_set(self,
	1488	+ location,
	1489	+ data->ip_src[0]);
	1490	+ } else {
	1491	+ hw_atl_rpfl3l4_ipv6_dest_addr_set(self,
	1492	+ location,
	1493	+ data->ip_dst);
	1494	+ hw_atl_rpfl3l4_ipv6_src_addr_set(self,
	1495	+ location,
	1496	+ data->ip_src);
	1497	+ }
	1498	+ }
	1499	+
	1500	+ if (data->cmd & (HW_ATL_RX_ENABLE_CMP_DEST_PORT_L4 \|
	1501	+ HW_ATL_RX_ENABLE_CMP_SRC_PORT_L4)) {
	1502	+ hw_atl_rpf_l4_dpd_set(self, data->p_dst, location);
	1503	+ hw_atl_rpf_l4_spd_set(self, data->p_src, location);
	1504	+ }
	1505	+
	1506	+ hw_atl_rpfl3l4_cmd_set(self, location, data->cmd);
	1507	+
	1508	+ return aq_hw_err_from_flags(self);
	1509	+}
	1510	+
	1511	+static int hw_atl_b0_hw_fl2_set(struct aq_hw_s *self,
	1512	+ struct aq_rx_filter_l2 *data)
	1513	+{
	1514	+ hw_atl_rpf_etht_flr_en_set(self, 1U, data->location);
	1515	+ hw_atl_rpf_etht_flr_set(self, data->ethertype, data->location);
	1516	+ hw_atl_rpf_etht_user_priority_en_set(self,
	1517	+ !!data->user_priority_en,
	1518	+ data->location);
	1519	+ if (data->user_priority_en)
	1520	+ hw_atl_rpf_etht_user_priority_set(self,
	1521	+ data->user_priority,
	1522	+ data->location);
	1523	+
	1524	+ if (data->queue < 0) {
	1525	+ hw_atl_rpf_etht_flr_act_set(self, 0U, data->location);
	1526	+ hw_atl_rpf_etht_rx_queue_en_set(self, 0U, data->location);
	1527	+ } else {
	1528	+ hw_atl_rpf_etht_flr_act_set(self, 1U, data->location);
	1529	+ hw_atl_rpf_etht_rx_queue_en_set(self, 1U, data->location);
	1530	+ hw_atl_rpf_etht_rx_queue_set(self, data->queue, data->location);
	1531	+ }
	1532	+
	1533	+ return aq_hw_err_from_flags(self);
	1534	+}
	1535	+
	1536	+static int hw_atl_b0_hw_fl2_clear(struct aq_hw_s *self,
	1537	+ struct aq_rx_filter_l2 *data)
	1538	+{
	1539	+ hw_atl_rpf_etht_flr_en_set(self, 0U, data->location);
	1540	+ hw_atl_rpf_etht_flr_set(self, 0U, data->location);
	1541	+ hw_atl_rpf_etht_user_priority_en_set(self, 0U, data->location);
	1542	+
	1543	+ return aq_hw_err_from_flags(self);
	1544	+}
	1545	+
	1546	+/*
	1547	+ * @brief Set VLAN filter table
	1548	+ * @details Configure VLAN filter table to accept (and assign the queue) traffic
	1549	+ * for the particular vlan ids.
	1550	+ * Note: use this function under vlan promisc mode not to lost the traffic
	1551	+ *
	1552	+ * @param aq_hw_s
	1553	+ * @param aq_rx_filter_vlan VLAN filter configuration
	1554	+ * @return 0 - OK, <0 - error
	1555	+ */
	1556	+static int hw_atl_b0_hw_vlan_set(struct aq_hw_s *self,
	1557	+ struct aq_rx_filter_vlan *aq_vlans)
	1558	+{
	1559	+ int i;
	1560	+
	1561	+ for (i = 0; i < AQ_VLAN_MAX_FILTERS; i++) {
	1562	+ hw_atl_rpf_vlan_flr_en_set(self, 0U, i);
	1563	+ hw_atl_rpf_vlan_rxq_en_flr_set(self, 0U, i);
	1564	+ if (aq_vlans[i].enable) {
	1565	+ hw_atl_rpf_vlan_id_flr_set(self,
	1566	+ aq_vlans[i].vlan_id,
	1567	+ i);
	1568	+ hw_atl_rpf_vlan_flr_act_set(self, 1U, i);
	1569	+ hw_atl_rpf_vlan_flr_en_set(self, 1U, i);
	1570	+ if (aq_vlans[i].queue != 0xFF) {
	1571	+ hw_atl_rpf_vlan_rxq_flr_set(self,
	1572	+ aq_vlans[i].queue,
	1573	+ i);
	1574	+ hw_atl_rpf_vlan_rxq_en_flr_set(self, 1U, i);
	1575	+ }
	1576	+ }
	1577	+ }
	1578	+
	1579	+ return aq_hw_err_from_flags(self);
	1580	+}
	1581	+
	1582	+static int hw_atl_b0_hw_vlan_ctrl(struct aq_hw_s *self, bool enable)
	1583	+{
	1584	+ /* set promisc in case of disabing the vland filter */
	1585	+ hw_atl_rpf_vlan_prom_mode_en_set(self, !enable);
	1586	+
	1587	+ return aq_hw_err_from_flags(self);
	1588	+}
	1589	+
	1590	+int hw_atl_b0_set_loopback(struct aq_hw_s *self, u32 mode, bool enable)
	1591	+{
	1592	+ switch (mode) {
	1593	+ case AQ_HW_LOOPBACK_DMA_SYS:
	1594	+ hw_atl_tpb_tx_dma_sys_lbk_en_set(self, enable);
	1595	+ hw_atl_rpb_dma_sys_lbk_set(self, enable);
	1596	+ break;
	1597	+ case AQ_HW_LOOPBACK_PKT_SYS:
	1598	+ hw_atl_tpo_tx_pkt_sys_lbk_en_set(self, enable);
	1599	+ hw_atl_rpf_tpo_to_rpf_sys_lbk_set(self, enable);
	1600	+ break;
	1601	+ case AQ_HW_LOOPBACK_DMA_NET:
	1602	+ hw_atl_rpf_vlan_prom_mode_en_set(self, enable);
	1603	+ hw_atl_rpfl2promiscuous_mode_en_set(self, enable);
	1604	+ hw_atl_tpb_tx_tx_clk_gate_en_set(self, !enable);
	1605	+ hw_atl_tpb_tx_dma_net_lbk_en_set(self, enable);
	1606	+ hw_atl_rpb_dma_net_lbk_set(self, enable);
	1607	+ break;
	1608	+ default:
	1609	+ return -EINVAL;
	1610	+ }
	1611	+
	1612	+ return 0;
	1613	+}
	1614	+
	1615	+static u32 hw_atl_b0_ts_ready_and_latch_high_get(struct aq_hw_s *self)
	1616	+{
	1617	+ if (hw_atl_ts_ready_get(self) && hw_atl_ts_ready_latch_high_get(self))
	1618	+ return 1;
	1619	+
	1620	+ return 0;
	1621	+}
	1622	+
	1623	+static int hw_atl_b0_get_mac_temp(struct aq_hw_s self, u32 temp)
	1624	+{
	1625	+ bool ts_disabled;
	1626	+ int err;
	1627	+ u32 val;
	1628	+ u32 ts;
	1629	+
	1630	+ ts_disabled = (hw_atl_ts_power_down_get(self) == 1U);
	1631	+
	1632	+ if (ts_disabled) {
	1633	+ // Set AFE Temperature Sensor to on (off by default)
	1634	+ hw_atl_ts_power_down_set(self, 0U);
	1635	+
	1636	+ // Reset internal capacitors, biasing, and counters
	1637	+ hw_atl_ts_reset_set(self, 1);
	1638	+ hw_atl_ts_reset_set(self, 0);
	1639	+ }
	1640	+
	1641	+ err = readx_poll_timeout(hw_atl_b0_ts_ready_and_latch_high_get, self,
	1642	+ val, val == 1, 10000U, 500000U);
	1643	+ if (err)
	1644	+ return err;
	1645	+
	1646	+ ts = hw_atl_ts_data_get(self);
	1647	+ temp = ts ts * 16 / 100000 + 60 * ts - 83410;
	1648	+
	1649	+ if (ts_disabled) {
	1650	+ // Set AFE Temperature Sensor back to off
	1651	+ hw_atl_ts_power_down_set(self, 1U);
	1652	+ }
	1653	+
	1654	+ return 0;
942	1655	}
943	1656
944	1657	const struct aq_hw_ops hw_atl_ops_b0 = {
	1658	+ .hw_soft_reset = hw_atl_utils_soft_reset,
	1659	+ .hw_prepare = hw_atl_utils_initfw,
945	1660	.hw_set_mac_address = hw_atl_b0_hw_mac_addr_set,
946	1661	.hw_init = hw_atl_b0_hw_init,
947		- .hw_set_power = hw_atl_utils_hw_set_power,
948	1662	.hw_reset = hw_atl_b0_hw_reset,
949	1663	.hw_start = hw_atl_b0_hw_start,
950	1664	.hw_ring_tx_start = hw_atl_b0_hw_ring_tx_start,
..	..	@@ -966,11 +1680,36 @@
966	1680	.hw_ring_rx_init = hw_atl_b0_hw_ring_rx_init,
967	1681	.hw_ring_tx_init = hw_atl_b0_hw_ring_tx_init,
968	1682	.hw_packet_filter_set = hw_atl_b0_hw_packet_filter_set,
	1683	+ .hw_filter_l2_set = hw_atl_b0_hw_fl2_set,
	1684	+ .hw_filter_l2_clear = hw_atl_b0_hw_fl2_clear,
	1685	+ .hw_filter_l3l4_set = hw_atl_b0_hw_fl3l4_set,
	1686	+ .hw_filter_vlan_set = hw_atl_b0_hw_vlan_set,
	1687	+ .hw_filter_vlan_ctrl = hw_atl_b0_hw_vlan_ctrl,
969	1688	.hw_multicast_list_set = hw_atl_b0_hw_multicast_list_set,
970	1689	.hw_interrupt_moderation_set = hw_atl_b0_hw_interrupt_moderation_set,
971	1690	.hw_rss_set = hw_atl_b0_hw_rss_set,
972	1691	.hw_rss_hash_set = hw_atl_b0_hw_rss_hash_set,
	1692	+ .hw_tc_rate_limit_set = hw_atl_b0_hw_init_tx_tc_rate_limit,
973	1693	.hw_get_regs = hw_atl_utils_hw_get_regs,
974	1694	.hw_get_hw_stats = hw_atl_utils_get_hw_stats,
975	1695	.hw_get_fw_version = hw_atl_utils_get_fw_version,
	1696	+
	1697	+ .hw_ring_hwts_rx_fill = hw_atl_b0_hw_ring_hwts_rx_fill,
	1698	+ .hw_ring_hwts_rx_receive = hw_atl_b0_hw_ring_hwts_rx_receive,
	1699	+
	1700	+ .hw_get_ptp_ts = hw_atl_b0_get_ptp_ts,
	1701	+ .hw_adj_sys_clock = hw_atl_b0_adj_sys_clock,
	1702	+ .hw_set_sys_clock = hw_atl_b0_set_sys_clock,
	1703	+ .hw_ts_to_sys_clock = hw_atl_b0_ts_to_sys_clock,
	1704	+ .hw_adj_clock_freq = hw_atl_b0_adj_clock_freq,
	1705	+ .hw_gpio_pulse = hw_atl_b0_gpio_pulse,
	1706	+ .hw_extts_gpio_enable = hw_atl_b0_extts_gpio_enable,
	1707	+ .hw_get_sync_ts = hw_atl_b0_get_sync_ts,
	1708	+ .rx_extract_ts = hw_atl_b0_rx_extract_ts,
	1709	+ .extract_hwts = hw_atl_b0_extract_hwts,
	1710	+ .hw_set_offload = hw_atl_b0_hw_offload_set,
	1711	+ .hw_set_loopback = hw_atl_b0_set_loopback,
	1712	+ .hw_set_fc = hw_atl_b0_set_fc,
	1713	+
	1714	+ .hw_get_mac_temp = hw_atl_b0_get_mac_temp,
976	1715	};