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2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390 
 kernel/drivers/mtd/nand/raw/nand_hynix.c
....@@ -1,23 +1,15 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * Copyright (C) 2017 Free Electrons
34  * Copyright (C) 2017 NextThing Co
45  *
56  * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
6
- *
7
- * This program is free software; you can redistribute it and/or modify
8
- * it under the terms of the GNU General Public License as published by
9
- * the Free Software Foundation; either version 2 of the License, or
10
- * (at your option) any later version.
11
- *
12
- * This program is distributed in the hope that it will be useful,
13
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
14
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
- * GNU General Public License for more details.
167  */
178 
18
-#include <linux/mtd/rawnand.h>
199 #include <linux/sizes.h>
2010 #include <linux/slab.h>
11
+
12
+#include "internals.h"
2113 
2214 #define NAND_HYNIX_CMD_SET_PARAMS	0x36
2315 #define NAND_HYNIX_CMD_APPLY_PARAMS	0x16
....@@ -34,7 +26,7 @@
3426 struct hynix_read_retry {
3527 	int nregs;
3628 	const u8 *regs;
37
-	u8 values[0];
29
+	u8 values[];
3830 };
3931 
4032 /**
....@@ -79,46 +71,42 @@
7971 
8072 static int hynix_nand_cmd_op(struct nand_chip *chip, u8 cmd)
8173 {
82
-	struct mtd_info *mtd = nand_to_mtd(chip);
83
-
84
-	if (chip->exec_op) {
74
+	if (nand_has_exec_op(chip)) {
8575 		struct nand_op_instr instrs[] = {
8676 			NAND_OP_CMD(cmd, 0),
8777 		};
88
-		struct nand_operation op = NAND_OPERATION(instrs);
78
+		struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
8979 
9080 		return nand_exec_op(chip, &op);
9181 	}
9282 
93
-	chip->cmdfunc(mtd, cmd, -1, -1);
83
+	chip->legacy.cmdfunc(chip, cmd, -1, -1);
9484 
9585 	return 0;
9686 }
9787 
9888 static int hynix_nand_reg_write_op(struct nand_chip *chip, u8 addr, u8 val)
9989 {
100
-	struct mtd_info *mtd = nand_to_mtd(chip);
10190 	u16 column = ((u16)addr << 8) | addr;
10291 
103
-	if (chip->exec_op) {
92
+	if (nand_has_exec_op(chip)) {
10493 		struct nand_op_instr instrs[] = {
10594 			NAND_OP_ADDR(1, &addr, 0),
10695 			NAND_OP_8BIT_DATA_OUT(1, &val, 0),
10796 		};
108
-		struct nand_operation op = NAND_OPERATION(instrs);
97
+		struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
10998 
11099 		return nand_exec_op(chip, &op);
111100 	}
112101 
113
-	chip->cmdfunc(mtd, NAND_CMD_NONE, column, -1);
114
-	chip->write_byte(mtd, val);
102
+	chip->legacy.cmdfunc(chip, NAND_CMD_NONE, column, -1);
103
+	chip->legacy.write_byte(chip, val);
115104 
116105 	return 0;
117106 }
118107 
119
-static int hynix_nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
108
+static int hynix_nand_setup_read_retry(struct nand_chip *chip, int retry_mode)
120109 {
121
-	struct nand_chip *chip = mtd_to_nand(mtd);
122110 	struct hynix_nand *hynix = nand_get_manufacturer_data(chip);
123111 	const u8 *values;
124112 	int i, ret;
....@@ -349,7 +337,7 @@
349337 	rr->nregs = nregs;
350338 	rr->regs = hynix_1xnm_mlc_read_retry_regs;
351339 	hynix->read_retry = rr;
352
-	chip->setup_read_retry = hynix_nand_setup_read_retry;
340
+	chip->ops.setup_read_retry = hynix_nand_setup_read_retry;
353341 	chip->read_retries = nmodes;
354342 
355343 out:
....@@ -421,7 +409,10 @@
421409 				       bool valid_jedecid)
422410 {
423411 	struct mtd_info *mtd = nand_to_mtd(chip);
412
+	struct nand_memory_organization *memorg;
424413 	u8 oobsize;
414
+
415
+	memorg = nanddev_get_memorg(&chip->base);
425416 
426417 	oobsize = ((chip->id.data[3] >> 2) & 0x3) |
427418 		  ((chip->id.data[3] >> 4) & 0x4);
....@@ -429,16 +420,16 @@
429420 	if (valid_jedecid) {
430421 		switch (oobsize) {
431422 		case 0:
432
-			mtd->oobsize = 2048;
423
+			memorg->oobsize = 2048;
433424 			break;
434425 		case 1:
435
-			mtd->oobsize = 1664;
426
+			memorg->oobsize = 1664;
436427 			break;
437428 		case 2:
438
-			mtd->oobsize = 1024;
429
+			memorg->oobsize = 1024;
439430 			break;
440431 		case 3:
441
-			mtd->oobsize = 640;
432
+			memorg->oobsize = 640;
442433 			break;
443434 		default:
444435 			/*
....@@ -453,25 +444,25 @@
453444 	} else {
454445 		switch (oobsize) {
455446 		case 0:
456
-			mtd->oobsize = 128;
447
+			memorg->oobsize = 128;
457448 			break;
458449 		case 1:
459
-			mtd->oobsize = 224;
450
+			memorg->oobsize = 224;
460451 			break;
461452 		case 2:
462
-			mtd->oobsize = 448;
453
+			memorg->oobsize = 448;
463454 			break;
464455 		case 3:
465
-			mtd->oobsize = 64;
456
+			memorg->oobsize = 64;
466457 			break;
467458 		case 4:
468
-			mtd->oobsize = 32;
459
+			memorg->oobsize = 32;
469460 			break;
470461 		case 5:
471
-			mtd->oobsize = 16;
462
+			memorg->oobsize = 16;
472463 			break;
473464 		case 6:
474
-			mtd->oobsize = 640;
465
+			memorg->oobsize = 640;
475466 			break;
476467 		default:
477468 			/*
....@@ -495,41 +486,45 @@
495486 		 * the actual OOB size for this chip is: 640 * 16k / 8k).
496487 		 */
497488 		if (chip->id.data[1] == 0xde)
498
-			mtd->oobsize *= mtd->writesize / SZ_8K;
489
+			memorg->oobsize *= memorg->pagesize / SZ_8K;
499490 	}
491
+
492
+	mtd->oobsize = memorg->oobsize;
500493 }
501494 
502495 static void hynix_nand_extract_ecc_requirements(struct nand_chip *chip,
503496 						bool valid_jedecid)
504497 {
498
+	struct nand_device *base = &chip->base;
499
+	struct nand_ecc_props requirements = {};
505500 	u8 ecc_level = (chip->id.data[4] >> 4) & 0x7;
506501 
507502 	if (valid_jedecid) {
508503 		/* Reference: H27UCG8T2E datasheet */
509
-		chip->ecc_step_ds = 1024;
504
+		requirements.step_size = 1024;
510505 
511506 		switch (ecc_level) {
512507 		case 0:
513
-			chip->ecc_step_ds = 0;
514
-			chip->ecc_strength_ds = 0;
508
+			requirements.step_size = 0;
509
+			requirements.strength = 0;
515510 			break;
516511 		case 1:
517
-			chip->ecc_strength_ds = 4;
512
+			requirements.strength = 4;
518513 			break;
519514 		case 2:
520
-			chip->ecc_strength_ds = 24;
515
+			requirements.strength = 24;
521516 			break;
522517 		case 3:
523
-			chip->ecc_strength_ds = 32;
518
+			requirements.strength = 32;
524519 			break;
525520 		case 4:
526
-			chip->ecc_strength_ds = 40;
521
+			requirements.strength = 40;
527522 			break;
528523 		case 5:
529
-			chip->ecc_strength_ds = 50;
524
+			requirements.strength = 50;
530525 			break;
531526 		case 6:
532
-			chip->ecc_strength_ds = 60;
527
+			requirements.strength = 60;
533528 			break;
534529 		default:
535530 			/*
....@@ -550,14 +545,14 @@
550545 		if (nand_tech < 3) {
551546 			/* > 26nm, reference: H27UBG8T2A datasheet */
552547 			if (ecc_level < 5) {
553
-				chip->ecc_step_ds = 512;
554
-				chip->ecc_strength_ds = 1 << ecc_level;
548
+				requirements.step_size = 512;
549
+				requirements.strength = 1 << ecc_level;
555550 			} else if (ecc_level < 7) {
556551 				if (ecc_level == 5)
557
-					chip->ecc_step_ds = 2048;
552
+					requirements.step_size = 2048;
558553 				else
559
-					chip->ecc_step_ds = 1024;
560
-				chip->ecc_strength_ds = 24;
554
+					requirements.step_size = 1024;
555
+				requirements.strength = 24;
561556 			} else {
562557 				/*
563558 				 * We should never reach this case, but if that
....@@ -570,18 +565,20 @@
570565 		} else {
571566 			/* <= 26nm, reference: H27UBG8T2B datasheet */
572567 			if (!ecc_level) {
573
-				chip->ecc_step_ds = 0;
574
-				chip->ecc_strength_ds = 0;
568
+				requirements.step_size = 0;
569
+				requirements.strength = 0;
575570 			} else if (ecc_level < 5) {
576
-				chip->ecc_step_ds = 512;
577
-				chip->ecc_strength_ds = 1 << (ecc_level - 1);
571
+				requirements.step_size = 512;
572
+				requirements.strength = 1 << (ecc_level - 1);
578573 			} else {
579
-				chip->ecc_step_ds = 1024;
580
-				chip->ecc_strength_ds = 24 +
574
+				requirements.step_size = 1024;
575
+				requirements.strength = 24 +
581576 							(8 * (ecc_level - 5));
582577 			}
583578 		}
584579 	}
580
+
581
+	nanddev_set_ecc_requirements(base, &requirements);
585582 }
586583 
587584 static void hynix_nand_extract_scrambling_requirements(struct nand_chip *chip,
....@@ -590,7 +587,7 @@
590587 	u8 nand_tech;
591588 
592589 	/* We need scrambling on all TLC NANDs*/
593
-	if (chip->bits_per_cell > 2)
590
+	if (nanddev_bits_per_cell(&chip->base) > 2)
594591 		chip->options |= NAND_NEED_SCRAMBLING;
595592 
596593 	/* And on MLC NANDs with sub-3xnm process */
....@@ -612,8 +609,11 @@
612609 static void hynix_nand_decode_id(struct nand_chip *chip)
613610 {
614611 	struct mtd_info *mtd = nand_to_mtd(chip);
612
+	struct nand_memory_organization *memorg;
615613 	bool valid_jedecid;
616614 	u8 tmp;
615
+
616
+	memorg = nanddev_get_memorg(&chip->base);
617617 
618618 	/*
619619 	 * Exclude all SLC NANDs from this advanced detection scheme.
....@@ -628,7 +628,8 @@
628628 	}
629629 
630630 	/* Extract pagesize */
631
-	mtd->writesize = 2048 << (chip->id.data[3] & 0x03);
631
+	memorg->pagesize = 2048 << (chip->id.data[3] & 0x03);
632
+	mtd->writesize = memorg->pagesize;
632633 
633634 	tmp = (chip->id.data[3] >> 4) & 0x3;
634635 	/*
....@@ -638,12 +639,19 @@
638639 	 * The only exception is when ID[3][4:5] == 3 and ID[3][7] == 0, in
639640 	 * this case the erasesize is set to 768KiB.
640641 	 */
641
-	if (chip->id.data[3] & 0x80)
642
+	if (chip->id.data[3] & 0x80) {
643
+		memorg->pages_per_eraseblock = (SZ_1M << tmp) /
644
+					       memorg->pagesize;
642645 		mtd->erasesize = SZ_1M << tmp;
643
-	else if (tmp == 3)
646
+	} else if (tmp == 3) {
647
+		memorg->pages_per_eraseblock = (SZ_512K + SZ_256K) /
648
+					       memorg->pagesize;
644649 		mtd->erasesize = SZ_512K + SZ_256K;
645
-	else
650
+	} else {
651
+		memorg->pages_per_eraseblock = (SZ_128K << tmp) /
652
+					       memorg->pagesize;
646653 		mtd->erasesize = SZ_128K << tmp;
654
+	}
647655 
648656 	/*
649657 	 * Modern Toggle DDR NANDs have a valid JEDECID even though they are
....@@ -669,15 +677,24 @@
669677 	nand_set_manufacturer_data(chip, NULL);
670678 }
671679 
680
+static int
681
+h27ucg8t2atrbc_choose_interface_config(struct nand_chip *chip,
682
+				       struct nand_interface_config *iface)
683
+{
684
+	onfi_fill_interface_config(chip, iface, NAND_SDR_IFACE, 4);
685
+
686
+	return nand_choose_best_sdr_timings(chip, iface, NULL);
687
+}
688
+
672689 static int hynix_nand_init(struct nand_chip *chip)
673690 {
674691 	struct hynix_nand *hynix;
675692 	int ret;
676693 
677694 	if (!nand_is_slc(chip))
678
-		chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
695
+		chip->options |= NAND_BBM_LASTPAGE;
679696 	else
680
-		chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
697
+		chip->options |= NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE;
681698 
682699 	hynix = kzalloc(sizeof(*hynix), GFP_KERNEL);
683700 	if (!hynix)
....@@ -685,6 +702,11 @@
685702 
686703 	nand_set_manufacturer_data(chip, hynix);
687704 
705
+	if (!strncmp("H27UCG8T2ATR-BC", chip->parameters.model,
706
+		     sizeof("H27UCG8T2ATR-BC") - 1))
707
+		chip->ops.choose_interface_config =
708
+			h27ucg8t2atrbc_choose_interface_config;
709
+
688710 	ret = hynix_nand_rr_init(chip);
689711 	if (ret)
690712 		hynix_nand_cleanup(chip);