change wifi driver to cypress

hc

2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390

 kernel/drivers/mtd/nand/raw/nand_base.c
..
..
@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
1
2
 /*
2
3
  *  Overview:
3
4
  *   This is the generic MTD driver for NAND flash devices. It should be
..
..
@@ -20,11 +21,6 @@
20
21
  *	Check, if mtd->ecctype should be set to MTD_ECC_HW
21
22
  *	if we have HW ECC support.
22
23
  *	BBT table is not serialized, has to be fixed
23
- *
24
- * This program is free software; you can redistribute it and/or modify
25
- * it under the terms of the GNU General Public License version 2 as
26
- * published by the Free Software Foundation.
27
- *
28
24
  */
29
25
 
30
26
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
..
..
@@ -36,10 +32,9 @@
36
32
 #include <linux/sched.h>
37
33
 #include <linux/slab.h>
38
34
 #include <linux/mm.h>
39
-#include <linux/nmi.h>
40
35
 #include <linux/types.h>
41
36
 #include <linux/mtd/mtd.h>
42
-#include <linux/mtd/rawnand.h>
37
+#include <linux/mtd/nand.h>
43
38
 #include <linux/mtd/nand_ecc.h>
44
39
 #include <linux/mtd/nand_bch.h>
45
40
 #include <linux/interrupt.h>
..
..
@@ -47,176 +42,62 @@
47
42
 #include <linux/io.h>
48
43
 #include <linux/mtd/partitions.h>
49
44
 #include <linux/of.h>
45
+#include <linux/gpio/consumer.h>
50
46
 
51
-static int nand_get_device(struct mtd_info *mtd, int new_state);
47
+#include "internals.h"
52
48
 
53
-static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
54
-			     struct mtd_oob_ops *ops);
55
-
56
-/* Define default oob placement schemes for large and small page devices */
57
-static int nand_ooblayout_ecc_sp(struct mtd_info *mtd, int section,
58
-				 struct mtd_oob_region *oobregion)
49
+static int nand_pairing_dist3_get_info(struct mtd_info *mtd, int page,
50
+				       struct mtd_pairing_info *info)
59
51
 {
60
-	struct nand_chip *chip = mtd_to_nand(mtd);
61
-	struct nand_ecc_ctrl *ecc = &chip->ecc;
52
+	int lastpage = (mtd->erasesize / mtd->writesize) - 1;
53
+	int dist = 3;
62
54
 
63
-	if (section > 1)
64
-		return -ERANGE;
55
+	if (page == lastpage)
56
+		dist = 2;
65
57
 
66
-	if (!section) {
67
-		oobregion->offset = 0;
68
-		if (mtd->oobsize == 16)
69
-			oobregion->length = 4;
70
-		else
71
-			oobregion->length = 3;
58
+	if (!page || (page & 1)) {
59
+		info->group = 0;
60
+		info->pair = (page + 1) / 2;
72
61
 	} else {
73
-		if (mtd->oobsize == 8)
74
-			return -ERANGE;
75
-
76
-		oobregion->offset = 6;
77
-		oobregion->length = ecc->total - 4;
62
+		info->group = 1;
63
+		info->pair = (page + 1 - dist) / 2;
78
64
 	}
79
65
 
80
66
 	return 0;
81
67
 }
82
68
 
83
-static int nand_ooblayout_free_sp(struct mtd_info *mtd, int section,
84
-				  struct mtd_oob_region *oobregion)
69
+static int nand_pairing_dist3_get_wunit(struct mtd_info *mtd,
70
+					const struct mtd_pairing_info *info)
85
71
 {
86
-	if (section > 1)
87
-		return -ERANGE;
72
+	int lastpair = ((mtd->erasesize / mtd->writesize) - 1) / 2;
73
+	int page = info->pair * 2;
74
+	int dist = 3;
88
75
 
89
-	if (mtd->oobsize == 16) {
90
-		if (section)
91
-			return -ERANGE;
76
+	if (!info->group && !info->pair)
77
+		return 0;
92
78
 
93
-		oobregion->length = 8;
94
-		oobregion->offset = 8;
95
-	} else {
96
-		oobregion->length = 2;
97
-		if (!section)
98
-			oobregion->offset = 3;
99
-		else
100
-			oobregion->offset = 6;
101
-	}
79
+	if (info->pair == lastpair && info->group)
80
+		dist = 2;
102
81
 
103
-	return 0;
104
-}
82
+	if (!info->group)
83
+		page--;
84
+	else if (info->pair)
85
+		page += dist - 1;
105
86
 
106
-const struct mtd_ooblayout_ops nand_ooblayout_sp_ops = {
107
-	.ecc = nand_ooblayout_ecc_sp,
108
-	.free = nand_ooblayout_free_sp,
109
-};
110
-EXPORT_SYMBOL_GPL(nand_ooblayout_sp_ops);
111
-
112
-static int nand_ooblayout_ecc_lp(struct mtd_info *mtd, int section,
113
-				 struct mtd_oob_region *oobregion)
114
-{
115
-	struct nand_chip *chip = mtd_to_nand(mtd);
116
-	struct nand_ecc_ctrl *ecc = &chip->ecc;
117
-
118
-	if (section || !ecc->total)
119
-		return -ERANGE;
120
-
121
-	oobregion->length = ecc->total;
122
-	oobregion->offset = mtd->oobsize - oobregion->length;
123
-
124
-	return 0;
125
-}
126
-
127
-static int nand_ooblayout_free_lp(struct mtd_info *mtd, int section,
128
-				  struct mtd_oob_region *oobregion)
129
-{
130
-	struct nand_chip *chip = mtd_to_nand(mtd);
131
-	struct nand_ecc_ctrl *ecc = &chip->ecc;
132
-
133
-	if (section)
134
-		return -ERANGE;
135
-
136
-	oobregion->length = mtd->oobsize - ecc->total - 2;
137
-	oobregion->offset = 2;
138
-
139
-	return 0;
140
-}
141
-
142
-const struct mtd_ooblayout_ops nand_ooblayout_lp_ops = {
143
-	.ecc = nand_ooblayout_ecc_lp,
144
-	.free = nand_ooblayout_free_lp,
145
-};
146
-EXPORT_SYMBOL_GPL(nand_ooblayout_lp_ops);
147
-
148
-/*
149
- * Support the old "large page" layout used for 1-bit Hamming ECC where ECC
150
- * are placed at a fixed offset.
151
- */
152
-static int nand_ooblayout_ecc_lp_hamming(struct mtd_info *mtd, int section,
153
-					 struct mtd_oob_region *oobregion)
154
-{
155
-	struct nand_chip *chip = mtd_to_nand(mtd);
156
-	struct nand_ecc_ctrl *ecc = &chip->ecc;
157
-
158
-	if (section)
159
-		return -ERANGE;
160
-
161
-	switch (mtd->oobsize) {
162
-	case 64:
163
-		oobregion->offset = 40;
164
-		break;
165
-	case 128:
166
-		oobregion->offset = 80;
167
-		break;
168
-	default:
87
+	if (page >= mtd->erasesize / mtd->writesize)
169
88
 		return -EINVAL;
170
-	}
171
89
 
172
-	oobregion->length = ecc->total;
173
-	if (oobregion->offset + oobregion->length > mtd->oobsize)
174
-		return -ERANGE;
175
-
176
-	return 0;
90
+	return page;
177
91
 }
178
92
 
179
-static int nand_ooblayout_free_lp_hamming(struct mtd_info *mtd, int section,
180
-					  struct mtd_oob_region *oobregion)
181
-{
182
-	struct nand_chip *chip = mtd_to_nand(mtd);
183
-	struct nand_ecc_ctrl *ecc = &chip->ecc;
184
-	int ecc_offset = 0;
185
-
186
-	if (section < 0 || section > 1)
187
-		return -ERANGE;
188
-
189
-	switch (mtd->oobsize) {
190
-	case 64:
191
-		ecc_offset = 40;
192
-		break;
193
-	case 128:
194
-		ecc_offset = 80;
195
-		break;
196
-	default:
197
-		return -EINVAL;
198
-	}
199
-
200
-	if (section == 0) {
201
-		oobregion->offset = 2;
202
-		oobregion->length = ecc_offset - 2;
203
-	} else {
204
-		oobregion->offset = ecc_offset + ecc->total;
205
-		oobregion->length = mtd->oobsize - oobregion->offset;
206
-	}
207
-
208
-	return 0;
209
-}
210
-
211
-static const struct mtd_ooblayout_ops nand_ooblayout_lp_hamming_ops = {
212
-	.ecc = nand_ooblayout_ecc_lp_hamming,
213
-	.free = nand_ooblayout_free_lp_hamming,
93
+const struct mtd_pairing_scheme dist3_pairing_scheme = {
94
+	.ngroups = 2,
95
+	.get_info = nand_pairing_dist3_get_info,
96
+	.get_wunit = nand_pairing_dist3_get_wunit,
214
97
 };
215
98
 
216
-static int check_offs_len(struct mtd_info *mtd,
217
-					loff_t ofs, uint64_t len)
99
+static int check_offs_len(struct nand_chip *chip, loff_t ofs, uint64_t len)
218
100
 {
219
-	struct nand_chip *chip = mtd_to_nand(mtd);
220
101
 	int ret = 0;
221
102
 
222
103
 	/* Start address must align on block boundary */
..
..
@@ -235,211 +116,150 @@
235
116
 }
236
117
 
237
118
 /**
119
+ * nand_extract_bits - Copy unaligned bits from one buffer to another one
120
+ * @dst: destination buffer
121
+ * @dst_off: bit offset at which the writing starts
122
+ * @src: source buffer
123
+ * @src_off: bit offset at which the reading starts
124
+ * @nbits: number of bits to copy from @src to @dst
125
+ *
126
+ * Copy bits from one memory region to another (overlap authorized).
127
+ */
128
+void nand_extract_bits(u8 *dst, unsigned int dst_off, const u8 *src,
129
+		       unsigned int src_off, unsigned int nbits)
130
+{
131
+	unsigned int tmp, n;
132
+
133
+	dst += dst_off / 8;
134
+	dst_off %= 8;
135
+	src += src_off / 8;
136
+	src_off %= 8;
137
+
138
+	while (nbits) {
139
+		n = min3(8 - dst_off, 8 - src_off, nbits);
140
+
141
+		tmp = (*src >> src_off) & GENMASK(n - 1, 0);
142
+		*dst &= ~GENMASK(n - 1 + dst_off, dst_off);
143
+		*dst |= tmp << dst_off;
144
+
145
+		dst_off += n;
146
+		if (dst_off >= 8) {
147
+			dst++;
148
+			dst_off -= 8;
149
+		}
150
+
151
+		src_off += n;
152
+		if (src_off >= 8) {
153
+			src++;
154
+			src_off -= 8;
155
+		}
156
+
157
+		nbits -= n;
158
+	}
159
+}
160
+EXPORT_SYMBOL_GPL(nand_extract_bits);
161
+
162
+/**
163
+ * nand_select_target() - Select a NAND target (A.K.A. die)
164
+ * @chip: NAND chip object
165
+ * @cs: the CS line to select. Note that this CS id is always from the chip
166
+ *	PoV, not the controller one
167
+ *
168
+ * Select a NAND target so that further operations executed on @chip go to the
169
+ * selected NAND target.
170
+ */
171
+void nand_select_target(struct nand_chip *chip, unsigned int cs)
172
+{
173
+	/*
174
+	 * cs should always lie between 0 and nanddev_ntargets(), when that's
175
+	 * not the case it's a bug and the caller should be fixed.
176
+	 */
177
+	if (WARN_ON(cs > nanddev_ntargets(&chip->base)))
178
+		return;
179
+
180
+	chip->cur_cs = cs;
181
+
182
+	if (chip->legacy.select_chip)
183
+		chip->legacy.select_chip(chip, cs);
184
+}
185
+EXPORT_SYMBOL_GPL(nand_select_target);
186
+
187
+/**
188
+ * nand_deselect_target() - Deselect the currently selected target
189
+ * @chip: NAND chip object
190
+ *
191
+ * Deselect the currently selected NAND target. The result of operations
192
+ * executed on @chip after the target has been deselected is undefined.
193
+ */
194
+void nand_deselect_target(struct nand_chip *chip)
195
+{
196
+	if (chip->legacy.select_chip)
197
+		chip->legacy.select_chip(chip, -1);
198
+
199
+	chip->cur_cs = -1;
200
+}
201
+EXPORT_SYMBOL_GPL(nand_deselect_target);
202
+
203
+/**
238
204
  * nand_release_device - [GENERIC] release chip
239
- * @mtd: MTD device structure
205
+ * @chip: NAND chip object
240
206
  *
241
207
  * Release chip lock and wake up anyone waiting on the device.
242
208
  */
243
-static void nand_release_device(struct mtd_info *mtd)
209
+static void nand_release_device(struct nand_chip *chip)
244
210
 {
245
-	struct nand_chip *chip = mtd_to_nand(mtd);
246
-
247
211
 	/* Release the controller and the chip */
248
-	spin_lock(&chip->controller->lock);
249
-	chip->controller->active = NULL;
250
-	chip->state = FL_READY;
251
-	wake_up(&chip->controller->wq);
252
-	spin_unlock(&chip->controller->lock);
212
+	mutex_unlock(&chip->controller->lock);
213
+	mutex_unlock(&chip->lock);
253
214
 }
254
215
 
255
216
 /**
256
- * nand_read_byte - [DEFAULT] read one byte from the chip
257
- * @mtd: MTD device structure
217
+ * nand_bbm_get_next_page - Get the next page for bad block markers
218
+ * @chip: NAND chip object
219
+ * @page: First page to start checking for bad block marker usage
258
220
  *
259
- * Default read function for 8bit buswidth
221
+ * Returns an integer that corresponds to the page offset within a block, for
222
+ * a page that is used to store bad block markers. If no more pages are
223
+ * available, -EINVAL is returned.
260
224
  */
261
-static uint8_t nand_read_byte(struct mtd_info *mtd)
225
+int nand_bbm_get_next_page(struct nand_chip *chip, int page)
262
226
 {
263
-	struct nand_chip *chip = mtd_to_nand(mtd);
264
-	return readb(chip->IO_ADDR_R);
265
-}
227
+	struct mtd_info *mtd = nand_to_mtd(chip);
228
+	int last_page = ((mtd->erasesize - mtd->writesize) >>
229
+			 chip->page_shift) & chip->pagemask;
230
+	unsigned int bbm_flags = NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE
231
+		| NAND_BBM_LASTPAGE;
266
232
 
267
-/**
268
- * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
269
- * @mtd: MTD device structure
270
- *
271
- * Default read function for 16bit buswidth with endianness conversion.
272
- *
273
- */
274
-static uint8_t nand_read_byte16(struct mtd_info *mtd)
275
-{
276
-	struct nand_chip *chip = mtd_to_nand(mtd);
277
-	return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
278
-}
233
+	if (page == 0 && !(chip->options & bbm_flags))
234
+		return 0;
235
+	if (page == 0 && chip->options & NAND_BBM_FIRSTPAGE)
236
+		return 0;
237
+	if (page <= 1 && chip->options & NAND_BBM_SECONDPAGE)
238
+		return 1;
239
+	if (page <= last_page && chip->options & NAND_BBM_LASTPAGE)
240
+		return last_page;
279
241
 
280
-/**
281
- * nand_read_word - [DEFAULT] read one word from the chip
282
- * @mtd: MTD device structure
283
- *
284
- * Default read function for 16bit buswidth without endianness conversion.
285
- */
286
-static u16 nand_read_word(struct mtd_info *mtd)
287
-{
288
-	struct nand_chip *chip = mtd_to_nand(mtd);
289
-	return readw(chip->IO_ADDR_R);
290
-}
291
-
292
-/**
293
- * nand_select_chip - [DEFAULT] control CE line
294
- * @mtd: MTD device structure
295
- * @chipnr: chipnumber to select, -1 for deselect
296
- *
297
- * Default select function for 1 chip devices.
298
- */
299
-static void nand_select_chip(struct mtd_info *mtd, int chipnr)
300
-{
301
-	struct nand_chip *chip = mtd_to_nand(mtd);
302
-
303
-	switch (chipnr) {
304
-	case -1:
305
-		chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
306
-		break;
307
-	case 0:
308
-		break;
309
-
310
-	default:
311
-		BUG();
312
-	}
313
-}
314
-
315
-/**
316
- * nand_write_byte - [DEFAULT] write single byte to chip
317
- * @mtd: MTD device structure
318
- * @byte: value to write
319
- *
320
- * Default function to write a byte to I/O[7:0]
321
- */
322
-static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
323
-{
324
-	struct nand_chip *chip = mtd_to_nand(mtd);
325
-
326
-	chip->write_buf(mtd, &byte, 1);
327
-}
328
-
329
-/**
330
- * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
331
- * @mtd: MTD device structure
332
- * @byte: value to write
333
- *
334
- * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
335
- */
336
-static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
337
-{
338
-	struct nand_chip *chip = mtd_to_nand(mtd);
339
-	uint16_t word = byte;
340
-
341
-	/*
342
-	 * It's not entirely clear what should happen to I/O[15:8] when writing
343
-	 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
344
-	 *
345
-	 *    When the host supports a 16-bit bus width, only data is
346
-	 *    transferred at the 16-bit width. All address and command line
347
-	 *    transfers shall use only the lower 8-bits of the data bus. During
348
-	 *    command transfers, the host may place any value on the upper
349
-	 *    8-bits of the data bus. During address transfers, the host shall
350
-	 *    set the upper 8-bits of the data bus to 00h.
351
-	 *
352
-	 * One user of the write_byte callback is nand_set_features. The
353
-	 * four parameters are specified to be written to I/O[7:0], but this is
354
-	 * neither an address nor a command transfer. Let's assume a 0 on the
355
-	 * upper I/O lines is OK.
356
-	 */
357
-	chip->write_buf(mtd, (uint8_t *)&word, 2);
358
-}
359
-
360
-/**
361
- * nand_write_buf - [DEFAULT] write buffer to chip
362
- * @mtd: MTD device structure
363
- * @buf: data buffer
364
- * @len: number of bytes to write
365
- *
366
- * Default write function for 8bit buswidth.
367
- */
368
-static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
369
-{
370
-	struct nand_chip *chip = mtd_to_nand(mtd);
371
-
372
-	iowrite8_rep(chip->IO_ADDR_W, buf, len);
373
-}
374
-
375
-/**
376
- * nand_read_buf - [DEFAULT] read chip data into buffer
377
- * @mtd: MTD device structure
378
- * @buf: buffer to store date
379
- * @len: number of bytes to read
380
- *
381
- * Default read function for 8bit buswidth.
382
- */
383
-static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
384
-{
385
-	struct nand_chip *chip = mtd_to_nand(mtd);
386
-
387
-	ioread8_rep(chip->IO_ADDR_R, buf, len);
388
-}
389
-
390
-/**
391
- * nand_write_buf16 - [DEFAULT] write buffer to chip
392
- * @mtd: MTD device structure
393
- * @buf: data buffer
394
- * @len: number of bytes to write
395
- *
396
- * Default write function for 16bit buswidth.
397
- */
398
-static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
399
-{
400
-	struct nand_chip *chip = mtd_to_nand(mtd);
401
-	u16 *p = (u16 *) buf;
402
-
403
-	iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
404
-}
405
-
406
-/**
407
- * nand_read_buf16 - [DEFAULT] read chip data into buffer
408
- * @mtd: MTD device structure
409
- * @buf: buffer to store date
410
- * @len: number of bytes to read
411
- *
412
- * Default read function for 16bit buswidth.
413
- */
414
-static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
415
-{
416
-	struct nand_chip *chip = mtd_to_nand(mtd);
417
-	u16 *p = (u16 *) buf;
418
-
419
-	ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
242
+	return -EINVAL;
420
243
 }
421
244
 
422
245
 /**
423
246
  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
424
- * @mtd: MTD device structure
247
+ * @chip: NAND chip object
425
248
  * @ofs: offset from device start
426
249
  *
427
250
  * Check, if the block is bad.
428
251
  */
429
-static int nand_block_bad(struct mtd_info *mtd, loff_t ofs)
252
+static int nand_block_bad(struct nand_chip *chip, loff_t ofs)
430
253
 {
431
-	int page, page_end, res;
432
-	struct nand_chip *chip = mtd_to_nand(mtd);
254
+	int first_page, page_offset;
255
+	int res;
433
256
 	u8 bad;
434
257
 
435
-	if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
436
-		ofs += mtd->erasesize - mtd->writesize;
258
+	first_page = (int)(ofs >> chip->page_shift) & chip->pagemask;
259
+	page_offset = nand_bbm_get_next_page(chip, 0);
437
260
 
438
-	page = (int)(ofs >> chip->page_shift) & chip->pagemask;
439
-	page_end = page + (chip->bbt_options & NAND_BBT_SCAN2NDPAGE ? 2 : 1);
440
-
441
-	for (; page < page_end; page++) {
442
-		res = chip->ecc.read_oob(mtd, chip, page);
261
+	while (page_offset >= 0) {
262
+		res = chip->ecc.read_oob(chip, first_page + page_offset);
443
263
 		if (res < 0)
444
264
 			return res;
445
265
 
..
..
@@ -451,115 +271,56 @@
451
271
 			res = hweight8(bad) < chip->badblockbits;
452
272
 		if (res)
453
273
 			return res;
274
+
275
+		page_offset = nand_bbm_get_next_page(chip, page_offset + 1);
454
276
 	}
455
277
 
456
278
 	return 0;
457
279
 }
458
280
 
459
-/**
460
- * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
461
- * @mtd: MTD device structure
462
- * @ofs: offset from device start
463
- *
464
- * This is the default implementation, which can be overridden by a hardware
465
- * specific driver. It provides the details for writing a bad block marker to a
466
- * block.
467
- */
468
-static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
281
+static int nand_isbad_bbm(struct nand_chip *chip, loff_t ofs)
469
282
 {
470
-	struct nand_chip *chip = mtd_to_nand(mtd);
471
-	struct mtd_oob_ops ops;
472
-	uint8_t buf[2] = { 0, 0 };
473
-	int ret = 0, res, i = 0;
283
+	if (chip->options & NAND_NO_BBM_QUIRK)
284
+		return 0;
474
285
 
475
-	memset(&ops, 0, sizeof(ops));
476
-	ops.oobbuf = buf;
477
-	ops.ooboffs = chip->badblockpos;
478
-	if (chip->options & NAND_BUSWIDTH_16) {
479
-		ops.ooboffs &= ~0x01;
480
-		ops.len = ops.ooblen = 2;
481
-	} else {
482
-		ops.len = ops.ooblen = 1;
483
-	}
484
-	ops.mode = MTD_OPS_PLACE_OOB;
286
+	if (chip->legacy.block_bad)
287
+		return chip->legacy.block_bad(chip, ofs);
485
288
 
486
-	/* Write to first/last page(s) if necessary */
487
-	if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
488
-		ofs += mtd->erasesize - mtd->writesize;
489
-	do {
490
-		res = nand_do_write_oob(mtd, ofs, &ops);
491
-		if (!ret)
492
-			ret = res;
493
-
494
-		i++;
495
-		ofs += mtd->writesize;
496
-	} while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
497
-
498
-	return ret;
289
+	return nand_block_bad(chip, ofs);
499
290
 }
500
291
 
501
292
 /**
502
- * nand_block_markbad_lowlevel - mark a block bad
503
- * @mtd: MTD device structure
504
- * @ofs: offset from device start
293
+ * nand_get_device - [GENERIC] Get chip for selected access
294
+ * @chip: NAND chip structure
505
295
  *
506
- * This function performs the generic NAND bad block marking steps (i.e., bad
507
- * block table(s) and/or marker(s)). We only allow the hardware driver to
508
- * specify how to write bad block markers to OOB (chip->block_markbad).
296
+ * Lock the device and its controller for exclusive access
509
297
  *
510
- * We try operations in the following order:
511
- *
512
- *  (1) erase the affected block, to allow OOB marker to be written cleanly
513
- *  (2) write bad block marker to OOB area of affected block (unless flag
514
- *      NAND_BBT_NO_OOB_BBM is present)
515
- *  (3) update the BBT
516
- *
517
- * Note that we retain the first error encountered in (2) or (3), finish the
518
- * procedures, and dump the error in the end.
519
-*/
520
-static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
298
+ * Return: -EBUSY if the chip has been suspended, 0 otherwise
299
+ */
300
+static void nand_get_device(struct nand_chip *chip)
521
301
 {
522
-	struct nand_chip *chip = mtd_to_nand(mtd);
523
-	int res, ret = 0;
302
+	/* Wait until the device is resumed. */
303
+	while (1) {
304
+		mutex_lock(&chip->lock);
305
+		if (!chip->suspended) {
306
+			mutex_lock(&chip->controller->lock);
307
+			return;
308
+		}
309
+		mutex_unlock(&chip->lock);
524
310
 
525
-	if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
526
-		struct erase_info einfo;
527
-
528
-		/* Attempt erase before marking OOB */
529
-		memset(&einfo, 0, sizeof(einfo));
530
-		einfo.addr = ofs;
531
-		einfo.len = 1ULL << chip->phys_erase_shift;
532
-		nand_erase_nand(mtd, &einfo, 0);
533
-
534
-		/* Write bad block marker to OOB */
535
-		nand_get_device(mtd, FL_WRITING);
536
-		ret = chip->block_markbad(mtd, ofs);
537
-		nand_release_device(mtd);
311
+		wait_event(chip->resume_wq, !chip->suspended);
538
312
 	}
539
-
540
-	/* Mark block bad in BBT */
541
-	if (chip->bbt) {
542
-		res = nand_markbad_bbt(mtd, ofs);
543
-		if (!ret)
544
-			ret = res;
545
-	}
546
-
547
-	if (!ret)
548
-		mtd->ecc_stats.badblocks++;
549
-
550
-	return ret;
551
313
 }
552
314
 
553
315
 /**
554
316
  * nand_check_wp - [GENERIC] check if the chip is write protected
555
- * @mtd: MTD device structure
317
+ * @chip: NAND chip object
556
318
  *
557
319
  * Check, if the device is write protected. The function expects, that the
558
320
  * device is already selected.
559
321
  */
560
-static int nand_check_wp(struct mtd_info *mtd)
322
+static int nand_check_wp(struct nand_chip *chip)
561
323
 {
562
-	struct nand_chip *chip = mtd_to_nand(mtd);
563
324
 	u8 status;
564
325
 	int ret;
565
326
 
..
..
@@ -576,6 +337,223 @@
576
337
 }
577
338
 
578
339
 /**
340
+ * nand_fill_oob - [INTERN] Transfer client buffer to oob
341
+ * @chip: NAND chip object
342
+ * @oob: oob data buffer
343
+ * @len: oob data write length
344
+ * @ops: oob ops structure
345
+ */
346
+static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, size_t len,
347
+			      struct mtd_oob_ops *ops)
348
+{
349
+	struct mtd_info *mtd = nand_to_mtd(chip);
350
+	int ret;
351
+
352
+	/*
353
+	 * Initialise to all 0xFF, to avoid the possibility of left over OOB
354
+	 * data from a previous OOB read.
355
+	 */
356
+	memset(chip->oob_poi, 0xff, mtd->oobsize);
357
+
358
+	switch (ops->mode) {
359
+
360
+	case MTD_OPS_PLACE_OOB:
361
+	case MTD_OPS_RAW:
362
+		memcpy(chip->oob_poi + ops->ooboffs, oob, len);
363
+		return oob + len;
364
+
365
+	case MTD_OPS_AUTO_OOB:
366
+		ret = mtd_ooblayout_set_databytes(mtd, oob, chip->oob_poi,
367
+						  ops->ooboffs, len);
368
+		BUG_ON(ret);
369
+		return oob + len;
370
+
371
+	default:
372
+		BUG();
373
+	}
374
+	return NULL;
375
+}
376
+
377
+/**
378
+ * nand_do_write_oob - [MTD Interface] NAND write out-of-band
379
+ * @chip: NAND chip object
380
+ * @to: offset to write to
381
+ * @ops: oob operation description structure
382
+ *
383
+ * NAND write out-of-band.
384
+ */
385
+static int nand_do_write_oob(struct nand_chip *chip, loff_t to,
386
+			     struct mtd_oob_ops *ops)
387
+{
388
+	struct mtd_info *mtd = nand_to_mtd(chip);
389
+	int chipnr, page, status, len, ret;
390
+
391
+	pr_debug("%s: to = 0x%08x, len = %i\n",
392
+			 __func__, (unsigned int)to, (int)ops->ooblen);
393
+
394
+	len = mtd_oobavail(mtd, ops);
395
+
396
+	/* Do not allow write past end of page */
397
+	if ((ops->ooboffs + ops->ooblen) > len) {
398
+		pr_debug("%s: attempt to write past end of page\n",
399
+				__func__);
400
+		return -EINVAL;
401
+	}
402
+
403
+	chipnr = (int)(to >> chip->chip_shift);
404
+
405
+	/*
406
+	 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
407
+	 * of my DiskOnChip 2000 test units) will clear the whole data page too
408
+	 * if we don't do this. I have no clue why, but I seem to have 'fixed'
409
+	 * it in the doc2000 driver in August 1999.  dwmw2.
410
+	 */
411
+	ret = nand_reset(chip, chipnr);
412
+	if (ret)
413
+		return ret;
414
+
415
+	nand_select_target(chip, chipnr);
416
+
417
+	/* Shift to get page */
418
+	page = (int)(to >> chip->page_shift);
419
+
420
+	/* Check, if it is write protected */
421
+	if (nand_check_wp(chip)) {
422
+		nand_deselect_target(chip);
423
+		return -EROFS;
424
+	}
425
+
426
+	/* Invalidate the page cache, if we write to the cached page */
427
+	if (page == chip->pagecache.page)
428
+		chip->pagecache.page = -1;
429
+
430
+	nand_fill_oob(chip, ops->oobbuf, ops->ooblen, ops);
431
+
432
+	if (ops->mode == MTD_OPS_RAW)
433
+		status = chip->ecc.write_oob_raw(chip, page & chip->pagemask);
434
+	else
435
+		status = chip->ecc.write_oob(chip, page & chip->pagemask);
436
+
437
+	nand_deselect_target(chip);
438
+
439
+	if (status)
440
+		return status;
441
+
442
+	ops->oobretlen = ops->ooblen;
443
+
444
+	return 0;
445
+}
446
+
447
+/**
448
+ * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
449
+ * @chip: NAND chip object
450
+ * @ofs: offset from device start
451
+ *
452
+ * This is the default implementation, which can be overridden by a hardware
453
+ * specific driver. It provides the details for writing a bad block marker to a
454
+ * block.
455
+ */
456
+static int nand_default_block_markbad(struct nand_chip *chip, loff_t ofs)
457
+{
458
+	struct mtd_info *mtd = nand_to_mtd(chip);
459
+	struct mtd_oob_ops ops;
460
+	uint8_t buf[2] = { 0, 0 };
461
+	int ret = 0, res, page_offset;
462
+
463
+	memset(&ops, 0, sizeof(ops));
464
+	ops.oobbuf = buf;
465
+	ops.ooboffs = chip->badblockpos;
466
+	if (chip->options & NAND_BUSWIDTH_16) {
467
+		ops.ooboffs &= ~0x01;
468
+		ops.len = ops.ooblen = 2;
469
+	} else {
470
+		ops.len = ops.ooblen = 1;
471
+	}
472
+	ops.mode = MTD_OPS_PLACE_OOB;
473
+
474
+	page_offset = nand_bbm_get_next_page(chip, 0);
475
+
476
+	while (page_offset >= 0) {
477
+		res = nand_do_write_oob(chip,
478
+					ofs + (page_offset * mtd->writesize),
479
+					&ops);
480
+
481
+		if (!ret)
482
+			ret = res;
483
+
484
+		page_offset = nand_bbm_get_next_page(chip, page_offset + 1);
485
+	}
486
+
487
+	return ret;
488
+}
489
+
490
+/**
491
+ * nand_markbad_bbm - mark a block by updating the BBM
492
+ * @chip: NAND chip object
493
+ * @ofs: offset of the block to mark bad
494
+ */
495
+int nand_markbad_bbm(struct nand_chip *chip, loff_t ofs)
496
+{
497
+	if (chip->legacy.block_markbad)
498
+		return chip->legacy.block_markbad(chip, ofs);
499
+
500
+	return nand_default_block_markbad(chip, ofs);
501
+}
502
+
503
+/**
504
+ * nand_block_markbad_lowlevel - mark a block bad
505
+ * @chip: NAND chip object
506
+ * @ofs: offset from device start
507
+ *
508
+ * This function performs the generic NAND bad block marking steps (i.e., bad
509
+ * block table(s) and/or marker(s)). We only allow the hardware driver to
510
+ * specify how to write bad block markers to OOB (chip->legacy.block_markbad).
511
+ *
512
+ * We try operations in the following order:
513
+ *
514
+ *  (1) erase the affected block, to allow OOB marker to be written cleanly
515
+ *  (2) write bad block marker to OOB area of affected block (unless flag
516
+ *      NAND_BBT_NO_OOB_BBM is present)
517
+ *  (3) update the BBT
518
+ *
519
+ * Note that we retain the first error encountered in (2) or (3), finish the
520
+ * procedures, and dump the error in the end.
521
+*/
522
+static int nand_block_markbad_lowlevel(struct nand_chip *chip, loff_t ofs)
523
+{
524
+	struct mtd_info *mtd = nand_to_mtd(chip);
525
+	int res, ret = 0;
526
+
527
+	if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
528
+		struct erase_info einfo;
529
+
530
+		/* Attempt erase before marking OOB */
531
+		memset(&einfo, 0, sizeof(einfo));
532
+		einfo.addr = ofs;
533
+		einfo.len = 1ULL << chip->phys_erase_shift;
534
+		nand_erase_nand(chip, &einfo, 0);
535
+
536
+		/* Write bad block marker to OOB */
537
+		nand_get_device(chip);
538
+
539
+		ret = nand_markbad_bbm(chip, ofs);
540
+		nand_release_device(chip);
541
+	}
542
+
543
+	/* Mark block bad in BBT */
544
+	if (chip->bbt) {
545
+		res = nand_markbad_bbt(chip, ofs);
546
+		if (!ret)
547
+			ret = res;
548
+	}
549
+
550
+	if (!ret)
551
+		mtd->ecc_stats.badblocks++;
552
+
553
+	return ret;
554
+}
555
+
556
+/**
579
557
  * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
580
558
  * @mtd: MTD device structure
581
559
  * @ofs: offset from device start
..
..
@@ -589,103 +567,26 @@
589
567
 	if (!chip->bbt)
590
568
 		return 0;
591
569
 	/* Return info from the table */
592
-	return nand_isreserved_bbt(mtd, ofs);
570
+	return nand_isreserved_bbt(chip, ofs);
593
571
 }
594
572
 
595
573
 /**
596
574
  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
597
- * @mtd: MTD device structure
575
+ * @chip: NAND chip object
598
576
  * @ofs: offset from device start
599
577
  * @allowbbt: 1, if its allowed to access the bbt area
600
578
  *
601
579
  * Check, if the block is bad. Either by reading the bad block table or
602
580
  * calling of the scan function.
603
581
  */
604
-static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt)
582
+static int nand_block_checkbad(struct nand_chip *chip, loff_t ofs, int allowbbt)
605
583
 {
606
-	struct nand_chip *chip = mtd_to_nand(mtd);
607
-
608
-	if (!chip->bbt)
609
-		return chip->block_bad(mtd, ofs);
610
-
611
584
 	/* Return info from the table */
612
-	return nand_isbad_bbt(mtd, ofs, allowbbt);
585
+	if (chip->bbt)
586
+		return nand_isbad_bbt(chip, ofs, allowbbt);
587
+
588
+	return nand_isbad_bbm(chip, ofs);
613
589
 }
614
-
615
-/**
616
- * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
617
- * @mtd: MTD device structure
618
- * @timeo: Timeout
619
- *
620
- * Helper function for nand_wait_ready used when needing to wait in interrupt
621
- * context.
622
- */
623
-static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
624
-{
625
-	struct nand_chip *chip = mtd_to_nand(mtd);
626
-	int i;
627
-
628
-	/* Wait for the device to get ready */
629
-	for (i = 0; i < timeo; i++) {
630
-		if (chip->dev_ready(mtd))
631
-			break;
632
-		touch_softlockup_watchdog();
633
-		mdelay(1);
634
-	}
635
-}
636
-
637
-/**
638
- * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
639
- * @mtd: MTD device structure
640
- *
641
- * Wait for the ready pin after a command, and warn if a timeout occurs.
642
- */
643
-void nand_wait_ready(struct mtd_info *mtd)
644
-{
645
-	struct nand_chip *chip = mtd_to_nand(mtd);
646
-	unsigned long timeo = 400;
647
-
648
-	if (in_interrupt() || oops_in_progress)
649
-		return panic_nand_wait_ready(mtd, timeo);
650
-
651
-	/* Wait until command is processed or timeout occurs */
652
-	timeo = jiffies + msecs_to_jiffies(timeo);
653
-	do {
654
-		if (chip->dev_ready(mtd))
655
-			return;
656
-		cond_resched();
657
-	} while (time_before(jiffies, timeo));
658
-
659
-	if (!chip->dev_ready(mtd))
660
-		pr_warn_ratelimited("timeout while waiting for chip to become ready\n");
661
-}
662
-EXPORT_SYMBOL_GPL(nand_wait_ready);
663
-
664
-/**
665
- * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
666
- * @mtd: MTD device structure
667
- * @timeo: Timeout in ms
668
- *
669
- * Wait for status ready (i.e. command done) or timeout.
670
- */
671
-static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo)
672
-{
673
-	register struct nand_chip *chip = mtd_to_nand(mtd);
674
-	int ret;
675
-
676
-	timeo = jiffies + msecs_to_jiffies(timeo);
677
-	do {
678
-		u8 status;
679
-
680
-		ret = nand_read_data_op(chip, &status, sizeof(status), true);
681
-		if (ret)
682
-			return;
683
-
684
-		if (status & NAND_STATUS_READY)
685
-			break;
686
-		touch_softlockup_watchdog();
687
-	} while (time_before(jiffies, timeo));
688
-};
689
590
 
690
591
 /**
691
592
  * nand_soft_waitrdy - Poll STATUS reg until RDY bit is set to 1
..
..
@@ -710,20 +611,26 @@
710
611
 	u8 status = 0;
711
612
 	int ret;
712
613
 
713
-	if (!chip->exec_op)
614
+	if (!nand_has_exec_op(chip))
714
615
 		return -ENOTSUPP;
715
616
 
716
617
 	/* Wait tWB before polling the STATUS reg. */
717
-	timings = nand_get_sdr_timings(&chip->data_interface);
618
+	timings = nand_get_sdr_timings(nand_get_interface_config(chip));
718
619
 	ndelay(PSEC_TO_NSEC(timings->tWB_max));
719
620
 
720
621
 	ret = nand_status_op(chip, NULL);
721
622
 	if (ret)
722
623
 		return ret;
723
624
 
724
-	timeout_ms = jiffies + msecs_to_jiffies(timeout_ms);
625
+	/*
626
+	 * +1 below is necessary because if we are now in the last fraction
627
+	 * of jiffy and msecs_to_jiffies is 1 then we will wait only that
628
+	 * small jiffy fraction - possibly leading to false timeout
629
+	 */
630
+	timeout_ms = jiffies + msecs_to_jiffies(timeout_ms) + 1;
725
631
 	do {
726
-		ret = nand_read_data_op(chip, &status, sizeof(status), true);
632
+		ret = nand_read_data_op(chip, &status, sizeof(status), true,
633
+					false);
727
634
 		if (ret)
728
635
 			break;
729
636
 
..
..
@@ -753,332 +660,43 @@
753
660
 EXPORT_SYMBOL_GPL(nand_soft_waitrdy);
754
661
 
755
662
 /**
756
- * nand_command - [DEFAULT] Send command to NAND device
757
- * @mtd: MTD device structure
758
- * @command: the command to be sent
759
- * @column: the column address for this command, -1 if none
760
- * @page_addr: the page address for this command, -1 if none
663
+ * nand_gpio_waitrdy - Poll R/B GPIO pin until ready
664
+ * @chip: NAND chip structure
665
+ * @gpiod: GPIO descriptor of R/B pin
666
+ * @timeout_ms: Timeout in ms
761
667
  *
762
- * Send command to NAND device. This function is used for small page devices
763
- * (512 Bytes per page).
764
- */
765
-static void nand_command(struct mtd_info *mtd, unsigned int command,
766
-			 int column, int page_addr)
767
-{
768
-	register struct nand_chip *chip = mtd_to_nand(mtd);
769
-	int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
770
-
771
-	/* Write out the command to the device */
772
-	if (command == NAND_CMD_SEQIN) {
773
-		int readcmd;
774
-
775
-		if (column >= mtd->writesize) {
776
-			/* OOB area */
777
-			column -= mtd->writesize;
778
-			readcmd = NAND_CMD_READOOB;
779
-		} else if (column < 256) {
780
-			/* First 256 bytes --> READ0 */
781
-			readcmd = NAND_CMD_READ0;
782
-		} else {
783
-			column -= 256;
784
-			readcmd = NAND_CMD_READ1;
785
-		}
786
-		chip->cmd_ctrl(mtd, readcmd, ctrl);
787
-		ctrl &= ~NAND_CTRL_CHANGE;
788
-	}
789
-	if (command != NAND_CMD_NONE)
790
-		chip->cmd_ctrl(mtd, command, ctrl);
791
-
792
-	/* Address cycle, when necessary */
793
-	ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
794
-	/* Serially input address */
795
-	if (column != -1) {
796
-		/* Adjust columns for 16 bit buswidth */
797
-		if (chip->options & NAND_BUSWIDTH_16 &&
798
-				!nand_opcode_8bits(command))
799
-			column >>= 1;
800
-		chip->cmd_ctrl(mtd, column, ctrl);
801
-		ctrl &= ~NAND_CTRL_CHANGE;
802
-	}
803
-	if (page_addr != -1) {
804
-		chip->cmd_ctrl(mtd, page_addr, ctrl);
805
-		ctrl &= ~NAND_CTRL_CHANGE;
806
-		chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
807
-		if (chip->options & NAND_ROW_ADDR_3)
808
-			chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
809
-	}
810
-	chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
811
-
812
-	/*
813
-	 * Program and erase have their own busy handlers status and sequential
814
-	 * in needs no delay
815
-	 */
816
-	switch (command) {
817
-
818
-	case NAND_CMD_NONE:
819
-	case NAND_CMD_PAGEPROG:
820
-	case NAND_CMD_ERASE1:
821
-	case NAND_CMD_ERASE2:
822
-	case NAND_CMD_SEQIN:
823
-	case NAND_CMD_STATUS:
824
-	case NAND_CMD_READID:
825
-	case NAND_CMD_SET_FEATURES:
826
-		return;
827
-
828
-	case NAND_CMD_RESET:
829
-		if (chip->dev_ready)
830
-			break;
831
-		udelay(chip->chip_delay);
832
-		chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
833
-			       NAND_CTRL_CLE | NAND_CTRL_CHANGE);
834
-		chip->cmd_ctrl(mtd,
835
-			       NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
836
-		/* EZ-NAND can take upto 250ms as per ONFi v4.0 */
837
-		nand_wait_status_ready(mtd, 250);
838
-		return;
839
-
840
-		/* This applies to read commands */
841
-	case NAND_CMD_READ0:
842
-		/*
843
-		 * READ0 is sometimes used to exit GET STATUS mode. When this
844
-		 * is the case no address cycles are requested, and we can use
845
-		 * this information to detect that we should not wait for the
846
-		 * device to be ready.
847
-		 */
848
-		if (column == -1 && page_addr == -1)
849
-			return;
850
-
851
-	default:
852
-		/*
853
-		 * If we don't have access to the busy pin, we apply the given
854
-		 * command delay
855
-		 */
856
-		if (!chip->dev_ready) {
857
-			udelay(chip->chip_delay);
858
-			return;
859
-		}
860
-	}
861
-	/*
862
-	 * Apply this short delay always to ensure that we do wait tWB in
863
-	 * any case on any machine.
864
-	 */
865
-	ndelay(100);
866
-
867
-	nand_wait_ready(mtd);
868
-}
869
-
870
-static void nand_ccs_delay(struct nand_chip *chip)
871
-{
872
-	/*
873
-	 * The controller already takes care of waiting for tCCS when the RNDIN
874
-	 * or RNDOUT command is sent, return directly.
875
-	 */
876
-	if (!(chip->options & NAND_WAIT_TCCS))
877
-		return;
878
-
879
-	/*
880
-	 * Wait tCCS_min if it is correctly defined, otherwise wait 500ns
881
-	 * (which should be safe for all NANDs).
882
-	 */
883
-	if (chip->setup_data_interface)
884
-		ndelay(chip->data_interface.timings.sdr.tCCS_min / 1000);
885
-	else
886
-		ndelay(500);
887
-}
888
-
889
-/**
890
- * nand_command_lp - [DEFAULT] Send command to NAND large page device
891
- * @mtd: MTD device structure
892
- * @command: the command to be sent
893
- * @column: the column address for this command, -1 if none
894
- * @page_addr: the page address for this command, -1 if none
668
+ * Poll the R/B GPIO pin until it becomes ready. If that does not happen
669
+ * whitin the specified timeout, -ETIMEDOUT is returned.
895
670
  *
896
- * Send command to NAND device. This is the version for the new large page
897
- * devices. We don't have the separate regions as we have in the small page
898
- * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
671
+ * This helper is intended to be used when the controller has access to the
672
+ * NAND R/B pin over GPIO.
673
+ *
674
+ * Return 0 if the R/B pin indicates chip is ready, a negative error otherwise.
899
675
  */
900
-static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
901
-			    int column, int page_addr)
676
+int nand_gpio_waitrdy(struct nand_chip *chip, struct gpio_desc *gpiod,
677
+		      unsigned long timeout_ms)
902
678
 {
903
-	register struct nand_chip *chip = mtd_to_nand(mtd);
904
-
905
-	/* Emulate NAND_CMD_READOOB */
906
-	if (command == NAND_CMD_READOOB) {
907
-		column += mtd->writesize;
908
-		command = NAND_CMD_READ0;
909
-	}
910
-
911
-	/* Command latch cycle */
912
-	if (command != NAND_CMD_NONE)
913
-		chip->cmd_ctrl(mtd, command,
914
-			       NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
915
-
916
-	if (column != -1 || page_addr != -1) {
917
-		int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
918
-
919
-		/* Serially input address */
920
-		if (column != -1) {
921
-			/* Adjust columns for 16 bit buswidth */
922
-			if (chip->options & NAND_BUSWIDTH_16 &&
923
-					!nand_opcode_8bits(command))
924
-				column >>= 1;
925
-			chip->cmd_ctrl(mtd, column, ctrl);
926
-			ctrl &= ~NAND_CTRL_CHANGE;
927
-
928
-			/* Only output a single addr cycle for 8bits opcodes. */
929
-			if (!nand_opcode_8bits(command))
930
-				chip->cmd_ctrl(mtd, column >> 8, ctrl);
931
-		}
932
-		if (page_addr != -1) {
933
-			chip->cmd_ctrl(mtd, page_addr, ctrl);
934
-			chip->cmd_ctrl(mtd, page_addr >> 8,
935
-				       NAND_NCE | NAND_ALE);
936
-			if (chip->options & NAND_ROW_ADDR_3)
937
-				chip->cmd_ctrl(mtd, page_addr >> 16,
938
-					       NAND_NCE | NAND_ALE);
939
-		}
940
-	}
941
-	chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
942
679
 
943
680
 	/*
944
-	 * Program and erase have their own busy handlers status, sequential
945
-	 * in and status need no delay.
681
+	 * Wait until R/B pin indicates chip is ready or timeout occurs.
682
+	 * +1 below is necessary because if we are now in the last fraction
683
+	 * of jiffy and msecs_to_jiffies is 1 then we will wait only that
684
+	 * small jiffy fraction - possibly leading to false timeout.
946
685
 	 */
947
-	switch (command) {
948
-
949
-	case NAND_CMD_NONE:
950
-	case NAND_CMD_CACHEDPROG:
951
-	case NAND_CMD_PAGEPROG:
952
-	case NAND_CMD_ERASE1:
953
-	case NAND_CMD_ERASE2:
954
-	case NAND_CMD_SEQIN:
955
-	case NAND_CMD_STATUS:
956
-	case NAND_CMD_READID:
957
-	case NAND_CMD_SET_FEATURES:
958
-		return;
959
-
960
-	case NAND_CMD_RNDIN:
961
-		nand_ccs_delay(chip);
962
-		return;
963
-
964
-	case NAND_CMD_RESET:
965
-		if (chip->dev_ready)
966
-			break;
967
-		udelay(chip->chip_delay);
968
-		chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
969
-			       NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
970
-		chip->cmd_ctrl(mtd, NAND_CMD_NONE,
971
-			       NAND_NCE | NAND_CTRL_CHANGE);
972
-		/* EZ-NAND can take upto 250ms as per ONFi v4.0 */
973
-		nand_wait_status_ready(mtd, 250);
974
-		return;
975
-
976
-	case NAND_CMD_RNDOUT:
977
-		/* No ready / busy check necessary */
978
-		chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
979
-			       NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
980
-		chip->cmd_ctrl(mtd, NAND_CMD_NONE,
981
-			       NAND_NCE | NAND_CTRL_CHANGE);
982
-
983
-		nand_ccs_delay(chip);
984
-		return;
985
-
986
-	case NAND_CMD_READ0:
987
-		/*
988
-		 * READ0 is sometimes used to exit GET STATUS mode. When this
989
-		 * is the case no address cycles are requested, and we can use
990
-		 * this information to detect that READSTART should not be
991
-		 * issued.
992
-		 */
993
-		if (column == -1 && page_addr == -1)
994
-			return;
995
-
996
-		chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
997
-			       NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
998
-		chip->cmd_ctrl(mtd, NAND_CMD_NONE,
999
-			       NAND_NCE | NAND_CTRL_CHANGE);
1000
-
1001
-		/* This applies to read commands */
1002
-	default:
1003
-		/*
1004
-		 * If we don't have access to the busy pin, we apply the given
1005
-		 * command delay.
1006
-		 */
1007
-		if (!chip->dev_ready) {
1008
-			udelay(chip->chip_delay);
1009
-			return;
1010
-		}
1011
-	}
1012
-
1013
-	/*
1014
-	 * Apply this short delay always to ensure that we do wait tWB in
1015
-	 * any case on any machine.
1016
-	 */
1017
-	ndelay(100);
1018
-
1019
-	nand_wait_ready(mtd);
1020
-}
1021
-
1022
-/**
1023
- * panic_nand_get_device - [GENERIC] Get chip for selected access
1024
- * @chip: the nand chip descriptor
1025
- * @mtd: MTD device structure
1026
- * @new_state: the state which is requested
1027
- *
1028
- * Used when in panic, no locks are taken.
1029
- */
1030
-static void panic_nand_get_device(struct nand_chip *chip,
1031
-		      struct mtd_info *mtd, int new_state)
1032
-{
1033
-	/* Hardware controller shared among independent devices */
1034
-	chip->controller->active = chip;
1035
-	chip->state = new_state;
1036
-}
1037
-
1038
-/**
1039
- * nand_get_device - [GENERIC] Get chip for selected access
1040
- * @mtd: MTD device structure
1041
- * @new_state: the state which is requested
1042
- *
1043
- * Get the device and lock it for exclusive access
1044
- */
1045
-static int
1046
-nand_get_device(struct mtd_info *mtd, int new_state)
1047
-{
1048
-	struct nand_chip *chip = mtd_to_nand(mtd);
1049
-	spinlock_t *lock = &chip->controller->lock;
1050
-	wait_queue_head_t *wq = &chip->controller->wq;
1051
-	DECLARE_WAITQUEUE(wait, current);
1052
-retry:
1053
-	spin_lock(lock);
1054
-
1055
-	/* Hardware controller shared among independent devices */
1056
-	if (!chip->controller->active)
1057
-		chip->controller->active = chip;
1058
-
1059
-	if (chip->controller->active == chip && chip->state == FL_READY) {
1060
-		chip->state = new_state;
1061
-		spin_unlock(lock);
1062
-		return 0;
1063
-	}
1064
-	if (new_state == FL_PM_SUSPENDED) {
1065
-		if (chip->controller->active->state == FL_PM_SUSPENDED) {
1066
-			chip->state = FL_PM_SUSPENDED;
1067
-			spin_unlock(lock);
686
+	timeout_ms = jiffies + msecs_to_jiffies(timeout_ms) + 1;
687
+	do {
688
+		if (gpiod_get_value_cansleep(gpiod))
1068
689
 			return 0;
1069
-		}
1070
-	}
1071
-	set_current_state(TASK_UNINTERRUPTIBLE);
1072
-	add_wait_queue(wq, &wait);
1073
-	spin_unlock(lock);
1074
-	schedule();
1075
-	remove_wait_queue(wq, &wait);
1076
-	goto retry;
1077
-}
690
+
691
+		cond_resched();
692
+	} while	(time_before(jiffies, timeout_ms));
693
+
694
+	return gpiod_get_value_cansleep(gpiod) ? 0 : -ETIMEDOUT;
695
+};
696
+EXPORT_SYMBOL_GPL(nand_gpio_waitrdy);
1078
697
 
1079
698
 /**
1080
699
  * panic_nand_wait - [GENERIC] wait until the command is done
1081
- * @mtd: MTD device structure
1082
700
  * @chip: NAND chip structure
1083
701
  * @timeo: timeout
1084
702
  *
..
..
@@ -1086,20 +704,19 @@
1086
704
  * we are in interrupt context. May happen when in panic and trying to write
1087
705
  * an oops through mtdoops.
1088
706
  */
1089
-static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
1090
-			    unsigned long timeo)
707
+void panic_nand_wait(struct nand_chip *chip, unsigned long timeo)
1091
708
 {
1092
709
 	int i;
1093
710
 	for (i = 0; i < timeo; i++) {
1094
-		if (chip->dev_ready) {
1095
-			if (chip->dev_ready(mtd))
711
+		if (chip->legacy.dev_ready) {
712
+			if (chip->legacy.dev_ready(chip))
1096
713
 				break;
1097
714
 		} else {
1098
715
 			int ret;
1099
716
 			u8 status;
1100
717
 
1101
718
 			ret = nand_read_data_op(chip, &status, sizeof(status),
1102
-						true);
719
+						true, false);
1103
720
 			if (ret)
1104
721
 				return;
1105
722
 
..
..
@@ -1108,60 +725,6 @@
1108
725
 		}
1109
726
 		mdelay(1);
1110
727
 	}
1111
-}
1112
-
1113
-/**
1114
- * nand_wait - [DEFAULT] wait until the command is done
1115
- * @mtd: MTD device structure
1116
- * @chip: NAND chip structure
1117
- *
1118
- * Wait for command done. This applies to erase and program only.
1119
- */
1120
-static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
1121
-{
1122
-
1123
-	unsigned long timeo = 400;
1124
-	u8 status;
1125
-	int ret;
1126
-
1127
-	/*
1128
-	 * Apply this short delay always to ensure that we do wait tWB in any
1129
-	 * case on any machine.
1130
-	 */
1131
-	ndelay(100);
1132
-
1133
-	ret = nand_status_op(chip, NULL);
1134
-	if (ret)
1135
-		return ret;
1136
-
1137
-	if (in_interrupt() || oops_in_progress)
1138
-		panic_nand_wait(mtd, chip, timeo);
1139
-	else {
1140
-		timeo = jiffies + msecs_to_jiffies(timeo);
1141
-		do {
1142
-			if (chip->dev_ready) {
1143
-				if (chip->dev_ready(mtd))
1144
-					break;
1145
-			} else {
1146
-				ret = nand_read_data_op(chip, &status,
1147
-							sizeof(status), true);
1148
-				if (ret)
1149
-					return ret;
1150
-
1151
-				if (status & NAND_STATUS_READY)
1152
-					break;
1153
-			}
1154
-			cond_resched();
1155
-		} while (time_before(jiffies, timeo));
1156
-	}
1157
-
1158
-	ret = nand_read_data_op(chip, &status, sizeof(status), true);
1159
-	if (ret)
1160
-		return ret;
1161
-
1162
-	/* This can happen if in case of timeout or buggy dev_ready */
1163
-	WARN_ON(!(status & NAND_STATUS_READY));
1164
-	return status;
1165
728
 }
1166
729
 
1167
730
 static bool nand_supports_get_features(struct nand_chip *chip, int addr)
..
..
@@ -1177,49 +740,7 @@
1177
740
 }
1178
741
 
1179
742
 /**
1180
- * nand_get_features - wrapper to perform a GET_FEATURE
1181
- * @chip: NAND chip info structure
1182
- * @addr: feature address
1183
- * @subfeature_param: the subfeature parameters, a four bytes array
1184
- *
1185
- * Returns 0 for success, a negative error otherwise. Returns -ENOTSUPP if the
1186
- * operation cannot be handled.
1187
- */
1188
-int nand_get_features(struct nand_chip *chip, int addr,
1189
-		      u8 *subfeature_param)
1190
-{
1191
-	struct mtd_info *mtd = nand_to_mtd(chip);
1192
-
1193
-	if (!nand_supports_get_features(chip, addr))
1194
-		return -ENOTSUPP;
1195
-
1196
-	return chip->get_features(mtd, chip, addr, subfeature_param);
1197
-}
1198
-EXPORT_SYMBOL_GPL(nand_get_features);
1199
-
1200
-/**
1201
- * nand_set_features - wrapper to perform a SET_FEATURE
1202
- * @chip: NAND chip info structure
1203
- * @addr: feature address
1204
- * @subfeature_param: the subfeature parameters, a four bytes array
1205
- *
1206
- * Returns 0 for success, a negative error otherwise. Returns -ENOTSUPP if the
1207
- * operation cannot be handled.
1208
- */
1209
-int nand_set_features(struct nand_chip *chip, int addr,
1210
-		      u8 *subfeature_param)
1211
-{
1212
-	struct mtd_info *mtd = nand_to_mtd(chip);
1213
-
1214
-	if (!nand_supports_set_features(chip, addr))
1215
-		return -ENOTSUPP;
1216
-
1217
-	return chip->set_features(mtd, chip, addr, subfeature_param);
1218
-}
1219
-EXPORT_SYMBOL_GPL(nand_set_features);
1220
-
1221
-/**
1222
- * nand_reset_data_interface - Reset data interface and timings
743
+ * nand_reset_interface - Reset data interface and timings
1223
744
  * @chip: The NAND chip
1224
745
  * @chipnr: Internal die id
1225
746
  *
..
..
@@ -1227,12 +748,12 @@
1227
748
  *
1228
749
  * Returns 0 for success or negative error code otherwise.
1229
750
  */
1230
-static int nand_reset_data_interface(struct nand_chip *chip, int chipnr)
751
+static int nand_reset_interface(struct nand_chip *chip, int chipnr)
1231
752
 {
1232
-	struct mtd_info *mtd = nand_to_mtd(chip);
753
+	const struct nand_controller_ops *ops = chip->controller->ops;
1233
754
 	int ret;
1234
755
 
1235
-	if (!chip->setup_data_interface)
756
+	if (!nand_controller_can_setup_interface(chip))
1236
757
 		return 0;
1237
758
 
1238
759
 	/*
..
..
@@ -1249,8 +770,9 @@
1249
770
 	 * timings to timing mode 0.
1250
771
 	 */
1251
772
 
1252
-	onfi_fill_data_interface(chip, NAND_SDR_IFACE, 0);
1253
-	ret = chip->setup_data_interface(mtd, chipnr, &chip->data_interface);
773
+	chip->current_interface_config = nand_get_reset_interface_config();
774
+	ret = ops->setup_interface(chip, chipnr,
775
+				   chip->current_interface_config);
1254
776
 	if (ret)
1255
777
 		pr_err("Failed to configure data interface to SDR timing mode 0\n");
1256
778
 
..
..
@@ -1258,61 +780,71 @@
1258
780
 }
1259
781
 
1260
782
 /**
1261
- * nand_setup_data_interface - Setup the best data interface and timings
783
+ * nand_setup_interface - Setup the best data interface and timings
1262
784
  * @chip: The NAND chip
1263
785
  * @chipnr: Internal die id
1264
786
  *
1265
- * Find and configure the best data interface and NAND timings supported by
1266
- * the chip and the driver.
1267
- * First tries to retrieve supported timing modes from ONFI information,
1268
- * and if the NAND chip does not support ONFI, relies on the
1269
- * ->onfi_timing_mode_default specified in the nand_ids table.
787
+ * Configure what has been reported to be the best data interface and NAND
788
+ * timings supported by the chip and the driver.
1270
789
  *
1271
790
  * Returns 0 for success or negative error code otherwise.
1272
791
  */
1273
-static int nand_setup_data_interface(struct nand_chip *chip, int chipnr)
792
+static int nand_setup_interface(struct nand_chip *chip, int chipnr)
1274
793
 {
1275
-	struct mtd_info *mtd = nand_to_mtd(chip);
1276
-	u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = {
1277
-		chip->onfi_timing_mode_default,
1278
-	};
794
+	const struct nand_controller_ops *ops = chip->controller->ops;
795
+	u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = { };
1279
796
 	int ret;
1280
797
 
1281
-	if (!chip->setup_data_interface)
798
+	if (!nand_controller_can_setup_interface(chip))
1282
799
 		return 0;
800
+
801
+	/*
802
+	 * A nand_reset_interface() put both the NAND chip and the NAND
803
+	 * controller in timings mode 0. If the default mode for this chip is
804
+	 * also 0, no need to proceed to the change again. Plus, at probe time,
805
+	 * nand_setup_interface() uses ->set/get_features() which would
806
+	 * fail anyway as the parameter page is not available yet.
807
+	 */
808
+	if (!chip->best_interface_config)
809
+		return 0;
810
+
811
+	tmode_param[0] = chip->best_interface_config->timings.mode;
1283
812
 
1284
813
 	/* Change the mode on the chip side (if supported by the NAND chip) */
1285
814
 	if (nand_supports_set_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE)) {
1286
-		chip->select_chip(mtd, chipnr);
815
+		nand_select_target(chip, chipnr);
1287
816
 		ret = nand_set_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE,
1288
817
 					tmode_param);
1289
-		chip->select_chip(mtd, -1);
818
+		nand_deselect_target(chip);
1290
819
 		if (ret)
1291
820
 			return ret;
1292
821
 	}
1293
822
 
1294
823
 	/* Change the mode on the controller side */
1295
-	ret = chip->setup_data_interface(mtd, chipnr, &chip->data_interface);
824
+	ret = ops->setup_interface(chip, chipnr, chip->best_interface_config);
1296
825
 	if (ret)
1297
826
 		return ret;
1298
827
 
1299
828
 	/* Check the mode has been accepted by the chip, if supported */
1300
829
 	if (!nand_supports_get_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE))
1301
-		return 0;
830
+		goto update_interface_config;
1302
831
 
1303
832
 	memset(tmode_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
1304
-	chip->select_chip(mtd, chipnr);
833
+	nand_select_target(chip, chipnr);
1305
834
 	ret = nand_get_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE,
1306
835
 				tmode_param);
1307
-	chip->select_chip(mtd, -1);
836
+	nand_deselect_target(chip);
1308
837
 	if (ret)
1309
838
 		goto err_reset_chip;
1310
839
 
1311
-	if (tmode_param[0] != chip->onfi_timing_mode_default) {
840
+	if (tmode_param[0] != chip->best_interface_config->timings.mode) {
1312
841
 		pr_warn("timing mode %d not acknowledged by the NAND chip\n",
1313
-			chip->onfi_timing_mode_default);
842
+			chip->best_interface_config->timings.mode);
1314
843
 		goto err_reset_chip;
1315
844
 	}
845
+
846
+update_interface_config:
847
+	chip->current_interface_config = chip->best_interface_config;
1316
848
 
1317
849
 	return 0;
1318
850
 
..
..
@@ -1321,69 +853,99 @@
1321
853
 	 * Fallback to mode 0 if the chip explicitly did not ack the chosen
1322
854
 	 * timing mode.
1323
855
 	 */
1324
-	nand_reset_data_interface(chip, chipnr);
1325
-	chip->select_chip(mtd, chipnr);
856
+	nand_reset_interface(chip, chipnr);
857
+	nand_select_target(chip, chipnr);
1326
858
 	nand_reset_op(chip);
1327
-	chip->select_chip(mtd, -1);
859
+	nand_deselect_target(chip);
1328
860
 
1329
861
 	return ret;
1330
862
 }
1331
863
 
1332
864
 /**
1333
- * nand_init_data_interface - find the best data interface and timings
865
+ * nand_choose_best_sdr_timings - Pick up the best SDR timings that both the
866
+ *                                NAND controller and the NAND chip support
867
+ * @chip: the NAND chip
868
+ * @iface: the interface configuration (can eventually be updated)
869
+ * @spec_timings: specific timings, when not fitting the ONFI specification
870
+ *
871
+ * If specific timings are provided, use them. Otherwise, retrieve supported
872
+ * timing modes from ONFI information.
873
+ */
874
+int nand_choose_best_sdr_timings(struct nand_chip *chip,
875
+				 struct nand_interface_config *iface,
876
+				 struct nand_sdr_timings *spec_timings)
877
+{
878
+	const struct nand_controller_ops *ops = chip->controller->ops;
879
+	int best_mode = 0, mode, ret;
880
+
881
+	iface->type = NAND_SDR_IFACE;
882
+
883
+	if (spec_timings) {
884
+		iface->timings.sdr = *spec_timings;
885
+		iface->timings.mode = onfi_find_closest_sdr_mode(spec_timings);
886
+
887
+		/* Verify the controller supports the requested interface */
888
+		ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY,
889
+					   iface);
890
+		if (!ret) {
891
+			chip->best_interface_config = iface;
892
+			return ret;
893
+		}
894
+
895
+		/* Fallback to slower modes */
896
+		best_mode = iface->timings.mode;
897
+	} else if (chip->parameters.onfi) {
898
+		best_mode = fls(chip->parameters.onfi->async_timing_mode) - 1;
899
+	}
900
+
901
+	for (mode = best_mode; mode >= 0; mode--) {
902
+		onfi_fill_interface_config(chip, iface, NAND_SDR_IFACE, mode);
903
+
904
+		ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY,
905
+					   iface);
906
+		if (!ret)
907
+			break;
908
+	}
909
+
910
+	chip->best_interface_config = iface;
911
+
912
+	return 0;
913
+}
914
+
915
+/**
916
+ * nand_choose_interface_config - find the best data interface and timings
1334
917
  * @chip: The NAND chip
1335
918
  *
1336
919
  * Find the best data interface and NAND timings supported by the chip
1337
- * and the driver.
1338
- * First tries to retrieve supported timing modes from ONFI information,
1339
- * and if the NAND chip does not support ONFI, relies on the
1340
- * ->onfi_timing_mode_default specified in the nand_ids table. After this
1341
- * function nand_chip->data_interface is initialized with the best timing mode
1342
- * available.
920
+ * and the driver. Eventually let the NAND manufacturer driver propose his own
921
+ * set of timings.
922
+ *
923
+ * After this function nand_chip->interface_config is initialized with the best
924
+ * timing mode available.
1343
925
  *
1344
926
  * Returns 0 for success or negative error code otherwise.
1345
927
  */
1346
-static int nand_init_data_interface(struct nand_chip *chip)
928
+static int nand_choose_interface_config(struct nand_chip *chip)
1347
929
 {
1348
-	struct mtd_info *mtd = nand_to_mtd(chip);
1349
-	int modes, mode, ret;
930
+	struct nand_interface_config *iface;
931
+	int ret;
1350
932
 
1351
-	if (!chip->setup_data_interface)
933
+	if (!nand_controller_can_setup_interface(chip))
1352
934
 		return 0;
1353
935
 
1354
-	/*
1355
-	 * First try to identify the best timings from ONFI parameters and
1356
-	 * if the NAND does not support ONFI, fallback to the default ONFI
1357
-	 * timing mode.
1358
-	 */
1359
-	modes = onfi_get_async_timing_mode(chip);
1360
-	if (modes == ONFI_TIMING_MODE_UNKNOWN) {
1361
-		if (!chip->onfi_timing_mode_default)
1362
-			return 0;
936
+	iface = kzalloc(sizeof(*iface), GFP_KERNEL);
937
+	if (!iface)
938
+		return -ENOMEM;
1363
939
 
1364
-		modes = GENMASK(chip->onfi_timing_mode_default, 0);
1365
-	}
940
+	if (chip->ops.choose_interface_config)
941
+		ret = chip->ops.choose_interface_config(chip, iface);
942
+	else
943
+		ret = nand_choose_best_sdr_timings(chip, iface, NULL);
1366
944
 
945
+	if (ret)
946
+		kfree(iface);
1367
947
 
1368
-	for (mode = fls(modes) - 1; mode >= 0; mode--) {
1369
-		ret = onfi_fill_data_interface(chip, NAND_SDR_IFACE, mode);
1370
-		if (ret)
1371
-			continue;
1372
-
1373
-		/*
1374
-		 * Pass NAND_DATA_IFACE_CHECK_ONLY to only check if the
1375
-		 * controller supports the requested timings.
1376
-		 */
1377
-		ret = chip->setup_data_interface(mtd,
1378
-						 NAND_DATA_IFACE_CHECK_ONLY,
1379
-						 &chip->data_interface);
1380
-		if (!ret) {
1381
-			chip->onfi_timing_mode_default = mode;
1382
-			break;
1383
-		}
1384
-	}
1385
-
1386
-	return 0;
948
+	return ret;
1387
949
 }
1388
950
 
1389
951
 /**
..
..
@@ -1444,9 +1006,9 @@
1444
1006
 				     unsigned int offset_in_page, void *buf,
1445
1007
 				     unsigned int len)
1446
1008
 {
1447
-	struct mtd_info *mtd = nand_to_mtd(chip);
1448
1009
 	const struct nand_sdr_timings *sdr =
1449
-		nand_get_sdr_timings(&chip->data_interface);
1010
+		nand_get_sdr_timings(nand_get_interface_config(chip));
1011
+	struct mtd_info *mtd = nand_to_mtd(chip);
1450
1012
 	u8 addrs[4];
1451
1013
 	struct nand_op_instr instrs[] = {
1452
1014
 		NAND_OP_CMD(NAND_CMD_READ0, 0),
..
..
@@ -1455,7 +1017,7 @@
1455
1017
 				 PSEC_TO_NSEC(sdr->tRR_min)),
1456
1018
 		NAND_OP_DATA_IN(len, buf, 0),
1457
1019
 	};
1458
-	struct nand_operation op = NAND_OPERATION(instrs);
1020
+	struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1459
1021
 	int ret;
1460
1022
 
1461
1023
 	/* Drop the DATA_IN instruction if len is set to 0. */
..
..
@@ -1488,7 +1050,7 @@
1488
1050
 				     unsigned int len)
1489
1051
 {
1490
1052
 	const struct nand_sdr_timings *sdr =
1491
-		nand_get_sdr_timings(&chip->data_interface);
1053
+		nand_get_sdr_timings(nand_get_interface_config(chip));
1492
1054
 	u8 addrs[5];
1493
1055
 	struct nand_op_instr instrs[] = {
1494
1056
 		NAND_OP_CMD(NAND_CMD_READ0, 0),
..
..
@@ -1498,7 +1060,7 @@
1498
1060
 				 PSEC_TO_NSEC(sdr->tRR_min)),
1499
1061
 		NAND_OP_DATA_IN(len, buf, 0),
1500
1062
 	};
1501
-	struct nand_operation op = NAND_OPERATION(instrs);
1063
+	struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1502
1064
 	int ret;
1503
1065
 
1504
1066
 	/* Drop the DATA_IN instruction if len is set to 0. */
..
..
@@ -1544,7 +1106,7 @@
1544
1106
 	if (offset_in_page + len > mtd->writesize + mtd->oobsize)
1545
1107
 		return -EINVAL;
1546
1108
 
1547
-	if (chip->exec_op) {
1109
+	if (nand_has_exec_op(chip)) {
1548
1110
 		if (mtd->writesize > 512)
1549
1111
 			return nand_lp_exec_read_page_op(chip, page,
1550
1112
 							 offset_in_page, buf,
..
..
@@ -1554,9 +1116,9 @@
1554
1116
 						 buf, len);
1555
1117
 	}
1556
1118
 
1557
-	chip->cmdfunc(mtd, NAND_CMD_READ0, offset_in_page, page);
1119
+	chip->legacy.cmdfunc(chip, NAND_CMD_READ0, offset_in_page, page);
1558
1120
 	if (len)
1559
-		chip->read_buf(mtd, buf, len);
1121
+		chip->legacy.read_buf(chip, buf, len);
1560
1122
 
1561
1123
 	return 0;
1562
1124
 }
..
..
@@ -1574,19 +1136,18 @@
1574
1136
  *
1575
1137
  * Returns 0 on success, a negative error code otherwise.
1576
1138
  */
1577
-static int nand_read_param_page_op(struct nand_chip *chip, u8 page, void *buf,
1578
-				   unsigned int len)
1139
+int nand_read_param_page_op(struct nand_chip *chip, u8 page, void *buf,
1140
+			    unsigned int len)
1579
1141
 {
1580
-	struct mtd_info *mtd = nand_to_mtd(chip);
1581
1142
 	unsigned int i;
1582
1143
 	u8 *p = buf;
1583
1144
 
1584
1145
 	if (len && !buf)
1585
1146
 		return -EINVAL;
1586
1147
 
1587
-	if (chip->exec_op) {
1148
+	if (nand_has_exec_op(chip)) {
1588
1149
 		const struct nand_sdr_timings *sdr =
1589
-			nand_get_sdr_timings(&chip->data_interface);
1150
+			nand_get_sdr_timings(nand_get_interface_config(chip));
1590
1151
 		struct nand_op_instr instrs[] = {
1591
1152
 			NAND_OP_CMD(NAND_CMD_PARAM, 0),
1592
1153
 			NAND_OP_ADDR(1, &page, PSEC_TO_NSEC(sdr->tWB_max)),
..
..
@@ -1594,7 +1155,7 @@
1594
1155
 					 PSEC_TO_NSEC(sdr->tRR_min)),
1595
1156
 			NAND_OP_8BIT_DATA_IN(len, buf, 0),
1596
1157
 		};
1597
-		struct nand_operation op = NAND_OPERATION(instrs);
1158
+		struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1598
1159
 
1599
1160
 		/* Drop the DATA_IN instruction if len is set to 0. */
1600
1161
 		if (!len)
..
..
@@ -1603,9 +1164,9 @@
1603
1164
 		return nand_exec_op(chip, &op);
1604
1165
 	}
1605
1166
 
1606
-	chip->cmdfunc(mtd, NAND_CMD_PARAM, page, -1);
1167
+	chip->legacy.cmdfunc(chip, NAND_CMD_PARAM, page, -1);
1607
1168
 	for (i = 0; i < len; i++)
1608
-		p[i] = chip->read_byte(mtd);
1169
+		p[i] = chip->legacy.read_byte(chip);
1609
1170
 
1610
1171
 	return 0;
1611
1172
 }
..
..
@@ -1639,9 +1200,9 @@
1639
1200
 	if (mtd->writesize <= 512)
1640
1201
 		return -ENOTSUPP;
1641
1202
 
1642
-	if (chip->exec_op) {
1203
+	if (nand_has_exec_op(chip)) {
1643
1204
 		const struct nand_sdr_timings *sdr =
1644
-			nand_get_sdr_timings(&chip->data_interface);
1205
+			nand_get_sdr_timings(nand_get_interface_config(chip));
1645
1206
 		u8 addrs[2] = {};
1646
1207
 		struct nand_op_instr instrs[] = {
1647
1208
 			NAND_OP_CMD(NAND_CMD_RNDOUT, 0),
..
..
@@ -1650,7 +1211,7 @@
1650
1211
 				    PSEC_TO_NSEC(sdr->tCCS_min)),
1651
1212
 			NAND_OP_DATA_IN(len, buf, 0),
1652
1213
 		};
1653
-		struct nand_operation op = NAND_OPERATION(instrs);
1214
+		struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1654
1215
 		int ret;
1655
1216
 
1656
1217
 		ret = nand_fill_column_cycles(chip, addrs, offset_in_page);
..
..
@@ -1666,9 +1227,9 @@
1666
1227
 		return nand_exec_op(chip, &op);
1667
1228
 	}
1668
1229
 
1669
-	chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset_in_page, -1);
1230
+	chip->legacy.cmdfunc(chip, NAND_CMD_RNDOUT, offset_in_page, -1);
1670
1231
 	if (len)
1671
-		chip->read_buf(mtd, buf, len);
1232
+		chip->legacy.read_buf(chip, buf, len);
1672
1233
 
1673
1234
 	return 0;
1674
1235
 }
..
..
@@ -1698,14 +1259,14 @@
1698
1259
 	if (offset_in_oob + len > mtd->oobsize)
1699
1260
 		return -EINVAL;
1700
1261
 
1701
-	if (chip->exec_op)
1262
+	if (nand_has_exec_op(chip))
1702
1263
 		return nand_read_page_op(chip, page,
1703
1264
 					 mtd->writesize + offset_in_oob,
1704
1265
 					 buf, len);
1705
1266
 
1706
-	chip->cmdfunc(mtd, NAND_CMD_READOOB, offset_in_oob, page);
1267
+	chip->legacy.cmdfunc(chip, NAND_CMD_READOOB, offset_in_oob, page);
1707
1268
 	if (len)
1708
-		chip->read_buf(mtd, buf, len);
1269
+		chip->legacy.read_buf(chip, buf, len);
1709
1270
 
1710
1271
 	return 0;
1711
1272
 }
..
..
@@ -1715,9 +1276,9 @@
1715
1276
 				  unsigned int offset_in_page, const void *buf,
1716
1277
 				  unsigned int len, bool prog)
1717
1278
 {
1718
-	struct mtd_info *mtd = nand_to_mtd(chip);
1719
1279
 	const struct nand_sdr_timings *sdr =
1720
-		nand_get_sdr_timings(&chip->data_interface);
1280
+		nand_get_sdr_timings(nand_get_interface_config(chip));
1281
+	struct mtd_info *mtd = nand_to_mtd(chip);
1721
1282
 	u8 addrs[5] = {};
1722
1283
 	struct nand_op_instr instrs[] = {
1723
1284
 		/*
..
..
@@ -1732,7 +1293,7 @@
1732
1293
 		NAND_OP_CMD(NAND_CMD_PAGEPROG, PSEC_TO_NSEC(sdr->tWB_max)),
1733
1294
 		NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tPROG_max), 0),
1734
1295
 	};
1735
-	struct nand_operation op = NAND_OPERATION(instrs);
1296
+	struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1736
1297
 	int naddrs = nand_fill_column_cycles(chip, addrs, offset_in_page);
1737
1298
 	int ret;
1738
1299
 	u8 status;
..
..
@@ -1811,14 +1372,14 @@
1811
1372
 	if (offset_in_page + len > mtd->writesize + mtd->oobsize)
1812
1373
 		return -EINVAL;
1813
1374
 
1814
-	if (chip->exec_op)
1375
+	if (nand_has_exec_op(chip))
1815
1376
 		return nand_exec_prog_page_op(chip, page, offset_in_page, buf,
1816
1377
 					      len, false);
1817
1378
 
1818
-	chip->cmdfunc(mtd, NAND_CMD_SEQIN, offset_in_page, page);
1379
+	chip->legacy.cmdfunc(chip, NAND_CMD_SEQIN, offset_in_page, page);
1819
1380
 
1820
1381
 	if (buf)
1821
-		chip->write_buf(mtd, buf, len);
1382
+		chip->legacy.write_buf(chip, buf, len);
1822
1383
 
1823
1384
 	return 0;
1824
1385
 }
..
..
@@ -1835,19 +1396,18 @@
1835
1396
  */
1836
1397
 int nand_prog_page_end_op(struct nand_chip *chip)
1837
1398
 {
1838
-	struct mtd_info *mtd = nand_to_mtd(chip);
1839
1399
 	int ret;
1840
1400
 	u8 status;
1841
1401
 
1842
-	if (chip->exec_op) {
1402
+	if (nand_has_exec_op(chip)) {
1843
1403
 		const struct nand_sdr_timings *sdr =
1844
-			nand_get_sdr_timings(&chip->data_interface);
1404
+			nand_get_sdr_timings(nand_get_interface_config(chip));
1845
1405
 		struct nand_op_instr instrs[] = {
1846
1406
 			NAND_OP_CMD(NAND_CMD_PAGEPROG,
1847
1407
 				    PSEC_TO_NSEC(sdr->tWB_max)),
1848
1408
 			NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tPROG_max), 0),
1849
1409
 		};
1850
-		struct nand_operation op = NAND_OPERATION(instrs);
1410
+		struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1851
1411
 
1852
1412
 		ret = nand_exec_op(chip, &op);
1853
1413
 		if (ret)
..
..
@@ -1857,8 +1417,8 @@
1857
1417
 		if (ret)
1858
1418
 			return ret;
1859
1419
 	} else {
1860
-		chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1861
-		ret = chip->waitfunc(mtd, chip);
1420
+		chip->legacy.cmdfunc(chip, NAND_CMD_PAGEPROG, -1, -1);
1421
+		ret = chip->legacy.waitfunc(chip);
1862
1422
 		if (ret < 0)
1863
1423
 			return ret;
1864
1424
 
..
..
@@ -1898,14 +1458,15 @@
1898
1458
 	if (offset_in_page + len > mtd->writesize + mtd->oobsize)
1899
1459
 		return -EINVAL;
1900
1460
 
1901
-	if (chip->exec_op) {
1461
+	if (nand_has_exec_op(chip)) {
1902
1462
 		status = nand_exec_prog_page_op(chip, page, offset_in_page, buf,
1903
1463
 						len, true);
1904
1464
 	} else {
1905
-		chip->cmdfunc(mtd, NAND_CMD_SEQIN, offset_in_page, page);
1906
-		chip->write_buf(mtd, buf, len);
1907
-		chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1908
-		status = chip->waitfunc(mtd, chip);
1465
+		chip->legacy.cmdfunc(chip, NAND_CMD_SEQIN, offset_in_page,
1466
+				     page);
1467
+		chip->legacy.write_buf(chip, buf, len);
1468
+		chip->legacy.cmdfunc(chip, NAND_CMD_PAGEPROG, -1, -1);
1469
+		status = chip->legacy.waitfunc(chip);
1909
1470
 	}
1910
1471
 
1911
1472
 	if (status & NAND_STATUS_FAIL)
..
..
@@ -1945,16 +1506,16 @@
1945
1506
 	if (mtd->writesize <= 512)
1946
1507
 		return -ENOTSUPP;
1947
1508
 
1948
-	if (chip->exec_op) {
1509
+	if (nand_has_exec_op(chip)) {
1949
1510
 		const struct nand_sdr_timings *sdr =
1950
-			nand_get_sdr_timings(&chip->data_interface);
1511
+			nand_get_sdr_timings(nand_get_interface_config(chip));
1951
1512
 		u8 addrs[2];
1952
1513
 		struct nand_op_instr instrs[] = {
1953
1514
 			NAND_OP_CMD(NAND_CMD_RNDIN, 0),
1954
1515
 			NAND_OP_ADDR(2, addrs, PSEC_TO_NSEC(sdr->tCCS_min)),
1955
1516
 			NAND_OP_DATA_OUT(len, buf, 0),
1956
1517
 		};
1957
-		struct nand_operation op = NAND_OPERATION(instrs);
1518
+		struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1958
1519
 		int ret;
1959
1520
 
1960
1521
 		ret = nand_fill_column_cycles(chip, addrs, offset_in_page);
..
..
@@ -1970,9 +1531,9 @@
1970
1531
 		return nand_exec_op(chip, &op);
1971
1532
 	}
1972
1533
 
1973
-	chip->cmdfunc(mtd, NAND_CMD_RNDIN, offset_in_page, -1);
1534
+	chip->legacy.cmdfunc(chip, NAND_CMD_RNDIN, offset_in_page, -1);
1974
1535
 	if (len)
1975
-		chip->write_buf(mtd, buf, len);
1536
+		chip->legacy.write_buf(chip, buf, len);
1976
1537
 
1977
1538
 	return 0;
1978
1539
 }
..
..
@@ -1994,22 +1555,21 @@
1994
1555
 int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf,
1995
1556
 		   unsigned int len)
1996
1557
 {
1997
-	struct mtd_info *mtd = nand_to_mtd(chip);
1998
1558
 	unsigned int i;
1999
1559
 	u8 *id = buf;
2000
1560
 
2001
1561
 	if (len && !buf)
2002
1562
 		return -EINVAL;
2003
1563
 
2004
-	if (chip->exec_op) {
1564
+	if (nand_has_exec_op(chip)) {
2005
1565
 		const struct nand_sdr_timings *sdr =
2006
-			nand_get_sdr_timings(&chip->data_interface);
1566
+			nand_get_sdr_timings(nand_get_interface_config(chip));
2007
1567
 		struct nand_op_instr instrs[] = {
2008
1568
 			NAND_OP_CMD(NAND_CMD_READID, 0),
2009
1569
 			NAND_OP_ADDR(1, &addr, PSEC_TO_NSEC(sdr->tADL_min)),
2010
1570
 			NAND_OP_8BIT_DATA_IN(len, buf, 0),
2011
1571
 		};
2012
-		struct nand_operation op = NAND_OPERATION(instrs);
1572
+		struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
2013
1573
 
2014
1574
 		/* Drop the DATA_IN instruction if len is set to 0. */
2015
1575
 		if (!len)
..
..
@@ -2018,10 +1578,10 @@
2018
1578
 		return nand_exec_op(chip, &op);
2019
1579
 	}
2020
1580
 
2021
-	chip->cmdfunc(mtd, NAND_CMD_READID, addr, -1);
1581
+	chip->legacy.cmdfunc(chip, NAND_CMD_READID, addr, -1);
2022
1582
 
2023
1583
 	for (i = 0; i < len; i++)
2024
-		id[i] = chip->read_byte(mtd);
1584
+		id[i] = chip->legacy.read_byte(chip);
2025
1585
 
2026
1586
 	return 0;
2027
1587
 }
..
..
@@ -2040,17 +1600,15 @@
2040
1600
  */
2041
1601
 int nand_status_op(struct nand_chip *chip, u8 *status)
2042
1602
 {
2043
-	struct mtd_info *mtd = nand_to_mtd(chip);
2044
-
2045
-	if (chip->exec_op) {
1603
+	if (nand_has_exec_op(chip)) {
2046
1604
 		const struct nand_sdr_timings *sdr =
2047
-			nand_get_sdr_timings(&chip->data_interface);
1605
+			nand_get_sdr_timings(nand_get_interface_config(chip));
2048
1606
 		struct nand_op_instr instrs[] = {
2049
1607
 			NAND_OP_CMD(NAND_CMD_STATUS,
2050
1608
 				    PSEC_TO_NSEC(sdr->tADL_min)),
2051
1609
 			NAND_OP_8BIT_DATA_IN(1, status, 0),
2052
1610
 		};
2053
-		struct nand_operation op = NAND_OPERATION(instrs);
1611
+		struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
2054
1612
 
2055
1613
 		if (!status)
2056
1614
 			op.ninstrs--;
..
..
@@ -2058,9 +1616,9 @@
2058
1616
 		return nand_exec_op(chip, &op);
2059
1617
 	}
2060
1618
 
2061
-	chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1619
+	chip->legacy.cmdfunc(chip, NAND_CMD_STATUS, -1, -1);
2062
1620
 	if (status)
2063
-		*status = chip->read_byte(mtd);
1621
+		*status = chip->legacy.read_byte(chip);
2064
1622
 
2065
1623
 	return 0;
2066
1624
 }
..
..
@@ -2079,22 +1637,19 @@
2079
1637
  */
2080
1638
 int nand_exit_status_op(struct nand_chip *chip)
2081
1639
 {
2082
-	struct mtd_info *mtd = nand_to_mtd(chip);
2083
-
2084
-	if (chip->exec_op) {
1640
+	if (nand_has_exec_op(chip)) {
2085
1641
 		struct nand_op_instr instrs[] = {
2086
1642
 			NAND_OP_CMD(NAND_CMD_READ0, 0),
2087
1643
 		};
2088
-		struct nand_operation op = NAND_OPERATION(instrs);
1644
+		struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
2089
1645
 
2090
1646
 		return nand_exec_op(chip, &op);
2091
1647
 	}
2092
1648
 
2093
-	chip->cmdfunc(mtd, NAND_CMD_READ0, -1, -1);
1649
+	chip->legacy.cmdfunc(chip, NAND_CMD_READ0, -1, -1);
2094
1650
 
2095
1651
 	return 0;
2096
1652
 }
2097
-EXPORT_SYMBOL_GPL(nand_exit_status_op);
2098
1653
 
2099
1654
 /**
2100
1655
  * nand_erase_op - Do an erase operation
..
..
@@ -2109,15 +1664,14 @@
2109
1664
  */
2110
1665
 int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock)
2111
1666
 {
2112
-	struct mtd_info *mtd = nand_to_mtd(chip);
2113
1667
 	unsigned int page = eraseblock <<
2114
1668
 			    (chip->phys_erase_shift - chip->page_shift);
2115
1669
 	int ret;
2116
1670
 	u8 status;
2117
1671
 
2118
-	if (chip->exec_op) {
1672
+	if (nand_has_exec_op(chip)) {
2119
1673
 		const struct nand_sdr_timings *sdr =
2120
-			nand_get_sdr_timings(&chip->data_interface);
1674
+			nand_get_sdr_timings(nand_get_interface_config(chip));
2121
1675
 		u8 addrs[3] = {	page, page >> 8, page >> 16 };
2122
1676
 		struct nand_op_instr instrs[] = {
2123
1677
 			NAND_OP_CMD(NAND_CMD_ERASE1, 0),
..
..
@@ -2126,7 +1680,7 @@
2126
1680
 				    PSEC_TO_MSEC(sdr->tWB_max)),
2127
1681
 			NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tBERS_max), 0),
2128
1682
 		};
2129
-		struct nand_operation op = NAND_OPERATION(instrs);
1683
+		struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
2130
1684
 
2131
1685
 		if (chip->options & NAND_ROW_ADDR_3)
2132
1686
 			instrs[1].ctx.addr.naddrs++;
..
..
@@ -2139,10 +1693,10 @@
2139
1693
 		if (ret)
2140
1694
 			return ret;
2141
1695
 	} else {
2142
-		chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2143
-		chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1696
+		chip->legacy.cmdfunc(chip, NAND_CMD_ERASE1, -1, page);
1697
+		chip->legacy.cmdfunc(chip, NAND_CMD_ERASE2, -1, -1);
2144
1698
 
2145
-		ret = chip->waitfunc(mtd, chip);
1699
+		ret = chip->legacy.waitfunc(chip);
2146
1700
 		if (ret < 0)
2147
1701
 			return ret;
2148
1702
 
..
..
@@ -2171,13 +1725,12 @@
2171
1725
 static int nand_set_features_op(struct nand_chip *chip, u8 feature,
2172
1726
 				const void *data)
2173
1727
 {
2174
-	struct mtd_info *mtd = nand_to_mtd(chip);
2175
1728
 	const u8 *params = data;
2176
1729
 	int i, ret;
2177
1730
 
2178
-	if (chip->exec_op) {
1731
+	if (nand_has_exec_op(chip)) {
2179
1732
 		const struct nand_sdr_timings *sdr =
2180
-			nand_get_sdr_timings(&chip->data_interface);
1733
+			nand_get_sdr_timings(nand_get_interface_config(chip));
2181
1734
 		struct nand_op_instr instrs[] = {
2182
1735
 			NAND_OP_CMD(NAND_CMD_SET_FEATURES, 0),
2183
1736
 			NAND_OP_ADDR(1, &feature, PSEC_TO_NSEC(sdr->tADL_min)),
..
..
@@ -2185,16 +1738,16 @@
2185
1738
 					      PSEC_TO_NSEC(sdr->tWB_max)),
2186
1739
 			NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tFEAT_max), 0),
2187
1740
 		};
2188
-		struct nand_operation op = NAND_OPERATION(instrs);
1741
+		struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
2189
1742
 
2190
1743
 		return nand_exec_op(chip, &op);
2191
1744
 	}
2192
1745
 
2193
-	chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, feature, -1);
1746
+	chip->legacy.cmdfunc(chip, NAND_CMD_SET_FEATURES, feature, -1);
2194
1747
 	for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
2195
-		chip->write_byte(mtd, params[i]);
1748
+		chip->legacy.write_byte(chip, params[i]);
2196
1749
 
2197
-	ret = chip->waitfunc(mtd, chip);
1750
+	ret = chip->legacy.waitfunc(chip);
2198
1751
 	if (ret < 0)
2199
1752
 		return ret;
2200
1753
 
..
..
@@ -2219,13 +1772,12 @@
2219
1772
 static int nand_get_features_op(struct nand_chip *chip, u8 feature,
2220
1773
 				void *data)
2221
1774
 {
2222
-	struct mtd_info *mtd = nand_to_mtd(chip);
2223
1775
 	u8 *params = data;
2224
1776
 	int i;
2225
1777
 
2226
-	if (chip->exec_op) {
1778
+	if (nand_has_exec_op(chip)) {
2227
1779
 		const struct nand_sdr_timings *sdr =
2228
-			nand_get_sdr_timings(&chip->data_interface);
1780
+			nand_get_sdr_timings(nand_get_interface_config(chip));
2229
1781
 		struct nand_op_instr instrs[] = {
2230
1782
 			NAND_OP_CMD(NAND_CMD_GET_FEATURES, 0),
2231
1783
 			NAND_OP_ADDR(1, &feature, PSEC_TO_NSEC(sdr->tWB_max)),
..
..
@@ -2234,14 +1786,36 @@
2234
1786
 			NAND_OP_8BIT_DATA_IN(ONFI_SUBFEATURE_PARAM_LEN,
2235
1787
 					     data, 0),
2236
1788
 		};
2237
-		struct nand_operation op = NAND_OPERATION(instrs);
1789
+		struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
2238
1790
 
2239
1791
 		return nand_exec_op(chip, &op);
2240
1792
 	}
2241
1793
 
2242
-	chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, feature, -1);
1794
+	chip->legacy.cmdfunc(chip, NAND_CMD_GET_FEATURES, feature, -1);
2243
1795
 	for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
2244
-		params[i] = chip->read_byte(mtd);
1796
+		params[i] = chip->legacy.read_byte(chip);
1797
+
1798
+	return 0;
1799
+}
1800
+
1801
+static int nand_wait_rdy_op(struct nand_chip *chip, unsigned int timeout_ms,
1802
+			    unsigned int delay_ns)
1803
+{
1804
+	if (nand_has_exec_op(chip)) {
1805
+		struct nand_op_instr instrs[] = {
1806
+			NAND_OP_WAIT_RDY(PSEC_TO_MSEC(timeout_ms),
1807
+					 PSEC_TO_NSEC(delay_ns)),
1808
+		};
1809
+		struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1810
+
1811
+		return nand_exec_op(chip, &op);
1812
+	}
1813
+
1814
+	/* Apply delay or wait for ready/busy pin */
1815
+	if (!chip->legacy.dev_ready)
1816
+		udelay(chip->legacy.chip_delay);
1817
+	else
1818
+		nand_wait_ready(chip);
2245
1819
 
2246
1820
 	return 0;
2247
1821
 }
..
..
@@ -2258,21 +1832,19 @@
2258
1832
  */
2259
1833
 int nand_reset_op(struct nand_chip *chip)
2260
1834
 {
2261
-	struct mtd_info *mtd = nand_to_mtd(chip);
2262
-
2263
-	if (chip->exec_op) {
1835
+	if (nand_has_exec_op(chip)) {
2264
1836
 		const struct nand_sdr_timings *sdr =
2265
-			nand_get_sdr_timings(&chip->data_interface);
1837
+			nand_get_sdr_timings(nand_get_interface_config(chip));
2266
1838
 		struct nand_op_instr instrs[] = {
2267
1839
 			NAND_OP_CMD(NAND_CMD_RESET, PSEC_TO_NSEC(sdr->tWB_max)),
2268
1840
 			NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tRST_max), 0),
2269
1841
 		};
2270
-		struct nand_operation op = NAND_OPERATION(instrs);
1842
+		struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
2271
1843
 
2272
1844
 		return nand_exec_op(chip, &op);
2273
1845
 	}
2274
1846
 
2275
-	chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1847
+	chip->legacy.cmdfunc(chip, NAND_CMD_RESET, -1, -1);
2276
1848
 
2277
1849
 	return 0;
2278
1850
 }
..
..
@@ -2284,6 +1856,8 @@
2284
1856
  * @buf: buffer used to store the data
2285
1857
  * @len: length of the buffer
2286
1858
  * @force_8bit: force 8-bit bus access
1859
+ * @check_only: do not actually run the command, only checks if the
1860
+ *              controller driver supports it
2287
1861
  *
2288
1862
  * This function does a raw data read on the bus. Usually used after launching
2289
1863
  * another NAND operation like nand_read_page_op().
..
..
@@ -2292,32 +1866,36 @@
2292
1866
  * Returns 0 on success, a negative error code otherwise.
2293
1867
  */
2294
1868
 int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len,
2295
-		      bool force_8bit)
1869
+		      bool force_8bit, bool check_only)
2296
1870
 {
2297
-	struct mtd_info *mtd = nand_to_mtd(chip);
2298
-
2299
1871
 	if (!len || !buf)
2300
1872
 		return -EINVAL;
2301
1873
 
2302
-	if (chip->exec_op) {
1874
+	if (nand_has_exec_op(chip)) {
2303
1875
 		struct nand_op_instr instrs[] = {
2304
1876
 			NAND_OP_DATA_IN(len, buf, 0),
2305
1877
 		};
2306
-		struct nand_operation op = NAND_OPERATION(instrs);
1878
+		struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
2307
1879
 
2308
1880
 		instrs[0].ctx.data.force_8bit = force_8bit;
2309
1881
 
1882
+		if (check_only)
1883
+			return nand_check_op(chip, &op);
1884
+
2310
1885
 		return nand_exec_op(chip, &op);
2311
1886
 	}
1887
+
1888
+	if (check_only)
1889
+		return 0;
2312
1890
 
2313
1891
 	if (force_8bit) {
2314
1892
 		u8 *p = buf;
2315
1893
 		unsigned int i;
2316
1894
 
2317
1895
 		for (i = 0; i < len; i++)
2318
-			p[i] = chip->read_byte(mtd);
1896
+			p[i] = chip->legacy.read_byte(chip);
2319
1897
 	} else {
2320
-		chip->read_buf(mtd, buf, len);
1898
+		chip->legacy.read_buf(chip, buf, len);
2321
1899
 	}
2322
1900
 
2323
1901
 	return 0;
..
..
@@ -2340,16 +1918,14 @@
2340
1918
 int nand_write_data_op(struct nand_chip *chip, const void *buf,
2341
1919
 		       unsigned int len, bool force_8bit)
2342
1920
 {
2343
-	struct mtd_info *mtd = nand_to_mtd(chip);
2344
-
2345
1921
 	if (!len || !buf)
2346
1922
 		return -EINVAL;
2347
1923
 
2348
-	if (chip->exec_op) {
1924
+	if (nand_has_exec_op(chip)) {
2349
1925
 		struct nand_op_instr instrs[] = {
2350
1926
 			NAND_OP_DATA_OUT(len, buf, 0),
2351
1927
 		};
2352
-		struct nand_operation op = NAND_OPERATION(instrs);
1928
+		struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
2353
1929
 
2354
1930
 		instrs[0].ctx.data.force_8bit = force_8bit;
2355
1931
 
..
..
@@ -2361,9 +1937,9 @@
2361
1937
 		unsigned int i;
2362
1938
 
2363
1939
 		for (i = 0; i < len; i++)
2364
-			chip->write_byte(mtd, p[i]);
1940
+			chip->legacy.write_byte(chip, p[i]);
2365
1941
 	} else {
2366
-		chip->write_buf(mtd, buf, len);
1942
+		chip->legacy.write_buf(chip, buf, len);
2367
1943
 	}
2368
1944
 
2369
1945
 	return 0;
..
..
@@ -2532,7 +2108,7 @@
2532
2108
 	char *prefix = "      ";
2533
2109
 	unsigned int i;
2534
2110
 
2535
-	pr_debug("executing subop:\n");
2111
+	pr_debug("executing subop (CS%d):\n", ctx->subop.cs);
2536
2112
 
2537
2113
 	for (i = 0; i < ctx->ninstrs; i++) {
2538
2114
 		instr = &ctx->instrs[i];
..
..
@@ -2540,35 +2116,7 @@
2540
2116
 		if (instr == &ctx->subop.instrs[0])
2541
2117
 			prefix = "    ->";
2542
2118
 
2543
-		switch (instr->type) {
2544
-		case NAND_OP_CMD_INSTR:
2545
-			pr_debug("%sCMD      [0x%02x]\n", prefix,
2546
-				 instr->ctx.cmd.opcode);
2547
-			break;
2548
-		case NAND_OP_ADDR_INSTR:
2549
-			pr_debug("%sADDR     [%d cyc: %*ph]\n", prefix,
2550
-				 instr->ctx.addr.naddrs,
2551
-				 instr->ctx.addr.naddrs < 64 ?
2552
-				 instr->ctx.addr.naddrs : 64,
2553
-				 instr->ctx.addr.addrs);
2554
-			break;
2555
-		case NAND_OP_DATA_IN_INSTR:
2556
-			pr_debug("%sDATA_IN  [%d B%s]\n", prefix,
2557
-				 instr->ctx.data.len,
2558
-				 instr->ctx.data.force_8bit ?
2559
-				 ", force 8-bit" : "");
2560
-			break;
2561
-		case NAND_OP_DATA_OUT_INSTR:
2562
-			pr_debug("%sDATA_OUT [%d B%s]\n", prefix,
2563
-				 instr->ctx.data.len,
2564
-				 instr->ctx.data.force_8bit ?
2565
-				 ", force 8-bit" : "");
2566
-			break;
2567
-		case NAND_OP_WAITRDY_INSTR:
2568
-			pr_debug("%sWAITRDY  [max %d ms]\n", prefix,
2569
-				 instr->ctx.waitrdy.timeout_ms);
2570
-			break;
2571
-		}
2119
+		nand_op_trace(prefix, instr);
2572
2120
 
2573
2121
 		if (instr == &ctx->subop.instrs[ctx->subop.ninstrs - 1])
2574
2122
 			prefix = "      ";
..
..
@@ -2580,6 +2128,22 @@
2580
2128
 	/* NOP */
2581
2129
 }
2582
2130
 #endif
2131
+
2132
+static int nand_op_parser_cmp_ctx(const struct nand_op_parser_ctx *a,
2133
+				  const struct nand_op_parser_ctx *b)
2134
+{
2135
+	if (a->subop.ninstrs < b->subop.ninstrs)
2136
+		return -1;
2137
+	else if (a->subop.ninstrs > b->subop.ninstrs)
2138
+		return 1;
2139
+
2140
+	if (a->subop.last_instr_end_off < b->subop.last_instr_end_off)
2141
+		return -1;
2142
+	else if (a->subop.last_instr_end_off > b->subop.last_instr_end_off)
2143
+		return 1;
2144
+
2145
+	return 0;
2146
+}
2583
2147
 
2584
2148
 /**
2585
2149
  * nand_op_parser_exec_op - exec_op parser
..
..
@@ -2608,6 +2172,7 @@
2608
2172
 			   const struct nand_operation *op, bool check_only)
2609
2173
 {
2610
2174
 	struct nand_op_parser_ctx ctx = {
2175
+		.subop.cs = op->cs,
2611
2176
 		.subop.instrs = op->instrs,
2612
2177
 		.instrs = op->instrs,
2613
2178
 		.ninstrs = op->ninstrs,
..
..
@@ -2615,30 +2180,38 @@
2615
2180
 	unsigned int i;
2616
2181
 
2617
2182
 	while (ctx.subop.instrs < op->instrs + op->ninstrs) {
2618
-		int ret;
2183
+		const struct nand_op_parser_pattern *pattern;
2184
+		struct nand_op_parser_ctx best_ctx;
2185
+		int ret, best_pattern = -1;
2619
2186
 
2620
2187
 		for (i = 0; i < parser->npatterns; i++) {
2621
-			const struct nand_op_parser_pattern *pattern;
2188
+			struct nand_op_parser_ctx test_ctx = ctx;
2622
2189
 
2623
2190
 			pattern = &parser->patterns[i];
2624
-			if (!nand_op_parser_match_pat(pattern, &ctx))
2191
+			if (!nand_op_parser_match_pat(pattern, &test_ctx))
2625
2192
 				continue;
2626
2193
 
2627
-			nand_op_parser_trace(&ctx);
2194
+			if (best_pattern >= 0 &&
2195
+			    nand_op_parser_cmp_ctx(&test_ctx, &best_ctx) <= 0)
2196
+				continue;
2628
2197
 
2629
-			if (check_only)
2630
-				break;
2198
+			best_pattern = i;
2199
+			best_ctx = test_ctx;
2200
+		}
2631
2201
 
2202
+		if (best_pattern < 0) {
2203
+			pr_debug("->exec_op() parser: pattern not found!\n");
2204
+			return -ENOTSUPP;
2205
+		}
2206
+
2207
+		ctx = best_ctx;
2208
+		nand_op_parser_trace(&ctx);
2209
+
2210
+		if (!check_only) {
2211
+			pattern = &parser->patterns[best_pattern];
2632
2212
 			ret = pattern->exec(chip, &ctx.subop);
2633
2213
 			if (ret)
2634
2214
 				return ret;
2635
-
2636
-			break;
2637
-		}
2638
-
2639
-		if (i == parser->npatterns) {
2640
-			pr_debug("->exec_op() parser: pattern not found!\n");
2641
-			return -ENOTSUPP;
2642
2215
 		}
2643
2216
 
2644
2217
 		/*
..
..
@@ -2791,49 +2364,79 @@
2791
2364
  * @chipnr: Internal die id
2792
2365
  *
2793
2366
  * Save the timings data structure, then apply SDR timings mode 0 (see
2794
- * nand_reset_data_interface for details), do the reset operation, and
2795
- * apply back the previous timings.
2367
+ * nand_reset_interface for details), do the reset operation, and apply
2368
+ * back the previous timings.
2796
2369
  *
2797
2370
  * Returns 0 on success, a negative error code otherwise.
2798
2371
  */
2799
2372
 int nand_reset(struct nand_chip *chip, int chipnr)
2800
2373
 {
2801
-	struct mtd_info *mtd = nand_to_mtd(chip);
2802
-	struct nand_data_interface saved_data_intf = chip->data_interface;
2803
2374
 	int ret;
2804
2375
 
2805
-	ret = nand_reset_data_interface(chip, chipnr);
2376
+	ret = nand_reset_interface(chip, chipnr);
2806
2377
 	if (ret)
2807
2378
 		return ret;
2808
2379
 
2809
2380
 	/*
2810
2381
 	 * The CS line has to be released before we can apply the new NAND
2811
-	 * interface settings, hence this weird ->select_chip() dance.
2382
+	 * interface settings, hence this weird nand_select_target()
2383
+	 * nand_deselect_target() dance.
2812
2384
 	 */
2813
-	chip->select_chip(mtd, chipnr);
2385
+	nand_select_target(chip, chipnr);
2814
2386
 	ret = nand_reset_op(chip);
2815
-	chip->select_chip(mtd, -1);
2387
+	nand_deselect_target(chip);
2816
2388
 	if (ret)
2817
2389
 		return ret;
2818
2390
 
2819
-	/*
2820
-	 * A nand_reset_data_interface() put both the NAND chip and the NAND
2821
-	 * controller in timings mode 0. If the default mode for this chip is
2822
-	 * also 0, no need to proceed to the change again. Plus, at probe time,
2823
-	 * nand_setup_data_interface() uses ->set/get_features() which would
2824
-	 * fail anyway as the parameter page is not available yet.
2825
-	 */
2826
-	if (!chip->onfi_timing_mode_default)
2827
-		return 0;
2828
-
2829
-	chip->data_interface = saved_data_intf;
2830
-	ret = nand_setup_data_interface(chip, chipnr);
2391
+	ret = nand_setup_interface(chip, chipnr);
2831
2392
 	if (ret)
2832
2393
 		return ret;
2833
2394
 
2834
2395
 	return 0;
2835
2396
 }
2836
2397
 EXPORT_SYMBOL_GPL(nand_reset);
2398
+
2399
+/**
2400
+ * nand_get_features - wrapper to perform a GET_FEATURE
2401
+ * @chip: NAND chip info structure
2402
+ * @addr: feature address
2403
+ * @subfeature_param: the subfeature parameters, a four bytes array
2404
+ *
2405
+ * Returns 0 for success, a negative error otherwise. Returns -ENOTSUPP if the
2406
+ * operation cannot be handled.
2407
+ */
2408
+int nand_get_features(struct nand_chip *chip, int addr,
2409
+		      u8 *subfeature_param)
2410
+{
2411
+	if (!nand_supports_get_features(chip, addr))
2412
+		return -ENOTSUPP;
2413
+
2414
+	if (chip->legacy.get_features)
2415
+		return chip->legacy.get_features(chip, addr, subfeature_param);
2416
+
2417
+	return nand_get_features_op(chip, addr, subfeature_param);
2418
+}
2419
+
2420
+/**
2421
+ * nand_set_features - wrapper to perform a SET_FEATURE
2422
+ * @chip: NAND chip info structure
2423
+ * @addr: feature address
2424
+ * @subfeature_param: the subfeature parameters, a four bytes array
2425
+ *
2426
+ * Returns 0 for success, a negative error otherwise. Returns -ENOTSUPP if the
2427
+ * operation cannot be handled.
2428
+ */
2429
+int nand_set_features(struct nand_chip *chip, int addr,
2430
+		      u8 *subfeature_param)
2431
+{
2432
+	if (!nand_supports_set_features(chip, addr))
2433
+		return -ENOTSUPP;
2434
+
2435
+	if (chip->legacy.set_features)
2436
+		return chip->legacy.set_features(chip, addr, subfeature_param);
2437
+
2438
+	return nand_set_features_op(chip, addr, subfeature_param);
2439
+}
2837
2440
 
2838
2441
 /**
2839
2442
  * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
..
..
@@ -2968,7 +2571,6 @@
2968
2571
 
2969
2572
 /**
2970
2573
  * nand_read_page_raw_notsupp - dummy read raw page function
2971
- * @mtd: mtd info structure
2972
2574
  * @chip: nand chip info structure
2973
2575
  * @buf: buffer to store read data
2974
2576
  * @oob_required: caller requires OOB data read to chip->oob_poi
..
..
@@ -2976,16 +2578,14 @@
2976
2578
  *
2977
2579
  * Returns -ENOTSUPP unconditionally.
2978
2580
  */
2979
-int nand_read_page_raw_notsupp(struct mtd_info *mtd, struct nand_chip *chip,
2980
-			       u8 *buf, int oob_required, int page)
2581
+int nand_read_page_raw_notsupp(struct nand_chip *chip, u8 *buf,
2582
+			       int oob_required, int page)
2981
2583
 {
2982
2584
 	return -ENOTSUPP;
2983
2585
 }
2984
-EXPORT_SYMBOL(nand_read_page_raw_notsupp);
2985
2586
 
2986
2587
 /**
2987
2588
  * nand_read_page_raw - [INTERN] read raw page data without ecc
2988
- * @mtd: mtd info structure
2989
2589
  * @chip: nand chip info structure
2990
2590
  * @buf: buffer to store read data
2991
2591
  * @oob_required: caller requires OOB data read to chip->oob_poi
..
..
@@ -2993,9 +2593,10 @@
2993
2593
  *
2994
2594
  * Not for syndrome calculating ECC controllers, which use a special oob layout.
2995
2595
  */
2996
-int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
2997
-		       uint8_t *buf, int oob_required, int page)
2596
+int nand_read_page_raw(struct nand_chip *chip, uint8_t *buf, int oob_required,
2597
+		       int page)
2998
2598
 {
2599
+	struct mtd_info *mtd = nand_to_mtd(chip);
2999
2600
 	int ret;
3000
2601
 
3001
2602
 	ret = nand_read_page_op(chip, page, 0, buf, mtd->writesize);
..
..
@@ -3004,7 +2605,7 @@
3004
2605
 
3005
2606
 	if (oob_required) {
3006
2607
 		ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize,
3007
-					false);
2608
+					false, false);
3008
2609
 		if (ret)
3009
2610
 			return ret;
3010
2611
 	}
..
..
@@ -3014,8 +2615,48 @@
3014
2615
 EXPORT_SYMBOL(nand_read_page_raw);
3015
2616
 
3016
2617
 /**
2618
+ * nand_monolithic_read_page_raw - Monolithic page read in raw mode
2619
+ * @chip: NAND chip info structure
2620
+ * @buf: buffer to store read data
2621
+ * @oob_required: caller requires OOB data read to chip->oob_poi
2622
+ * @page: page number to read
2623
+ *
2624
+ * This is a raw page read, ie. without any error detection/correction.
2625
+ * Monolithic means we are requesting all the relevant data (main plus
2626
+ * eventually OOB) to be loaded in the NAND cache and sent over the
2627
+ * bus (from the NAND chip to the NAND controller) in a single
2628
+ * operation. This is an alternative to nand_read_page_raw(), which
2629
+ * first reads the main data, and if the OOB data is requested too,
2630
+ * then reads more data on the bus.
2631
+ */
2632
+int nand_monolithic_read_page_raw(struct nand_chip *chip, u8 *buf,
2633
+				  int oob_required, int page)
2634
+{
2635
+	struct mtd_info *mtd = nand_to_mtd(chip);
2636
+	unsigned int size = mtd->writesize;
2637
+	u8 *read_buf = buf;
2638
+	int ret;
2639
+
2640
+	if (oob_required) {
2641
+		size += mtd->oobsize;
2642
+
2643
+		if (buf != chip->data_buf)
2644
+			read_buf = nand_get_data_buf(chip);
2645
+	}
2646
+
2647
+	ret = nand_read_page_op(chip, page, 0, read_buf, size);
2648
+	if (ret)
2649
+		return ret;
2650
+
2651
+	if (buf != chip->data_buf)
2652
+		memcpy(buf, read_buf, mtd->writesize);
2653
+
2654
+	return 0;
2655
+}
2656
+EXPORT_SYMBOL(nand_monolithic_read_page_raw);
2657
+
2658
+/**
3017
2659
  * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
3018
- * @mtd: mtd info structure
3019
2660
  * @chip: nand chip info structure
3020
2661
  * @buf: buffer to store read data
3021
2662
  * @oob_required: caller requires OOB data read to chip->oob_poi
..
..
@@ -3023,10 +2664,10 @@
3023
2664
  *
3024
2665
  * We need a special oob layout and handling even when OOB isn't used.
3025
2666
  */
3026
-static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
3027
-				       struct nand_chip *chip, uint8_t *buf,
2667
+static int nand_read_page_raw_syndrome(struct nand_chip *chip, uint8_t *buf,
3028
2668
 				       int oob_required, int page)
3029
2669
 {
2670
+	struct mtd_info *mtd = nand_to_mtd(chip);
3030
2671
 	int eccsize = chip->ecc.size;
3031
2672
 	int eccbytes = chip->ecc.bytes;
3032
2673
 	uint8_t *oob = chip->oob_poi;
..
..
@@ -3037,7 +2678,7 @@
3037
2678
 		return ret;
3038
2679
 
3039
2680
 	for (steps = chip->ecc.steps; steps > 0; steps--) {
3040
-		ret = nand_read_data_op(chip, buf, eccsize, false);
2681
+		ret = nand_read_data_op(chip, buf, eccsize, false, false);
3041
2682
 		if (ret)
3042
2683
 			return ret;
3043
2684
 
..
..
@@ -3045,14 +2686,14 @@
3045
2686
 
3046
2687
 		if (chip->ecc.prepad) {
3047
2688
 			ret = nand_read_data_op(chip, oob, chip->ecc.prepad,
3048
-						false);
2689
+						false, false);
3049
2690
 			if (ret)
3050
2691
 				return ret;
3051
2692
 
3052
2693
 			oob += chip->ecc.prepad;
3053
2694
 		}
3054
2695
 
3055
-		ret = nand_read_data_op(chip, oob, eccbytes, false);
2696
+		ret = nand_read_data_op(chip, oob, eccbytes, false, false);
3056
2697
 		if (ret)
3057
2698
 			return ret;
3058
2699
 
..
..
@@ -3060,7 +2701,7 @@
3060
2701
 
3061
2702
 		if (chip->ecc.postpad) {
3062
2703
 			ret = nand_read_data_op(chip, oob, chip->ecc.postpad,
3063
-						false);
2704
+						false, false);
3064
2705
 			if (ret)
3065
2706
 				return ret;
3066
2707
 
..
..
@@ -3070,7 +2711,7 @@
3070
2711
 
3071
2712
 	size = mtd->oobsize - (oob - chip->oob_poi);
3072
2713
 	if (size) {
3073
-		ret = nand_read_data_op(chip, oob, size, false);
2714
+		ret = nand_read_data_op(chip, oob, size, false, false);
3074
2715
 		if (ret)
3075
2716
 			return ret;
3076
2717
 	}
..
..
@@ -3080,15 +2721,15 @@
3080
2721
 
3081
2722
 /**
3082
2723
  * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
3083
- * @mtd: mtd info structure
3084
2724
  * @chip: nand chip info structure
3085
2725
  * @buf: buffer to store read data
3086
2726
  * @oob_required: caller requires OOB data read to chip->oob_poi
3087
2727
  * @page: page number to read
3088
2728
  */
3089
-static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
3090
-				uint8_t *buf, int oob_required, int page)
2729
+static int nand_read_page_swecc(struct nand_chip *chip, uint8_t *buf,
2730
+				int oob_required, int page)
3091
2731
 {
2732
+	struct mtd_info *mtd = nand_to_mtd(chip);
3092
2733
 	int i, eccsize = chip->ecc.size, ret;
3093
2734
 	int eccbytes = chip->ecc.bytes;
3094
2735
 	int eccsteps = chip->ecc.steps;
..
..
@@ -3097,10 +2738,10 @@
3097
2738
 	uint8_t *ecc_code = chip->ecc.code_buf;
3098
2739
 	unsigned int max_bitflips = 0;
3099
2740
 
3100
-	chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
2741
+	chip->ecc.read_page_raw(chip, buf, 1, page);
3101
2742
 
3102
2743
 	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
3103
-		chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2744
+		chip->ecc.calculate(chip, p, &ecc_calc[i]);
3104
2745
 
3105
2746
 	ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
3106
2747
 					 chip->ecc.total);
..
..
@@ -3113,7 +2754,7 @@
3113
2754
 	for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
3114
2755
 		int stat;
3115
2756
 
3116
-		stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
2757
+		stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]);
3117
2758
 		if (stat < 0) {
3118
2759
 			mtd->ecc_stats.failed++;
3119
2760
 		} else {
..
..
@@ -3126,17 +2767,16 @@
3126
2767
 
3127
2768
 /**
3128
2769
  * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
3129
- * @mtd: mtd info structure
3130
2770
  * @chip: nand chip info structure
3131
2771
  * @data_offs: offset of requested data within the page
3132
2772
  * @readlen: data length
3133
2773
  * @bufpoi: buffer to store read data
3134
2774
  * @page: page number to read
3135
2775
  */
3136
-static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
3137
-			uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi,
3138
-			int page)
2776
+static int nand_read_subpage(struct nand_chip *chip, uint32_t data_offs,
2777
+			     uint32_t readlen, uint8_t *bufpoi, int page)
3139
2778
 {
2779
+	struct mtd_info *mtd = nand_to_mtd(chip);
3140
2780
 	int start_step, end_step, num_steps, ret;
3141
2781
 	uint8_t *p;
3142
2782
 	int data_col_addr, i, gaps = 0;
..
..
@@ -3165,7 +2805,7 @@
3165
2805
 
3166
2806
 	/* Calculate ECC */
3167
2807
 	for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
3168
-		chip->ecc.calculate(mtd, p, &chip->ecc.calc_buf[i]);
2808
+		chip->ecc.calculate(chip, p, &chip->ecc.calc_buf[i]);
3169
2809
 
3170
2810
 	/*
3171
2811
 	 * The performance is faster if we position offsets according to
..
..
@@ -3214,7 +2854,7 @@
3214
2854
 	for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
3215
2855
 		int stat;
3216
2856
 
3217
-		stat = chip->ecc.correct(mtd, p, &chip->ecc.code_buf[i],
2857
+		stat = chip->ecc.correct(chip, p, &chip->ecc.code_buf[i],
3218
2858
 					 &chip->ecc.calc_buf[i]);
3219
2859
 		if (stat == -EBADMSG &&
3220
2860
 		    (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
..
..
@@ -3238,7 +2878,6 @@
3238
2878
 
3239
2879
 /**
3240
2880
  * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
3241
- * @mtd: mtd info structure
3242
2881
  * @chip: nand chip info structure
3243
2882
  * @buf: buffer to store read data
3244
2883
  * @oob_required: caller requires OOB data read to chip->oob_poi
..
..
@@ -3246,9 +2885,10 @@
3246
2885
  *
3247
2886
  * Not for syndrome calculating ECC controllers which need a special oob layout.
3248
2887
  */
3249
-static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
3250
-				uint8_t *buf, int oob_required, int page)
2888
+static int nand_read_page_hwecc(struct nand_chip *chip, uint8_t *buf,
2889
+				int oob_required, int page)
3251
2890
 {
2891
+	struct mtd_info *mtd = nand_to_mtd(chip);
3252
2892
 	int i, eccsize = chip->ecc.size, ret;
3253
2893
 	int eccbytes = chip->ecc.bytes;
3254
2894
 	int eccsteps = chip->ecc.steps;
..
..
@@ -3262,16 +2902,17 @@
3262
2902
 		return ret;
3263
2903
 
3264
2904
 	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
3265
-		chip->ecc.hwctl(mtd, NAND_ECC_READ);
2905
+		chip->ecc.hwctl(chip, NAND_ECC_READ);
3266
2906
 
3267
-		ret = nand_read_data_op(chip, p, eccsize, false);
2907
+		ret = nand_read_data_op(chip, p, eccsize, false, false);
3268
2908
 		if (ret)
3269
2909
 			return ret;
3270
2910
 
3271
-		chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2911
+		chip->ecc.calculate(chip, p, &ecc_calc[i]);
3272
2912
 	}
3273
2913
 
3274
-	ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, false);
2914
+	ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, false,
2915
+				false);
3275
2916
 	if (ret)
3276
2917
 		return ret;
3277
2918
 
..
..
@@ -3286,77 +2927,7 @@
3286
2927
 	for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
3287
2928
 		int stat;
3288
2929
 
3289
-		stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
3290
-		if (stat == -EBADMSG &&
3291
-		    (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
3292
-			/* check for empty pages with bitflips */
3293
-			stat = nand_check_erased_ecc_chunk(p, eccsize,
3294
-						&ecc_code[i], eccbytes,
3295
-						NULL, 0,
3296
-						chip->ecc.strength);
3297
-		}
3298
-
3299
-		if (stat < 0) {
3300
-			mtd->ecc_stats.failed++;
3301
-		} else {
3302
-			mtd->ecc_stats.corrected += stat;
3303
-			max_bitflips = max_t(unsigned int, max_bitflips, stat);
3304
-		}
3305
-	}
3306
-	return max_bitflips;
3307
-}
3308
-
3309
-/**
3310
- * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
3311
- * @mtd: mtd info structure
3312
- * @chip: nand chip info structure
3313
- * @buf: buffer to store read data
3314
- * @oob_required: caller requires OOB data read to chip->oob_poi
3315
- * @page: page number to read
3316
- *
3317
- * Hardware ECC for large page chips, require OOB to be read first. For this
3318
- * ECC mode, the write_page method is re-used from ECC_HW. These methods
3319
- * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
3320
- * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
3321
- * the data area, by overwriting the NAND manufacturer bad block markings.
3322
- */
3323
-static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
3324
-	struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
3325
-{
3326
-	int i, eccsize = chip->ecc.size, ret;
3327
-	int eccbytes = chip->ecc.bytes;
3328
-	int eccsteps = chip->ecc.steps;
3329
-	uint8_t *p = buf;
3330
-	uint8_t *ecc_code = chip->ecc.code_buf;
3331
-	uint8_t *ecc_calc = chip->ecc.calc_buf;
3332
-	unsigned int max_bitflips = 0;
3333
-
3334
-	/* Read the OOB area first */
3335
-	ret = nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
3336
-	if (ret)
3337
-		return ret;
3338
-
3339
-	ret = nand_read_page_op(chip, page, 0, NULL, 0);
3340
-	if (ret)
3341
-		return ret;
3342
-
3343
-	ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
3344
-					 chip->ecc.total);
3345
-	if (ret)
3346
-		return ret;
3347
-
3348
-	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
3349
-		int stat;
3350
-
3351
-		chip->ecc.hwctl(mtd, NAND_ECC_READ);
3352
-
3353
-		ret = nand_read_data_op(chip, p, eccsize, false);
3354
-		if (ret)
3355
-			return ret;
3356
-
3357
-		chip->ecc.calculate(mtd, p, &ecc_calc[i]);
3358
-
3359
-		stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
2930
+		stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]);
3360
2931
 		if (stat == -EBADMSG &&
3361
2932
 		    (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
3362
2933
 			/* check for empty pages with bitflips */
..
..
@@ -3378,7 +2949,6 @@
3378
2949
 
3379
2950
 /**
3380
2951
  * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
3381
- * @mtd: mtd info structure
3382
2952
  * @chip: nand chip info structure
3383
2953
  * @buf: buffer to store read data
3384
2954
  * @oob_required: caller requires OOB data read to chip->oob_poi
..
..
@@ -3387,9 +2957,10 @@
3387
2957
  * The hw generator calculates the error syndrome automatically. Therefore we
3388
2958
  * need a special oob layout and handling.
3389
2959
  */
3390
-static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
3391
-				   uint8_t *buf, int oob_required, int page)
2960
+static int nand_read_page_syndrome(struct nand_chip *chip, uint8_t *buf,
2961
+				   int oob_required, int page)
3392
2962
 {
2963
+	struct mtd_info *mtd = nand_to_mtd(chip);
3393
2964
 	int ret, i, eccsize = chip->ecc.size;
3394
2965
 	int eccbytes = chip->ecc.bytes;
3395
2966
 	int eccsteps = chip->ecc.steps;
..
..
@@ -3405,34 +2976,34 @@
3405
2976
 	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
3406
2977
 		int stat;
3407
2978
 
3408
-		chip->ecc.hwctl(mtd, NAND_ECC_READ);
2979
+		chip->ecc.hwctl(chip, NAND_ECC_READ);
3409
2980
 
3410
-		ret = nand_read_data_op(chip, p, eccsize, false);
2981
+		ret = nand_read_data_op(chip, p, eccsize, false, false);
3411
2982
 		if (ret)
3412
2983
 			return ret;
3413
2984
 
3414
2985
 		if (chip->ecc.prepad) {
3415
2986
 			ret = nand_read_data_op(chip, oob, chip->ecc.prepad,
3416
-						false);
2987
+						false, false);
3417
2988
 			if (ret)
3418
2989
 				return ret;
3419
2990
 
3420
2991
 			oob += chip->ecc.prepad;
3421
2992
 		}
3422
2993
 
3423
-		chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
2994
+		chip->ecc.hwctl(chip, NAND_ECC_READSYN);
3424
2995
 
3425
-		ret = nand_read_data_op(chip, oob, eccbytes, false);
2996
+		ret = nand_read_data_op(chip, oob, eccbytes, false, false);
3426
2997
 		if (ret)
3427
2998
 			return ret;
3428
2999
 
3429
-		stat = chip->ecc.correct(mtd, p, oob, NULL);
3000
+		stat = chip->ecc.correct(chip, p, oob, NULL);
3430
3001
 
3431
3002
 		oob += eccbytes;
3432
3003
 
3433
3004
 		if (chip->ecc.postpad) {
3434
3005
 			ret = nand_read_data_op(chip, oob, chip->ecc.postpad,
3435
-						false);
3006
+						false, false);
3436
3007
 			if (ret)
3437
3008
 				return ret;
3438
3009
 
..
..
@@ -3460,7 +3031,7 @@
3460
3031
 	/* Calculate remaining oob bytes */
3461
3032
 	i = mtd->oobsize - (oob - chip->oob_poi);
3462
3033
 	if (i) {
3463
-		ret = nand_read_data_op(chip, oob, i, false);
3034
+		ret = nand_read_data_op(chip, oob, i, false, false);
3464
3035
 		if (ret)
3465
3036
 			return ret;
3466
3037
 	}
..
..
@@ -3470,15 +3041,15 @@
3470
3041
 
3471
3042
 /**
3472
3043
  * nand_transfer_oob - [INTERN] Transfer oob to client buffer
3473
- * @mtd: mtd info structure
3044
+ * @chip: NAND chip object
3474
3045
  * @oob: oob destination address
3475
3046
  * @ops: oob ops structure
3476
3047
  * @len: size of oob to transfer
3477
3048
  */
3478
-static uint8_t *nand_transfer_oob(struct mtd_info *mtd, uint8_t *oob,
3049
+static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
3479
3050
 				  struct mtd_oob_ops *ops, size_t len)
3480
3051
 {
3481
-	struct nand_chip *chip = mtd_to_nand(mtd);
3052
+	struct mtd_info *mtd = nand_to_mtd(chip);
3482
3053
 	int ret;
3483
3054
 
3484
3055
 	switch (ops->mode) {
..
..
@@ -3502,54 +3073,63 @@
3502
3073
 
3503
3074
 /**
3504
3075
  * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
3505
- * @mtd: MTD device structure
3076
+ * @chip: NAND chip object
3506
3077
  * @retry_mode: the retry mode to use
3507
3078
  *
3508
3079
  * Some vendors supply a special command to shift the Vt threshold, to be used
3509
3080
  * when there are too many bitflips in a page (i.e., ECC error). After setting
3510
3081
  * a new threshold, the host should retry reading the page.
3511
3082
  */
3512
-static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
3083
+static int nand_setup_read_retry(struct nand_chip *chip, int retry_mode)
3513
3084
 {
3514
-	struct nand_chip *chip = mtd_to_nand(mtd);
3515
-
3516
3085
 	pr_debug("setting READ RETRY mode %d\n", retry_mode);
3517
3086
 
3518
3087
 	if (retry_mode >= chip->read_retries)
3519
3088
 		return -EINVAL;
3520
3089
 
3521
-	if (!chip->setup_read_retry)
3090
+	if (!chip->ops.setup_read_retry)
3522
3091
 		return -EOPNOTSUPP;
3523
3092
 
3524
-	return chip->setup_read_retry(mtd, retry_mode);
3093
+	return chip->ops.setup_read_retry(chip, retry_mode);
3094
+}
3095
+
3096
+static void nand_wait_readrdy(struct nand_chip *chip)
3097
+{
3098
+	const struct nand_sdr_timings *sdr;
3099
+
3100
+	if (!(chip->options & NAND_NEED_READRDY))
3101
+		return;
3102
+
3103
+	sdr = nand_get_sdr_timings(nand_get_interface_config(chip));
3104
+	WARN_ON(nand_wait_rdy_op(chip, PSEC_TO_MSEC(sdr->tR_max), 0));
3525
3105
 }
3526
3106
 
3527
3107
 /**
3528
3108
  * nand_do_read_ops - [INTERN] Read data with ECC
3529
- * @mtd: MTD device structure
3109
+ * @chip: NAND chip object
3530
3110
  * @from: offset to read from
3531
3111
  * @ops: oob ops structure
3532
3112
  *
3533
3113
  * Internal function. Called with chip held.
3534
3114
  */
3535
-static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
3115
+static int nand_do_read_ops(struct nand_chip *chip, loff_t from,
3536
3116
 			    struct mtd_oob_ops *ops)
3537
3117
 {
3538
3118
 	int chipnr, page, realpage, col, bytes, aligned, oob_required;
3539
-	struct nand_chip *chip = mtd_to_nand(mtd);
3119
+	struct mtd_info *mtd = nand_to_mtd(chip);
3540
3120
 	int ret = 0;
3541
3121
 	uint32_t readlen = ops->len;
3542
3122
 	uint32_t oobreadlen = ops->ooblen;
3543
3123
 	uint32_t max_oobsize = mtd_oobavail(mtd, ops);
3544
3124
 
3545
3125
 	uint8_t *bufpoi, *oob, *buf;
3546
-	int use_bufpoi;
3126
+	int use_bounce_buf;
3547
3127
 	unsigned int max_bitflips = 0;
3548
3128
 	int retry_mode = 0;
3549
3129
 	bool ecc_fail = false;
3550
3130
 
3551
3131
 	chipnr = (int)(from >> chip->chip_shift);
3552
-	chip->select_chip(mtd, chipnr);
3132
+	nand_select_target(chip, chipnr);
3553
3133
 
3554
3134
 	realpage = (int)(from >> chip->page_shift);
3555
3135
 	page = realpage & chip->pagemask;
..
..
@@ -3561,25 +3141,25 @@
3561
3141
 	oob_required = oob ? 1 : 0;
3562
3142
 
3563
3143
 	while (1) {
3564
-		unsigned int ecc_failures = mtd->ecc_stats.failed;
3144
+		struct mtd_ecc_stats ecc_stats = mtd->ecc_stats;
3565
3145
 
3566
3146
 		bytes = min(mtd->writesize - col, readlen);
3567
3147
 		aligned = (bytes == mtd->writesize);
3568
3148
 
3569
3149
 		if (!aligned)
3570
-			use_bufpoi = 1;
3571
-		else if (chip->options & NAND_USE_BOUNCE_BUFFER)
3572
-			use_bufpoi = !virt_addr_valid(buf) ||
3573
-				     !IS_ALIGNED((unsigned long)buf,
3574
-						 chip->buf_align);
3150
+			use_bounce_buf = 1;
3151
+		else if (chip->options & NAND_USES_DMA)
3152
+			use_bounce_buf = !virt_addr_valid(buf) ||
3153
+					 !IS_ALIGNED((unsigned long)buf,
3154
+						     chip->buf_align);
3575
3155
 		else
3576
-			use_bufpoi = 0;
3156
+			use_bounce_buf = 0;
3577
3157
 
3578
3158
 		/* Is the current page in the buffer? */
3579
-		if (realpage != chip->pagebuf || oob) {
3580
-			bufpoi = use_bufpoi ? chip->data_buf : buf;
3159
+		if (realpage != chip->pagecache.page || oob) {
3160
+			bufpoi = use_bounce_buf ? chip->data_buf : buf;
3581
3161
 
3582
-			if (use_bufpoi && aligned)
3162
+			if (use_bounce_buf && aligned)
3583
3163
 				pr_debug("%s: using read bounce buffer for buf@%p\n",
3584
3164
 						 __func__, buf);
3585
3165
 
..
..
@@ -3589,66 +3169,62 @@
3589
3169
 			 * the read methods return max bitflips per ecc step.
3590
3170
 			 */
3591
3171
 			if (unlikely(ops->mode == MTD_OPS_RAW))
3592
-				ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
3172
+				ret = chip->ecc.read_page_raw(chip, bufpoi,
3593
3173
 							      oob_required,
3594
3174
 							      page);
3595
3175
 			else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
3596
3176
 				 !oob)
3597
-				ret = chip->ecc.read_subpage(mtd, chip,
3598
-							col, bytes, bufpoi,
3599
-							page);
3177
+				ret = chip->ecc.read_subpage(chip, col, bytes,
3178
+							     bufpoi, page);
3600
3179
 			else
3601
-				ret = chip->ecc.read_page(mtd, chip, bufpoi,
3180
+				ret = chip->ecc.read_page(chip, bufpoi,
3602
3181
 							  oob_required, page);
3603
3182
 			if (ret < 0) {
3604
-				if (use_bufpoi)
3183
+				if (use_bounce_buf)
3605
3184
 					/* Invalidate page cache */
3606
-					chip->pagebuf = -1;
3185
+					chip->pagecache.page = -1;
3607
3186
 				break;
3608
3187
 			}
3609
3188
 
3610
-			/* Transfer not aligned data */
3611
-			if (use_bufpoi) {
3189
+			/*
3190
+			 * Copy back the data in the initial buffer when reading
3191
+			 * partial pages or when a bounce buffer is required.
3192
+			 */
3193
+			if (use_bounce_buf) {
3612
3194
 				if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
3613
-				    !(mtd->ecc_stats.failed - ecc_failures) &&
3195
+				    !(mtd->ecc_stats.failed - ecc_stats.failed) &&
3614
3196
 				    (ops->mode != MTD_OPS_RAW)) {
3615
-					chip->pagebuf = realpage;
3616
-					chip->pagebuf_bitflips = ret;
3197
+					chip->pagecache.page = realpage;
3198
+					chip->pagecache.bitflips = ret;
3617
3199
 				} else {
3618
3200
 					/* Invalidate page cache */
3619
-					chip->pagebuf = -1;
3201
+					chip->pagecache.page = -1;
3620
3202
 				}
3621
-				memcpy(buf, chip->data_buf + col, bytes);
3203
+				memcpy(buf, bufpoi + col, bytes);
3622
3204
 			}
3623
3205
 
3624
3206
 			if (unlikely(oob)) {
3625
3207
 				int toread = min(oobreadlen, max_oobsize);
3626
3208
 
3627
3209
 				if (toread) {
3628
-					oob = nand_transfer_oob(mtd,
3629
-						oob, ops, toread);
3210
+					oob = nand_transfer_oob(chip, oob, ops,
3211
+								toread);
3630
3212
 					oobreadlen -= toread;
3631
3213
 				}
3632
3214
 			}
3633
3215
 
3634
-			if (chip->options & NAND_NEED_READRDY) {
3635
-				/* Apply delay or wait for ready/busy pin */
3636
-				if (!chip->dev_ready)
3637
-					udelay(chip->chip_delay);
3638
-				else
3639
-					nand_wait_ready(mtd);
3640
-			}
3216
+			nand_wait_readrdy(chip);
3641
3217
 
3642
-			if (mtd->ecc_stats.failed - ecc_failures) {
3218
+			if (mtd->ecc_stats.failed - ecc_stats.failed) {
3643
3219
 				if (retry_mode + 1 < chip->read_retries) {
3644
3220
 					retry_mode++;
3645
-					ret = nand_setup_read_retry(mtd,
3221
+					ret = nand_setup_read_retry(chip,
3646
3222
 							retry_mode);
3647
3223
 					if (ret < 0)
3648
3224
 						break;
3649
3225
 
3650
-					/* Reset failures; retry */
3651
-					mtd->ecc_stats.failed = ecc_failures;
3226
+					/* Reset ecc_stats; retry */
3227
+					mtd->ecc_stats = ecc_stats;
3652
3228
 					goto read_retry;
3653
3229
 				} else {
3654
3230
 					/* No more retry modes; real failure */
..
..
@@ -3662,14 +3238,14 @@
3662
3238
 			memcpy(buf, chip->data_buf + col, bytes);
3663
3239
 			buf += bytes;
3664
3240
 			max_bitflips = max_t(unsigned int, max_bitflips,
3665
-					     chip->pagebuf_bitflips);
3241
+					     chip->pagecache.bitflips);
3666
3242
 		}
3667
3243
 
3668
3244
 		readlen -= bytes;
3669
3245
 
3670
3246
 		/* Reset to retry mode 0 */
3671
3247
 		if (retry_mode) {
3672
-			ret = nand_setup_read_retry(mtd, 0);
3248
+			ret = nand_setup_read_retry(chip, 0);
3673
3249
 			if (ret < 0)
3674
3250
 				break;
3675
3251
 			retry_mode = 0;
..
..
@@ -3687,11 +3263,11 @@
3687
3263
 		/* Check, if we cross a chip boundary */
3688
3264
 		if (!page) {
3689
3265
 			chipnr++;
3690
-			chip->select_chip(mtd, -1);
3691
-			chip->select_chip(mtd, chipnr);
3266
+			nand_deselect_target(chip);
3267
+			nand_select_target(chip, chipnr);
3692
3268
 		}
3693
3269
 	}
3694
-	chip->select_chip(mtd, -1);
3270
+	nand_deselect_target(chip);
3695
3271
 
3696
3272
 	ops->retlen = ops->len - (size_t) readlen;
3697
3273
 	if (oob)
..
..
@@ -3708,12 +3284,13 @@
3708
3284
 
3709
3285
 /**
3710
3286
  * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
3711
- * @mtd: mtd info structure
3712
3287
  * @chip: nand chip info structure
3713
3288
  * @page: page number to read
3714
3289
  */
3715
-int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page)
3290
+int nand_read_oob_std(struct nand_chip *chip, int page)
3716
3291
 {
3292
+	struct mtd_info *mtd = nand_to_mtd(chip);
3293
+
3717
3294
 	return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
3718
3295
 }
3719
3296
 EXPORT_SYMBOL(nand_read_oob_std);
..
..
@@ -3721,13 +3298,12 @@
3721
3298
 /**
3722
3299
  * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
3723
3300
  *			    with syndromes
3724
- * @mtd: mtd info structure
3725
3301
  * @chip: nand chip info structure
3726
3302
  * @page: page number to read
3727
3303
  */
3728
-int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
3729
-			   int page)
3304
+static int nand_read_oob_syndrome(struct nand_chip *chip, int page)
3730
3305
 {
3306
+	struct mtd_info *mtd = nand_to_mtd(chip);
3731
3307
 	int length = mtd->oobsize;
3732
3308
 	int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
3733
3309
 	int eccsize = chip->ecc.size;
..
..
@@ -3757,7 +3333,7 @@
3757
3333
 			sndrnd = 1;
3758
3334
 		toread = min_t(int, length, chunk);
3759
3335
 
3760
-		ret = nand_read_data_op(chip, bufpoi, toread, false);
3336
+		ret = nand_read_data_op(chip, bufpoi, toread, false, false);
3761
3337
 		if (ret)
3762
3338
 			return ret;
3763
3339
 
..
..
@@ -3765,23 +3341,23 @@
3765
3341
 		length -= toread;
3766
3342
 	}
3767
3343
 	if (length > 0) {
3768
-		ret = nand_read_data_op(chip, bufpoi, length, false);
3344
+		ret = nand_read_data_op(chip, bufpoi, length, false, false);
3769
3345
 		if (ret)
3770
3346
 			return ret;
3771
3347
 	}
3772
3348
 
3773
3349
 	return 0;
3774
3350
 }
3775
-EXPORT_SYMBOL(nand_read_oob_syndrome);
3776
3351
 
3777
3352
 /**
3778
3353
  * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
3779
- * @mtd: mtd info structure
3780
3354
  * @chip: nand chip info structure
3781
3355
  * @page: page number to write
3782
3356
  */
3783
-int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page)
3357
+int nand_write_oob_std(struct nand_chip *chip, int page)
3784
3358
 {
3359
+	struct mtd_info *mtd = nand_to_mtd(chip);
3360
+
3785
3361
 	return nand_prog_page_op(chip, page, mtd->writesize, chip->oob_poi,
3786
3362
 				 mtd->oobsize);
3787
3363
 }
..
..
@@ -3790,13 +3366,12 @@
3790
3366
 /**
3791
3367
  * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
3792
3368
  *			     with syndrome - only for large page flash
3793
- * @mtd: mtd info structure
3794
3369
  * @chip: nand chip info structure
3795
3370
  * @page: page number to write
3796
3371
  */
3797
-int nand_write_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
3798
-			    int page)
3372
+static int nand_write_oob_syndrome(struct nand_chip *chip, int page)
3799
3373
 {
3374
+	struct mtd_info *mtd = nand_to_mtd(chip);
3800
3375
 	int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
3801
3376
 	int eccsize = chip->ecc.size, length = mtd->oobsize;
3802
3377
 	int ret, i, len, pos, sndcmd = 0, steps = chip->ecc.steps;
..
..
@@ -3860,22 +3435,21 @@
3860
3435
 
3861
3436
 	return nand_prog_page_end_op(chip);
3862
3437
 }
3863
-EXPORT_SYMBOL(nand_write_oob_syndrome);
3864
3438
 
3865
3439
 /**
3866
3440
  * nand_do_read_oob - [INTERN] NAND read out-of-band
3867
- * @mtd: MTD device structure
3441
+ * @chip: NAND chip object
3868
3442
  * @from: offset to read from
3869
3443
  * @ops: oob operations description structure
3870
3444
  *
3871
3445
  * NAND read out-of-band data from the spare area.
3872
3446
  */
3873
-static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
3447
+static int nand_do_read_oob(struct nand_chip *chip, loff_t from,
3874
3448
 			    struct mtd_oob_ops *ops)
3875
3449
 {
3450
+	struct mtd_info *mtd = nand_to_mtd(chip);
3876
3451
 	unsigned int max_bitflips = 0;
3877
3452
 	int page, realpage, chipnr;
3878
-	struct nand_chip *chip = mtd_to_nand(mtd);
3879
3453
 	struct mtd_ecc_stats stats;
3880
3454
 	int readlen = ops->ooblen;
3881
3455
 	int len;
..
..
@@ -3890,7 +3464,7 @@
3890
3464
 	len = mtd_oobavail(mtd, ops);
3891
3465
 
3892
3466
 	chipnr = (int)(from >> chip->chip_shift);
3893
-	chip->select_chip(mtd, chipnr);
3467
+	nand_select_target(chip, chipnr);
3894
3468
 
3895
3469
 	/* Shift to get page */
3896
3470
 	realpage = (int)(from >> chip->page_shift);
..
..
@@ -3898,23 +3472,17 @@
3898
3472
 
3899
3473
 	while (1) {
3900
3474
 		if (ops->mode == MTD_OPS_RAW)
3901
-			ret = chip->ecc.read_oob_raw(mtd, chip, page);
3475
+			ret = chip->ecc.read_oob_raw(chip, page);
3902
3476
 		else
3903
-			ret = chip->ecc.read_oob(mtd, chip, page);
3477
+			ret = chip->ecc.read_oob(chip, page);
3904
3478
 
3905
3479
 		if (ret < 0)
3906
3480
 			break;
3907
3481
 
3908
3482
 		len = min(len, readlen);
3909
-		buf = nand_transfer_oob(mtd, buf, ops, len);
3483
+		buf = nand_transfer_oob(chip, buf, ops, len);
3910
3484
 
3911
-		if (chip->options & NAND_NEED_READRDY) {
3912
-			/* Apply delay or wait for ready/busy pin */
3913
-			if (!chip->dev_ready)
3914
-				udelay(chip->chip_delay);
3915
-			else
3916
-				nand_wait_ready(mtd);
3917
-		}
3485
+		nand_wait_readrdy(chip);
3918
3486
 
3919
3487
 		max_bitflips = max_t(unsigned int, max_bitflips, ret);
3920
3488
 
..
..
@@ -3929,11 +3497,11 @@
3929
3497
 		/* Check, if we cross a chip boundary */
3930
3498
 		if (!page) {
3931
3499
 			chipnr++;
3932
-			chip->select_chip(mtd, -1);
3933
-			chip->select_chip(mtd, chipnr);
3500
+			nand_deselect_target(chip);
3501
+			nand_select_target(chip, chipnr);
3934
3502
 		}
3935
3503
 	}
3936
-	chip->select_chip(mtd, -1);
3504
+	nand_deselect_target(chip);
3937
3505
 
3938
3506
 	ops->oobretlen = ops->ooblen - readlen;
3939
3507
 
..
..
@@ -3957,6 +3525,7 @@
3957
3525
 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
3958
3526
 			 struct mtd_oob_ops *ops)
3959
3527
 {
3528
+	struct nand_chip *chip = mtd_to_nand(mtd);
3960
3529
 	int ret;
3961
3530
 
3962
3531
 	ops->retlen = 0;
..
..
@@ -3966,20 +3535,19 @@
3966
3535
 	    ops->mode != MTD_OPS_RAW)
3967
3536
 		return -ENOTSUPP;
3968
3537
 
3969
-	nand_get_device(mtd, FL_READING);
3538
+	nand_get_device(chip);
3970
3539
 
3971
3540
 	if (!ops->datbuf)
3972
-		ret = nand_do_read_oob(mtd, from, ops);
3541
+		ret = nand_do_read_oob(chip, from, ops);
3973
3542
 	else
3974
-		ret = nand_do_read_ops(mtd, from, ops);
3543
+		ret = nand_do_read_ops(chip, from, ops);
3975
3544
 
3976
-	nand_release_device(mtd);
3545
+	nand_release_device(chip);
3977
3546
 	return ret;
3978
3547
 }
3979
3548
 
3980
3549
 /**
3981
3550
  * nand_write_page_raw_notsupp - dummy raw page write function
3982
- * @mtd: mtd info structure
3983
3551
  * @chip: nand chip info structure
3984
3552
  * @buf: data buffer
3985
3553
  * @oob_required: must write chip->oob_poi to OOB
..
..
@@ -3987,16 +3555,14 @@
3987
3555
  *
3988
3556
  * Returns -ENOTSUPP unconditionally.
3989
3557
  */
3990
-int nand_write_page_raw_notsupp(struct mtd_info *mtd, struct nand_chip *chip,
3991
-				const u8 *buf, int oob_required, int page)
3558
+int nand_write_page_raw_notsupp(struct nand_chip *chip, const u8 *buf,
3559
+				int oob_required, int page)
3992
3560
 {
3993
3561
 	return -ENOTSUPP;
3994
3562
 }
3995
-EXPORT_SYMBOL(nand_write_page_raw_notsupp);
3996
3563
 
3997
3564
 /**
3998
3565
  * nand_write_page_raw - [INTERN] raw page write function
3999
- * @mtd: mtd info structure
4000
3566
  * @chip: nand chip info structure
4001
3567
  * @buf: data buffer
4002
3568
  * @oob_required: must write chip->oob_poi to OOB
..
..
@@ -4004,9 +3570,10 @@
4004
3570
  *
4005
3571
  * Not for syndrome calculating ECC controllers, which use a special oob layout.
4006
3572
  */
4007
-int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
4008
-			const uint8_t *buf, int oob_required, int page)
3573
+int nand_write_page_raw(struct nand_chip *chip, const uint8_t *buf,
3574
+			int oob_required, int page)
4009
3575
 {
3576
+	struct mtd_info *mtd = nand_to_mtd(chip);
4010
3577
 	int ret;
4011
3578
 
4012
3579
 	ret = nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize);
..
..
@@ -4025,8 +3592,43 @@
4025
3592
 EXPORT_SYMBOL(nand_write_page_raw);
4026
3593
 
4027
3594
 /**
3595
+ * nand_monolithic_write_page_raw - Monolithic page write in raw mode
3596
+ * @chip: NAND chip info structure
3597
+ * @buf: data buffer to write
3598
+ * @oob_required: must write chip->oob_poi to OOB
3599
+ * @page: page number to write
3600
+ *
3601
+ * This is a raw page write, ie. without any error detection/correction.
3602
+ * Monolithic means we are requesting all the relevant data (main plus
3603
+ * eventually OOB) to be sent over the bus and effectively programmed
3604
+ * into the NAND chip arrays in a single operation. This is an
3605
+ * alternative to nand_write_page_raw(), which first sends the main
3606
+ * data, then eventually send the OOB data by latching more data
3607
+ * cycles on the NAND bus, and finally sends the program command to
3608
+ * synchronyze the NAND chip cache.
3609
+ */
3610
+int nand_monolithic_write_page_raw(struct nand_chip *chip, const u8 *buf,
3611
+				   int oob_required, int page)
3612
+{
3613
+	struct mtd_info *mtd = nand_to_mtd(chip);
3614
+	unsigned int size = mtd->writesize;
3615
+	u8 *write_buf = (u8 *)buf;
3616
+
3617
+	if (oob_required) {
3618
+		size += mtd->oobsize;
3619
+
3620
+		if (buf != chip->data_buf) {
3621
+			write_buf = nand_get_data_buf(chip);
3622
+			memcpy(write_buf, buf, mtd->writesize);
3623
+		}
3624
+	}
3625
+
3626
+	return nand_prog_page_op(chip, page, 0, write_buf, size);
3627
+}
3628
+EXPORT_SYMBOL(nand_monolithic_write_page_raw);
3629
+
3630
+/**
4028
3631
  * nand_write_page_raw_syndrome - [INTERN] raw page write function
4029
- * @mtd: mtd info structure
4030
3632
  * @chip: nand chip info structure
4031
3633
  * @buf: data buffer
4032
3634
  * @oob_required: must write chip->oob_poi to OOB
..
..
@@ -4034,11 +3636,11 @@
4034
3636
  *
4035
3637
  * We need a special oob layout and handling even when ECC isn't checked.
4036
3638
  */
4037
-static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
4038
-					struct nand_chip *chip,
3639
+static int nand_write_page_raw_syndrome(struct nand_chip *chip,
4039
3640
 					const uint8_t *buf, int oob_required,
4040
3641
 					int page)
4041
3642
 {
3643
+	struct mtd_info *mtd = nand_to_mtd(chip);
4042
3644
 	int eccsize = chip->ecc.size;
4043
3645
 	int eccbytes = chip->ecc.bytes;
4044
3646
 	uint8_t *oob = chip->oob_poi;
..
..
@@ -4091,16 +3693,15 @@
4091
3693
 }
4092
3694
 /**
4093
3695
  * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
4094
- * @mtd: mtd info structure
4095
3696
  * @chip: nand chip info structure
4096
3697
  * @buf: data buffer
4097
3698
  * @oob_required: must write chip->oob_poi to OOB
4098
3699
  * @page: page number to write
4099
3700
  */
4100
-static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
4101
-				 const uint8_t *buf, int oob_required,
4102
-				 int page)
3701
+static int nand_write_page_swecc(struct nand_chip *chip, const uint8_t *buf,
3702
+				 int oob_required, int page)
4103
3703
 {
3704
+	struct mtd_info *mtd = nand_to_mtd(chip);
4104
3705
 	int i, eccsize = chip->ecc.size, ret;
4105
3706
 	int eccbytes = chip->ecc.bytes;
4106
3707
 	int eccsteps = chip->ecc.steps;
..
..
@@ -4109,28 +3710,27 @@
4109
3710
 
4110
3711
 	/* Software ECC calculation */
4111
3712
 	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
4112
-		chip->ecc.calculate(mtd, p, &ecc_calc[i]);
3713
+		chip->ecc.calculate(chip, p, &ecc_calc[i]);
4113
3714
 
4114
3715
 	ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
4115
3716
 					 chip->ecc.total);
4116
3717
 	if (ret)
4117
3718
 		return ret;
4118
3719
 
4119
-	return chip->ecc.write_page_raw(mtd, chip, buf, 1, page);
3720
+	return chip->ecc.write_page_raw(chip, buf, 1, page);
4120
3721
 }
4121
3722
 
4122
3723
 /**
4123
3724
  * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
4124
- * @mtd: mtd info structure
4125
3725
  * @chip: nand chip info structure
4126
3726
  * @buf: data buffer
4127
3727
  * @oob_required: must write chip->oob_poi to OOB
4128
3728
  * @page: page number to write
4129
3729
  */
4130
-static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
4131
-				  const uint8_t *buf, int oob_required,
4132
-				  int page)
3730
+static int nand_write_page_hwecc(struct nand_chip *chip, const uint8_t *buf,
3731
+				 int oob_required, int page)
4133
3732
 {
3733
+	struct mtd_info *mtd = nand_to_mtd(chip);
4134
3734
 	int i, eccsize = chip->ecc.size, ret;
4135
3735
 	int eccbytes = chip->ecc.bytes;
4136
3736
 	int eccsteps = chip->ecc.steps;
..
..
@@ -4142,13 +3742,13 @@
4142
3742
 		return ret;
4143
3743
 
4144
3744
 	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
4145
-		chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
3745
+		chip->ecc.hwctl(chip, NAND_ECC_WRITE);
4146
3746
 
4147
3747
 		ret = nand_write_data_op(chip, p, eccsize, false);
4148
3748
 		if (ret)
4149
3749
 			return ret;
4150
3750
 
4151
-		chip->ecc.calculate(mtd, p, &ecc_calc[i]);
3751
+		chip->ecc.calculate(chip, p, &ecc_calc[i]);
4152
3752
 	}
4153
3753
 
4154
3754
 	ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
..
..
@@ -4166,7 +3766,6 @@
4166
3766
 
4167
3767
 /**
4168
3768
  * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
4169
- * @mtd:	mtd info structure
4170
3769
  * @chip:	nand chip info structure
4171
3770
  * @offset:	column address of subpage within the page
4172
3771
  * @data_len:	data length
..
..
@@ -4174,11 +3773,11 @@
4174
3773
  * @oob_required: must write chip->oob_poi to OOB
4175
3774
  * @page: page number to write
4176
3775
  */
4177
-static int nand_write_subpage_hwecc(struct mtd_info *mtd,
4178
-				struct nand_chip *chip, uint32_t offset,
4179
-				uint32_t data_len, const uint8_t *buf,
4180
-				int oob_required, int page)
3776
+static int nand_write_subpage_hwecc(struct nand_chip *chip, uint32_t offset,
3777
+				    uint32_t data_len, const uint8_t *buf,
3778
+				    int oob_required, int page)
4181
3779
 {
3780
+	struct mtd_info *mtd = nand_to_mtd(chip);
4182
3781
 	uint8_t *oob_buf  = chip->oob_poi;
4183
3782
 	uint8_t *ecc_calc = chip->ecc.calc_buf;
4184
3783
 	int ecc_size      = chip->ecc.size;
..
..
@@ -4195,7 +3794,7 @@
4195
3794
 
4196
3795
 	for (step = 0; step < ecc_steps; step++) {
4197
3796
 		/* configure controller for WRITE access */
4198
-		chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
3797
+		chip->ecc.hwctl(chip, NAND_ECC_WRITE);
4199
3798
 
4200
3799
 		/* write data (untouched subpages already masked by 0xFF) */
4201
3800
 		ret = nand_write_data_op(chip, buf, ecc_size, false);
..
..
@@ -4206,7 +3805,7 @@
4206
3805
 		if ((step < start_step) || (step > end_step))
4207
3806
 			memset(ecc_calc, 0xff, ecc_bytes);
4208
3807
 		else
4209
-			chip->ecc.calculate(mtd, buf, ecc_calc);
3808
+			chip->ecc.calculate(chip, buf, ecc_calc);
4210
3809
 
4211
3810
 		/* mask OOB of un-touched subpages by padding 0xFF */
4212
3811
 		/* if oob_required, preserve OOB metadata of written subpage */
..
..
@@ -4237,7 +3836,6 @@
4237
3836
 
4238
3837
 /**
4239
3838
  * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
4240
- * @mtd: mtd info structure
4241
3839
  * @chip: nand chip info structure
4242
3840
  * @buf: data buffer
4243
3841
  * @oob_required: must write chip->oob_poi to OOB
..
..
@@ -4246,11 +3844,10 @@
4246
3844
  * The hw generator calculates the error syndrome automatically. Therefore we
4247
3845
  * need a special oob layout and handling.
4248
3846
  */
4249
-static int nand_write_page_syndrome(struct mtd_info *mtd,
4250
-				    struct nand_chip *chip,
4251
-				    const uint8_t *buf, int oob_required,
4252
-				    int page)
3847
+static int nand_write_page_syndrome(struct nand_chip *chip, const uint8_t *buf,
3848
+				    int oob_required, int page)
4253
3849
 {
3850
+	struct mtd_info *mtd = nand_to_mtd(chip);
4254
3851
 	int i, eccsize = chip->ecc.size;
4255
3852
 	int eccbytes = chip->ecc.bytes;
4256
3853
 	int eccsteps = chip->ecc.steps;
..
..
@@ -4263,7 +3860,7 @@
4263
3860
 		return ret;
4264
3861
 
4265
3862
 	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
4266
-		chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
3863
+		chip->ecc.hwctl(chip, NAND_ECC_WRITE);
4267
3864
 
4268
3865
 		ret = nand_write_data_op(chip, p, eccsize, false);
4269
3866
 		if (ret)
..
..
@@ -4278,7 +3875,7 @@
4278
3875
 			oob += chip->ecc.prepad;
4279
3876
 		}
4280
3877
 
4281
-		chip->ecc.calculate(mtd, p, oob);
3878
+		chip->ecc.calculate(chip, p, oob);
4282
3879
 
4283
3880
 		ret = nand_write_data_op(chip, oob, eccbytes, false);
4284
3881
 		if (ret)
..
..
@@ -4309,7 +3906,6 @@
4309
3906
 
4310
3907
 /**
4311
3908
  * nand_write_page - write one page
4312
- * @mtd: MTD device structure
4313
3909
  * @chip: NAND chip descriptor
4314
3910
  * @offset: address offset within the page
4315
3911
  * @data_len: length of actual data to be written
..
..
@@ -4318,10 +3914,11 @@
4318
3914
  * @page: page number to write
4319
3915
  * @raw: use _raw version of write_page
4320
3916
  */
4321
-static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
4322
-		uint32_t offset, int data_len, const uint8_t *buf,
4323
-		int oob_required, int page, int raw)
3917
+static int nand_write_page(struct nand_chip *chip, uint32_t offset,
3918
+			   int data_len, const uint8_t *buf, int oob_required,
3919
+			   int page, int raw)
4324
3920
 {
3921
+	struct mtd_info *mtd = nand_to_mtd(chip);
4325
3922
 	int status, subpage;
4326
3923
 
4327
3924
 	if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
..
..
@@ -4331,14 +3928,13 @@
4331
3928
 		subpage = 0;
4332
3929
 
4333
3930
 	if (unlikely(raw))
4334
-		status = chip->ecc.write_page_raw(mtd, chip, buf,
4335
-						  oob_required, page);
3931
+		status = chip->ecc.write_page_raw(chip, buf, oob_required,
3932
+						  page);
4336
3933
 	else if (subpage)
4337
-		status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
4338
-						 buf, oob_required, page);
3934
+		status = chip->ecc.write_subpage(chip, offset, data_len, buf,
3935
+						 oob_required, page);
4339
3936
 	else
4340
-		status = chip->ecc.write_page(mtd, chip, buf, oob_required,
4341
-					      page);
3937
+		status = chip->ecc.write_page(chip, buf, oob_required, page);
4342
3938
 
4343
3939
 	if (status < 0)
4344
3940
 		return status;
..
..
@@ -4346,59 +3942,21 @@
4346
3942
 	return 0;
4347
3943
 }
4348
3944
 
4349
-/**
4350
- * nand_fill_oob - [INTERN] Transfer client buffer to oob
4351
- * @mtd: MTD device structure
4352
- * @oob: oob data buffer
4353
- * @len: oob data write length
4354
- * @ops: oob ops structure
4355
- */
4356
-static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
4357
-			      struct mtd_oob_ops *ops)
4358
-{
4359
-	struct nand_chip *chip = mtd_to_nand(mtd);
4360
-	int ret;
4361
-
4362
-	/*
4363
-	 * Initialise to all 0xFF, to avoid the possibility of left over OOB
4364
-	 * data from a previous OOB read.
4365
-	 */
4366
-	memset(chip->oob_poi, 0xff, mtd->oobsize);
4367
-
4368
-	switch (ops->mode) {
4369
-
4370
-	case MTD_OPS_PLACE_OOB:
4371
-	case MTD_OPS_RAW:
4372
-		memcpy(chip->oob_poi + ops->ooboffs, oob, len);
4373
-		return oob + len;
4374
-
4375
-	case MTD_OPS_AUTO_OOB:
4376
-		ret = mtd_ooblayout_set_databytes(mtd, oob, chip->oob_poi,
4377
-						  ops->ooboffs, len);
4378
-		BUG_ON(ret);
4379
-		return oob + len;
4380
-
4381
-	default:
4382
-		BUG();
4383
-	}
4384
-	return NULL;
4385
-}
4386
-
4387
3945
 #define NOTALIGNED(x)	((x & (chip->subpagesize - 1)) != 0)
4388
3946
 
4389
3947
 /**
4390
3948
  * nand_do_write_ops - [INTERN] NAND write with ECC
4391
- * @mtd: MTD device structure
3949
+ * @chip: NAND chip object
4392
3950
  * @to: offset to write to
4393
3951
  * @ops: oob operations description structure
4394
3952
  *
4395
3953
  * NAND write with ECC.
4396
3954
  */
4397
-static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
3955
+static int nand_do_write_ops(struct nand_chip *chip, loff_t to,
4398
3956
 			     struct mtd_oob_ops *ops)
4399
3957
 {
3958
+	struct mtd_info *mtd = nand_to_mtd(chip);
4400
3959
 	int chipnr, realpage, page, column;
4401
-	struct nand_chip *chip = mtd_to_nand(mtd);
4402
3960
 	uint32_t writelen = ops->len;
4403
3961
 
4404
3962
 	uint32_t oobwritelen = ops->ooblen;
..
..
@@ -4423,10 +3981,10 @@
4423
3981
 	column = to & (mtd->writesize - 1);
4424
3982
 
4425
3983
 	chipnr = (int)(to >> chip->chip_shift);
4426
-	chip->select_chip(mtd, chipnr);
3984
+	nand_select_target(chip, chipnr);
4427
3985
 
4428
3986
 	/* Check, if it is write protected */
4429
-	if (nand_check_wp(mtd)) {
3987
+	if (nand_check_wp(chip)) {
4430
3988
 		ret = -EIO;
4431
3989
 		goto err_out;
4432
3990
 	}
..
..
@@ -4435,9 +3993,9 @@
4435
3993
 	page = realpage & chip->pagemask;
4436
3994
 
4437
3995
 	/* Invalidate the page cache, when we write to the cached page */
4438
-	if (to <= ((loff_t)chip->pagebuf << chip->page_shift) &&
4439
-	    ((loff_t)chip->pagebuf << chip->page_shift) < (to + ops->len))
4440
-		chip->pagebuf = -1;
3996
+	if (to <= ((loff_t)chip->pagecache.page << chip->page_shift) &&
3997
+	    ((loff_t)chip->pagecache.page << chip->page_shift) < (to + ops->len))
3998
+		chip->pagecache.page = -1;
4441
3999
 
4442
4000
 	/* Don't allow multipage oob writes with offset */
4443
4001
 	if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
..
..
@@ -4448,40 +4006,42 @@
4448
4006
 	while (1) {
4449
4007
 		int bytes = mtd->writesize;
4450
4008
 		uint8_t *wbuf = buf;
4451
-		int use_bufpoi;
4009
+		int use_bounce_buf;
4452
4010
 		int part_pagewr = (column || writelen < mtd->writesize);
4453
4011
 
4454
4012
 		if (part_pagewr)
4455
-			use_bufpoi = 1;
4456
-		else if (chip->options & NAND_USE_BOUNCE_BUFFER)
4457
-			use_bufpoi = !virt_addr_valid(buf) ||
4458
-				     !IS_ALIGNED((unsigned long)buf,
4459
-						 chip->buf_align);
4013
+			use_bounce_buf = 1;
4014
+		else if (chip->options & NAND_USES_DMA)
4015
+			use_bounce_buf = !virt_addr_valid(buf) ||
4016
+					 !IS_ALIGNED((unsigned long)buf,
4017
+						     chip->buf_align);
4460
4018
 		else
4461
-			use_bufpoi = 0;
4019
+			use_bounce_buf = 0;
4462
4020
 
4463
-		/* Partial page write?, or need to use bounce buffer */
4464
-		if (use_bufpoi) {
4021
+		/*
4022
+		 * Copy the data from the initial buffer when doing partial page
4023
+		 * writes or when a bounce buffer is required.
4024
+		 */
4025
+		if (use_bounce_buf) {
4465
4026
 			pr_debug("%s: using write bounce buffer for buf@%p\n",
4466
4027
 					 __func__, buf);
4467
4028
 			if (part_pagewr)
4468
4029
 				bytes = min_t(int, bytes - column, writelen);
4469
-			chip->pagebuf = -1;
4470
-			memset(chip->data_buf, 0xff, mtd->writesize);
4471
-			memcpy(&chip->data_buf[column], buf, bytes);
4472
-			wbuf = chip->data_buf;
4030
+			wbuf = nand_get_data_buf(chip);
4031
+			memset(wbuf, 0xff, mtd->writesize);
4032
+			memcpy(&wbuf[column], buf, bytes);
4473
4033
 		}
4474
4034
 
4475
4035
 		if (unlikely(oob)) {
4476
4036
 			size_t len = min(oobwritelen, oobmaxlen);
4477
-			oob = nand_fill_oob(mtd, oob, len, ops);
4037
+			oob = nand_fill_oob(chip, oob, len, ops);
4478
4038
 			oobwritelen -= len;
4479
4039
 		} else {
4480
4040
 			/* We still need to erase leftover OOB data */
4481
4041
 			memset(chip->oob_poi, 0xff, mtd->oobsize);
4482
4042
 		}
4483
4043
 
4484
-		ret = nand_write_page(mtd, chip, column, bytes, wbuf,
4044
+		ret = nand_write_page(chip, column, bytes, wbuf,
4485
4045
 				      oob_required, page,
4486
4046
 				      (ops->mode == MTD_OPS_RAW));
4487
4047
 		if (ret)
..
..
@@ -4499,8 +4059,8 @@
4499
4059
 		/* Check, if we cross a chip boundary */
4500
4060
 		if (!page) {
4501
4061
 			chipnr++;
4502
-			chip->select_chip(mtd, -1);
4503
-			chip->select_chip(mtd, chipnr);
4062
+			nand_deselect_target(chip);
4063
+			nand_select_target(chip, chipnr);
4504
4064
 		}
4505
4065
 	}
4506
4066
 
..
..
@@ -4509,7 +4069,7 @@
4509
4069
 		ops->oobretlen = ops->ooblen;
4510
4070
 
4511
4071
 err_out:
4512
-	chip->select_chip(mtd, -1);
4072
+	nand_deselect_target(chip);
4513
4073
 	return ret;
4514
4074
 }
4515
4075
 
..
..
@@ -4532,91 +4092,20 @@
4532
4092
 	struct mtd_oob_ops ops;
4533
4093
 	int ret;
4534
4094
 
4535
-	/* Grab the device */
4536
-	panic_nand_get_device(chip, mtd, FL_WRITING);
4537
-
4538
-	chip->select_chip(mtd, chipnr);
4095
+	nand_select_target(chip, chipnr);
4539
4096
 
4540
4097
 	/* Wait for the device to get ready */
4541
-	panic_nand_wait(mtd, chip, 400);
4098
+	panic_nand_wait(chip, 400);
4542
4099
 
4543
4100
 	memset(&ops, 0, sizeof(ops));
4544
4101
 	ops.len = len;
4545
4102
 	ops.datbuf = (uint8_t *)buf;
4546
4103
 	ops.mode = MTD_OPS_PLACE_OOB;
4547
4104
 
4548
-	ret = nand_do_write_ops(mtd, to, &ops);
4105
+	ret = nand_do_write_ops(chip, to, &ops);
4549
4106
 
4550
4107
 	*retlen = ops.retlen;
4551
4108
 	return ret;
4552
-}
4553
-
4554
-/**
4555
- * nand_do_write_oob - [MTD Interface] NAND write out-of-band
4556
- * @mtd: MTD device structure
4557
- * @to: offset to write to
4558
- * @ops: oob operation description structure
4559
- *
4560
- * NAND write out-of-band.
4561
- */
4562
-static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
4563
-			     struct mtd_oob_ops *ops)
4564
-{
4565
-	int chipnr, page, status, len;
4566
-	struct nand_chip *chip = mtd_to_nand(mtd);
4567
-
4568
-	pr_debug("%s: to = 0x%08x, len = %i\n",
4569
-			 __func__, (unsigned int)to, (int)ops->ooblen);
4570
-
4571
-	len = mtd_oobavail(mtd, ops);
4572
-
4573
-	/* Do not allow write past end of page */
4574
-	if ((ops->ooboffs + ops->ooblen) > len) {
4575
-		pr_debug("%s: attempt to write past end of page\n",
4576
-				__func__);
4577
-		return -EINVAL;
4578
-	}
4579
-
4580
-	chipnr = (int)(to >> chip->chip_shift);
4581
-
4582
-	/*
4583
-	 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
4584
-	 * of my DiskOnChip 2000 test units) will clear the whole data page too
4585
-	 * if we don't do this. I have no clue why, but I seem to have 'fixed'
4586
-	 * it in the doc2000 driver in August 1999.  dwmw2.
4587
-	 */
4588
-	nand_reset(chip, chipnr);
4589
-
4590
-	chip->select_chip(mtd, chipnr);
4591
-
4592
-	/* Shift to get page */
4593
-	page = (int)(to >> chip->page_shift);
4594
-
4595
-	/* Check, if it is write protected */
4596
-	if (nand_check_wp(mtd)) {
4597
-		chip->select_chip(mtd, -1);
4598
-		return -EROFS;
4599
-	}
4600
-
4601
-	/* Invalidate the page cache, if we write to the cached page */
4602
-	if (page == chip->pagebuf)
4603
-		chip->pagebuf = -1;
4604
-
4605
-	nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
4606
-
4607
-	if (ops->mode == MTD_OPS_RAW)
4608
-		status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
4609
-	else
4610
-		status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
4611
-
4612
-	chip->select_chip(mtd, -1);
4613
-
4614
-	if (status)
4615
-		return status;
4616
-
4617
-	ops->oobretlen = ops->ooblen;
4618
-
4619
-	return 0;
4620
4109
 }
4621
4110
 
4622
4111
 /**
..
..
@@ -4628,11 +4117,12 @@
4628
4117
 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
4629
4118
 			  struct mtd_oob_ops *ops)
4630
4119
 {
4631
-	int ret = -ENOTSUPP;
4120
+	struct nand_chip *chip = mtd_to_nand(mtd);
4121
+	int ret = 0;
4632
4122
 
4633
4123
 	ops->retlen = 0;
4634
4124
 
4635
-	nand_get_device(mtd, FL_WRITING);
4125
+	nand_get_device(chip);
4636
4126
 
4637
4127
 	switch (ops->mode) {
4638
4128
 	case MTD_OPS_PLACE_OOB:
..
..
@@ -4645,31 +4135,13 @@
4645
4135
 	}
4646
4136
 
4647
4137
 	if (!ops->datbuf)
4648
-		ret = nand_do_write_oob(mtd, to, ops);
4138
+		ret = nand_do_write_oob(chip, to, ops);
4649
4139
 	else
4650
-		ret = nand_do_write_ops(mtd, to, ops);
4140
+		ret = nand_do_write_ops(chip, to, ops);
4651
4141
 
4652
4142
 out:
4653
-	nand_release_device(mtd);
4143
+	nand_release_device(chip);
4654
4144
 	return ret;
4655
-}
4656
-
4657
-/**
4658
- * single_erase - [GENERIC] NAND standard block erase command function
4659
- * @mtd: MTD device structure
4660
- * @page: the page address of the block which will be erased
4661
- *
4662
- * Standard erase command for NAND chips. Returns NAND status.
4663
- */
4664
-static int single_erase(struct mtd_info *mtd, int page)
4665
-{
4666
-	struct nand_chip *chip = mtd_to_nand(mtd);
4667
-	unsigned int eraseblock;
4668
-
4669
-	/* Send commands to erase a block */
4670
-	eraseblock = page >> (chip->phys_erase_shift - chip->page_shift);
4671
-
4672
-	return nand_erase_op(chip, eraseblock);
4673
4145
 }
4674
4146
 
4675
4147
 /**
..
..
@@ -4681,33 +4153,32 @@
4681
4153
  */
4682
4154
 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
4683
4155
 {
4684
-	return nand_erase_nand(mtd, instr, 0);
4156
+	return nand_erase_nand(mtd_to_nand(mtd), instr, 0);
4685
4157
 }
4686
4158
 
4687
4159
 /**
4688
4160
  * nand_erase_nand - [INTERN] erase block(s)
4689
- * @mtd: MTD device structure
4161
+ * @chip: NAND chip object
4690
4162
  * @instr: erase instruction
4691
4163
  * @allowbbt: allow erasing the bbt area
4692
4164
  *
4693
4165
  * Erase one ore more blocks.
4694
4166
  */
4695
-int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
4167
+int nand_erase_nand(struct nand_chip *chip, struct erase_info *instr,
4696
4168
 		    int allowbbt)
4697
4169
 {
4698
-	int page, status, pages_per_block, ret, chipnr;
4699
-	struct nand_chip *chip = mtd_to_nand(mtd);
4170
+	int page, pages_per_block, ret, chipnr;
4700
4171
 	loff_t len;
4701
4172
 
4702
4173
 	pr_debug("%s: start = 0x%012llx, len = %llu\n",
4703
4174
 			__func__, (unsigned long long)instr->addr,
4704
4175
 			(unsigned long long)instr->len);
4705
4176
 
4706
-	if (check_offs_len(mtd, instr->addr, instr->len))
4177
+	if (check_offs_len(chip, instr->addr, instr->len))
4707
4178
 		return -EINVAL;
4708
4179
 
4709
4180
 	/* Grab the lock and see if the device is available */
4710
-	nand_get_device(mtd, FL_ERASING);
4181
+	nand_get_device(chip);
4711
4182
 
4712
4183
 	/* Shift to get first page */
4713
4184
 	page = (int)(instr->addr >> chip->page_shift);
..
..
@@ -4717,10 +4188,10 @@
4717
4188
 	pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
4718
4189
 
4719
4190
 	/* Select the NAND device */
4720
-	chip->select_chip(mtd, chipnr);
4191
+	nand_select_target(chip, chipnr);
4721
4192
 
4722
4193
 	/* Check, if it is write protected */
4723
-	if (nand_check_wp(mtd)) {
4194
+	if (nand_check_wp(chip)) {
4724
4195
 		pr_debug("%s: device is write protected!\n",
4725
4196
 				__func__);
4726
4197
 		ret = -EIO;
..
..
@@ -4732,7 +4203,7 @@
4732
4203
 
4733
4204
 	while (len) {
4734
4205
 		/* Check if we have a bad block, we do not erase bad blocks! */
4735
-		if (nand_block_checkbad(mtd, ((loff_t) page) <<
4206
+		if (nand_block_checkbad(chip, ((loff_t) page) <<
4736
4207
 					chip->page_shift, allowbbt)) {
4737
4208
 			pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
4738
4209
 				    __func__, page);
..
..
@@ -4744,17 +4215,15 @@
4744
4215
 		 * Invalidate the page cache, if we erase the block which
4745
4216
 		 * contains the current cached page.
4746
4217
 		 */
4747
-		if (page <= chip->pagebuf && chip->pagebuf <
4218
+		if (page <= chip->pagecache.page && chip->pagecache.page <
4748
4219
 		    (page + pages_per_block))
4749
-			chip->pagebuf = -1;
4220
+			chip->pagecache.page = -1;
4750
4221
 
4751
-		status = chip->erase(mtd, page & chip->pagemask);
4752
-
4753
-		/* See if block erase succeeded */
4754
-		if (status) {
4222
+		ret = nand_erase_op(chip, (page & chip->pagemask) >>
4223
+				    (chip->phys_erase_shift - chip->page_shift));
4224
+		if (ret) {
4755
4225
 			pr_debug("%s: failed erase, page 0x%08x\n",
4756
4226
 					__func__, page);
4757
-			ret = -EIO;
4758
4227
 			instr->fail_addr =
4759
4228
 				((loff_t)page << chip->page_shift);
4760
4229
 			goto erase_exit;
..
..
@@ -4767,8 +4236,8 @@
4767
4236
 		/* Check, if we cross a chip boundary */
4768
4237
 		if (len && !(page & chip->pagemask)) {
4769
4238
 			chipnr++;
4770
-			chip->select_chip(mtd, -1);
4771
-			chip->select_chip(mtd, chipnr);
4239
+			nand_deselect_target(chip);
4240
+			nand_select_target(chip, chipnr);
4772
4241
 		}
4773
4242
 	}
4774
4243
 
..
..
@@ -4776,8 +4245,8 @@
4776
4245
 erase_exit:
4777
4246
 
4778
4247
 	/* Deselect and wake up anyone waiting on the device */
4779
-	chip->select_chip(mtd, -1);
4780
-	nand_release_device(mtd);
4248
+	nand_deselect_target(chip);
4249
+	nand_release_device(chip);
4781
4250
 
4782
4251
 	/* Return more or less happy */
4783
4252
 	return ret;
..
..
@@ -4791,12 +4260,14 @@
4791
4260
  */
4792
4261
 static void nand_sync(struct mtd_info *mtd)
4793
4262
 {
4263
+	struct nand_chip *chip = mtd_to_nand(mtd);
4264
+
4794
4265
 	pr_debug("%s: called\n", __func__);
4795
4266
 
4796
4267
 	/* Grab the lock and see if the device is available */
4797
-	nand_get_device(mtd, FL_SYNCING);
4268
+	nand_get_device(chip);
4798
4269
 	/* Release it and go back */
4799
-	nand_release_device(mtd);
4270
+	nand_release_device(chip);
4800
4271
 }
4801
4272
 
4802
4273
 /**
..
..
@@ -4811,13 +4282,14 @@
4811
4282
 	int ret;
4812
4283
 
4813
4284
 	/* Select the NAND device */
4814
-	nand_get_device(mtd, FL_READING);
4815
-	chip->select_chip(mtd, chipnr);
4285
+	nand_get_device(chip);
4816
4286
 
4817
-	ret = nand_block_checkbad(mtd, offs, 0);
4287
+	nand_select_target(chip, chipnr);
4818
4288
 
4819
-	chip->select_chip(mtd, -1);
4820
-	nand_release_device(mtd);
4289
+	ret = nand_block_checkbad(chip, offs, 0);
4290
+
4291
+	nand_deselect_target(chip);
4292
+	nand_release_device(chip);
4821
4293
 
4822
4294
 	return ret;
4823
4295
 }
..
..
@@ -4839,97 +4311,28 @@
4839
4311
 		return ret;
4840
4312
 	}
4841
4313
 
4842
-	return nand_block_markbad_lowlevel(mtd, ofs);
4314
+	return nand_block_markbad_lowlevel(mtd_to_nand(mtd), ofs);
4843
4315
 }
4844
-
4845
-/**
4846
- * nand_max_bad_blocks - [MTD Interface] Max number of bad blocks for an mtd
4847
- * @mtd: MTD device structure
4848
- * @ofs: offset relative to mtd start
4849
- * @len: length of mtd
4850
- */
4851
-static int nand_max_bad_blocks(struct mtd_info *mtd, loff_t ofs, size_t len)
4852
-{
4853
-	struct nand_chip *chip = mtd_to_nand(mtd);
4854
-	u32 part_start_block;
4855
-	u32 part_end_block;
4856
-	u32 part_start_die;
4857
-	u32 part_end_die;
4858
-
4859
-	/*
4860
-	 * max_bb_per_die and blocks_per_die used to determine
4861
-	 * the maximum bad block count.
4862
-	 */
4863
-	if (!chip->max_bb_per_die || !chip->blocks_per_die)
4864
-		return -ENOTSUPP;
4865
-
4866
-	/* Get the start and end of the partition in erase blocks. */
4867
-	part_start_block = mtd_div_by_eb(ofs, mtd);
4868
-	part_end_block = mtd_div_by_eb(len, mtd) + part_start_block - 1;
4869
-
4870
-	/* Get the start and end LUNs of the partition. */
4871
-	part_start_die = part_start_block / chip->blocks_per_die;
4872
-	part_end_die = part_end_block / chip->blocks_per_die;
4873
-
4874
-	/*
4875
-	 * Look up the bad blocks per unit and multiply by the number of units
4876
-	 * that the partition spans.
4877
-	 */
4878
-	return chip->max_bb_per_die * (part_end_die - part_start_die + 1);
4879
-}
4880
-
4881
-/**
4882
- * nand_default_set_features- [REPLACEABLE] set NAND chip features
4883
- * @mtd: MTD device structure
4884
- * @chip: nand chip info structure
4885
- * @addr: feature address.
4886
- * @subfeature_param: the subfeature parameters, a four bytes array.
4887
- */
4888
-static int nand_default_set_features(struct mtd_info *mtd,
4889
-				     struct nand_chip *chip, int addr,
4890
-				     uint8_t *subfeature_param)
4891
-{
4892
-	return nand_set_features_op(chip, addr, subfeature_param);
4893
-}
4894
-
4895
-/**
4896
- * nand_default_get_features- [REPLACEABLE] get NAND chip features
4897
- * @mtd: MTD device structure
4898
- * @chip: nand chip info structure
4899
- * @addr: feature address.
4900
- * @subfeature_param: the subfeature parameters, a four bytes array.
4901
- */
4902
-static int nand_default_get_features(struct mtd_info *mtd,
4903
-				     struct nand_chip *chip, int addr,
4904
-				     uint8_t *subfeature_param)
4905
-{
4906
-	return nand_get_features_op(chip, addr, subfeature_param);
4907
-}
4908
-
4909
-/**
4910
- * nand_get_set_features_notsupp - set/get features stub returning -ENOTSUPP
4911
- * @mtd: MTD device structure
4912
- * @chip: nand chip info structure
4913
- * @addr: feature address.
4914
- * @subfeature_param: the subfeature parameters, a four bytes array.
4915
- *
4916
- * Should be used by NAND controller drivers that do not support the SET/GET
4917
- * FEATURES operations.
4918
- */
4919
-int nand_get_set_features_notsupp(struct mtd_info *mtd, struct nand_chip *chip,
4920
-				  int addr, u8 *subfeature_param)
4921
-{
4922
-	return -ENOTSUPP;
4923
-}
4924
-EXPORT_SYMBOL(nand_get_set_features_notsupp);
4925
4316
 
4926
4317
 /**
4927
4318
  * nand_suspend - [MTD Interface] Suspend the NAND flash
4928
4319
  * @mtd: MTD device structure
4320
+ *
4321
+ * Returns 0 for success or negative error code otherwise.
4929
4322
  */
4930
4323
 static int nand_suspend(struct mtd_info *mtd)
4931
4324
 {
4932
-	return nand_get_device(mtd, FL_PM_SUSPENDED);
4325
+	struct nand_chip *chip = mtd_to_nand(mtd);
4326
+	int ret = 0;
4327
+
4328
+	mutex_lock(&chip->lock);
4329
+	if (chip->ops.suspend)
4330
+		ret = chip->ops.suspend(chip);
4331
+	if (!ret)
4332
+		chip->suspended = 1;
4333
+	mutex_unlock(&chip->lock);
4334
+
4335
+	return ret;
4933
4336
 }
4934
4337
 
4935
4338
 /**
..
..
@@ -4940,11 +4343,18 @@
4940
4343
 {
4941
4344
 	struct nand_chip *chip = mtd_to_nand(mtd);
4942
4345
 
4943
-	if (chip->state == FL_PM_SUSPENDED)
4944
-		nand_release_device(mtd);
4945
-	else
4346
+	mutex_lock(&chip->lock);
4347
+	if (chip->suspended) {
4348
+		if (chip->ops.resume)
4349
+			chip->ops.resume(chip);
4350
+		chip->suspended = 0;
4351
+	} else {
4946
4352
 		pr_err("%s called for a chip which is not in suspended state\n",
4947
4353
 			__func__);
4354
+	}
4355
+	mutex_unlock(&chip->lock);
4356
+
4357
+	wake_up_all(&chip->resume_wq);
4948
4358
 }
4949
4359
 
4950
4360
 /**
..
..
@@ -4954,62 +4364,58 @@
4954
4364
  */
4955
4365
 static void nand_shutdown(struct mtd_info *mtd)
4956
4366
 {
4957
-	nand_get_device(mtd, FL_PM_SUSPENDED);
4367
+	nand_suspend(mtd);
4368
+}
4369
+
4370
+/**
4371
+ * nand_lock - [MTD Interface] Lock the NAND flash
4372
+ * @mtd: MTD device structure
4373
+ * @ofs: offset byte address
4374
+ * @len: number of bytes to lock (must be a multiple of block/page size)
4375
+ */
4376
+static int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
4377
+{
4378
+	struct nand_chip *chip = mtd_to_nand(mtd);
4379
+
4380
+	if (!chip->ops.lock_area)
4381
+		return -ENOTSUPP;
4382
+
4383
+	return chip->ops.lock_area(chip, ofs, len);
4384
+}
4385
+
4386
+/**
4387
+ * nand_unlock - [MTD Interface] Unlock the NAND flash
4388
+ * @mtd: MTD device structure
4389
+ * @ofs: offset byte address
4390
+ * @len: number of bytes to unlock (must be a multiple of block/page size)
4391
+ */
4392
+static int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
4393
+{
4394
+	struct nand_chip *chip = mtd_to_nand(mtd);
4395
+
4396
+	if (!chip->ops.unlock_area)
4397
+		return -ENOTSUPP;
4398
+
4399
+	return chip->ops.unlock_area(chip, ofs, len);
4958
4400
 }
4959
4401
 
4960
4402
 /* Set default functions */
4961
4403
 static void nand_set_defaults(struct nand_chip *chip)
4962
4404
 {
4963
-	unsigned int busw = chip->options & NAND_BUSWIDTH_16;
4964
-
4965
-	/* check for proper chip_delay setup, set 20us if not */
4966
-	if (!chip->chip_delay)
4967
-		chip->chip_delay = 20;
4968
-
4969
-	/* check, if a user supplied command function given */
4970
-	if (!chip->cmdfunc && !chip->exec_op)
4971
-		chip->cmdfunc = nand_command;
4972
-
4973
-	/* check, if a user supplied wait function given */
4974
-	if (chip->waitfunc == NULL)
4975
-		chip->waitfunc = nand_wait;
4976
-
4977
-	if (!chip->select_chip)
4978
-		chip->select_chip = nand_select_chip;
4979
-
4980
-	/* set for ONFI nand */
4981
-	if (!chip->set_features)
4982
-		chip->set_features = nand_default_set_features;
4983
-	if (!chip->get_features)
4984
-		chip->get_features = nand_default_get_features;
4985
-
4986
-	/* If called twice, pointers that depend on busw may need to be reset */
4987
-	if (!chip->read_byte || chip->read_byte == nand_read_byte)
4988
-		chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
4989
-	if (!chip->read_word)
4990
-		chip->read_word = nand_read_word;
4991
-	if (!chip->block_bad)
4992
-		chip->block_bad = nand_block_bad;
4993
-	if (!chip->block_markbad)
4994
-		chip->block_markbad = nand_default_block_markbad;
4995
-	if (!chip->write_buf || chip->write_buf == nand_write_buf)
4996
-		chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
4997
-	if (!chip->write_byte || chip->write_byte == nand_write_byte)
4998
-		chip->write_byte = busw ? nand_write_byte16 : nand_write_byte;
4999
-	if (!chip->read_buf || chip->read_buf == nand_read_buf)
5000
-		chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
5001
-
4405
+	/* If no controller is provided, use the dummy, legacy one. */
5002
4406
 	if (!chip->controller) {
5003
-		chip->controller = &chip->dummy_controller;
4407
+		chip->controller = &chip->legacy.dummy_controller;
5004
4408
 		nand_controller_init(chip->controller);
5005
4409
 	}
4410
+
4411
+	nand_legacy_set_defaults(chip);
5006
4412
 
5007
4413
 	if (!chip->buf_align)
5008
4414
 		chip->buf_align = 1;
5009
4415
 }
5010
4416
 
5011
4417
 /* Sanitize ONFI strings so we can safely print them */
5012
-static void sanitize_string(uint8_t *s, size_t len)
4418
+void sanitize_string(uint8_t *s, size_t len)
5013
4419
 {
5014
4420
 	ssize_t i;
5015
4421
 
..
..
@@ -5024,390 +4430,6 @@
5024
4430
 
5025
4431
 	/* Remove trailing spaces */
5026
4432
 	strim(s);
5027
-}
5028
-
5029
-static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
5030
-{
5031
-	int i;
5032
-	while (len--) {
5033
-		crc ^= *p++ << 8;
5034
-		for (i = 0; i < 8; i++)
5035
-			crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
5036
-	}
5037
-
5038
-	return crc;
5039
-}
5040
-
5041
-/* Parse the Extended Parameter Page. */
5042
-static int nand_flash_detect_ext_param_page(struct nand_chip *chip,
5043
-					    struct nand_onfi_params *p)
5044
-{
5045
-	struct onfi_ext_param_page *ep;
5046
-	struct onfi_ext_section *s;
5047
-	struct onfi_ext_ecc_info *ecc;
5048
-	uint8_t *cursor;
5049
-	int ret;
5050
-	int len;
5051
-	int i;
5052
-
5053
-	len = le16_to_cpu(p->ext_param_page_length) * 16;
5054
-	ep = kmalloc(len, GFP_KERNEL);
5055
-	if (!ep)
5056
-		return -ENOMEM;
5057
-
5058
-	/* Send our own NAND_CMD_PARAM. */
5059
-	ret = nand_read_param_page_op(chip, 0, NULL, 0);
5060
-	if (ret)
5061
-		goto ext_out;
5062
-
5063
-	/* Use the Change Read Column command to skip the ONFI param pages. */
5064
-	ret = nand_change_read_column_op(chip,
5065
-					 sizeof(*p) * p->num_of_param_pages,
5066
-					 ep, len, true);
5067
-	if (ret)
5068
-		goto ext_out;
5069
-
5070
-	ret = -EINVAL;
5071
-	if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
5072
-		!= le16_to_cpu(ep->crc))) {
5073
-		pr_debug("fail in the CRC.\n");
5074
-		goto ext_out;
5075
-	}
5076
-
5077
-	/*
5078
-	 * Check the signature.
5079
-	 * Do not strictly follow the ONFI spec, maybe changed in future.
5080
-	 */
5081
-	if (strncmp(ep->sig, "EPPS", 4)) {
5082
-		pr_debug("The signature is invalid.\n");
5083
-		goto ext_out;
5084
-	}
5085
-
5086
-	/* find the ECC section. */
5087
-	cursor = (uint8_t *)(ep + 1);
5088
-	for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
5089
-		s = ep->sections + i;
5090
-		if (s->type == ONFI_SECTION_TYPE_2)
5091
-			break;
5092
-		cursor += s->length * 16;
5093
-	}
5094
-	if (i == ONFI_EXT_SECTION_MAX) {
5095
-		pr_debug("We can not find the ECC section.\n");
5096
-		goto ext_out;
5097
-	}
5098
-
5099
-	/* get the info we want. */
5100
-	ecc = (struct onfi_ext_ecc_info *)cursor;
5101
-
5102
-	if (!ecc->codeword_size) {
5103
-		pr_debug("Invalid codeword size\n");
5104
-		goto ext_out;
5105
-	}
5106
-
5107
-	chip->ecc_strength_ds = ecc->ecc_bits;
5108
-	chip->ecc_step_ds = 1 << ecc->codeword_size;
5109
-	ret = 0;
5110
-
5111
-ext_out:
5112
-	kfree(ep);
5113
-	return ret;
5114
-}
5115
-
5116
-/*
5117
- * Recover data with bit-wise majority
5118
- */
5119
-static void nand_bit_wise_majority(const void **srcbufs,
5120
-				   unsigned int nsrcbufs,
5121
-				   void *dstbuf,
5122
-				   unsigned int bufsize)
5123
-{
5124
-	int i, j, k;
5125
-
5126
-	for (i = 0; i < bufsize; i++) {
5127
-		u8 val = 0;
5128
-
5129
-		for (j = 0; j < 8; j++) {
5130
-			unsigned int cnt = 0;
5131
-
5132
-			for (k = 0; k < nsrcbufs; k++) {
5133
-				const u8 *srcbuf = srcbufs[k];
5134
-
5135
-				if (srcbuf[i] & BIT(j))
5136
-					cnt++;
5137
-			}
5138
-
5139
-			if (cnt > nsrcbufs / 2)
5140
-				val |= BIT(j);
5141
-		}
5142
-
5143
-		((u8 *)dstbuf)[i] = val;
5144
-	}
5145
-}
5146
-
5147
-/*
5148
- * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
5149
- */
5150
-static int nand_flash_detect_onfi(struct nand_chip *chip)
5151
-{
5152
-	struct mtd_info *mtd = nand_to_mtd(chip);
5153
-	struct nand_onfi_params *p;
5154
-	struct onfi_params *onfi;
5155
-	int onfi_version = 0;
5156
-	char id[4];
5157
-	int i, ret, val;
5158
-
5159
-	/* Try ONFI for unknown chip or LP */
5160
-	ret = nand_readid_op(chip, 0x20, id, sizeof(id));
5161
-	if (ret || strncmp(id, "ONFI", 4))
5162
-		return 0;
5163
-
5164
-	/* ONFI chip: allocate a buffer to hold its parameter page */
5165
-	p = kzalloc((sizeof(*p) * 3), GFP_KERNEL);
5166
-	if (!p)
5167
-		return -ENOMEM;
5168
-
5169
-	ret = nand_read_param_page_op(chip, 0, NULL, 0);
5170
-	if (ret) {
5171
-		ret = 0;
5172
-		goto free_onfi_param_page;
5173
-	}
5174
-
5175
-	for (i = 0; i < 3; i++) {
5176
-		ret = nand_read_data_op(chip, &p[i], sizeof(*p), true);
5177
-		if (ret) {
5178
-			ret = 0;
5179
-			goto free_onfi_param_page;
5180
-		}
5181
-
5182
-		if (onfi_crc16(ONFI_CRC_BASE, (u8 *)&p[i], 254) ==
5183
-				le16_to_cpu(p->crc)) {
5184
-			if (i)
5185
-				memcpy(p, &p[i], sizeof(*p));
5186
-			break;
5187
-		}
5188
-	}
5189
-
5190
-	if (i == 3) {
5191
-		const void *srcbufs[3] = {p, p + 1, p + 2};
5192
-
5193
-		pr_warn("Could not find a valid ONFI parameter page, trying bit-wise majority to recover it\n");
5194
-		nand_bit_wise_majority(srcbufs, ARRAY_SIZE(srcbufs), p,
5195
-				       sizeof(*p));
5196
-
5197
-		if (onfi_crc16(ONFI_CRC_BASE, (u8 *)p, 254) !=
5198
-				le16_to_cpu(p->crc)) {
5199
-			pr_err("ONFI parameter recovery failed, aborting\n");
5200
-			goto free_onfi_param_page;
5201
-		}
5202
-	}
5203
-
5204
-	if (chip->manufacturer.desc && chip->manufacturer.desc->ops &&
5205
-	    chip->manufacturer.desc->ops->fixup_onfi_param_page)
5206
-		chip->manufacturer.desc->ops->fixup_onfi_param_page(chip, p);
5207
-
5208
-	/* Check version */
5209
-	val = le16_to_cpu(p->revision);
5210
-	if (val & ONFI_VERSION_2_3)
5211
-		onfi_version = 23;
5212
-	else if (val & ONFI_VERSION_2_2)
5213
-		onfi_version = 22;
5214
-	else if (val & ONFI_VERSION_2_1)
5215
-		onfi_version = 21;
5216
-	else if (val & ONFI_VERSION_2_0)
5217
-		onfi_version = 20;
5218
-	else if (val & ONFI_VERSION_1_0)
5219
-		onfi_version = 10;
5220
-
5221
-	if (!onfi_version) {
5222
-		pr_info("unsupported ONFI version: %d\n", val);
5223
-		goto free_onfi_param_page;
5224
-	}
5225
-
5226
-	sanitize_string(p->manufacturer, sizeof(p->manufacturer));
5227
-	sanitize_string(p->model, sizeof(p->model));
5228
-	chip->parameters.model = kstrdup(p->model, GFP_KERNEL);
5229
-	if (!chip->parameters.model) {
5230
-		ret = -ENOMEM;
5231
-		goto free_onfi_param_page;
5232
-	}
5233
-
5234
-	mtd->writesize = le32_to_cpu(p->byte_per_page);
5235
-
5236
-	/*
5237
-	 * pages_per_block and blocks_per_lun may not be a power-of-2 size
5238
-	 * (don't ask me who thought of this...). MTD assumes that these
5239
-	 * dimensions will be power-of-2, so just truncate the remaining area.
5240
-	 */
5241
-	mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
5242
-	mtd->erasesize *= mtd->writesize;
5243
-
5244
-	mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
5245
-
5246
-	/* See erasesize comment */
5247
-	chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
5248
-	chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
5249
-	chip->bits_per_cell = p->bits_per_cell;
5250
-
5251
-	chip->max_bb_per_die = le16_to_cpu(p->bb_per_lun);
5252
-	chip->blocks_per_die = le32_to_cpu(p->blocks_per_lun);
5253
-
5254
-	if (le16_to_cpu(p->features) & ONFI_FEATURE_16_BIT_BUS)
5255
-		chip->options |= NAND_BUSWIDTH_16;
5256
-
5257
-	if (p->ecc_bits != 0xff) {
5258
-		chip->ecc_strength_ds = p->ecc_bits;
5259
-		chip->ecc_step_ds = 512;
5260
-	} else if (onfi_version >= 21 &&
5261
-		(le16_to_cpu(p->features) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
5262
-
5263
-		/*
5264
-		 * The nand_flash_detect_ext_param_page() uses the
5265
-		 * Change Read Column command which maybe not supported
5266
-		 * by the chip->cmdfunc. So try to update the chip->cmdfunc
5267
-		 * now. We do not replace user supplied command function.
5268
-		 */
5269
-		if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
5270
-			chip->cmdfunc = nand_command_lp;
5271
-
5272
-		/* The Extended Parameter Page is supported since ONFI 2.1. */
5273
-		if (nand_flash_detect_ext_param_page(chip, p))
5274
-			pr_warn("Failed to detect ONFI extended param page\n");
5275
-	} else {
5276
-		pr_warn("Could not retrieve ONFI ECC requirements\n");
5277
-	}
5278
-
5279
-	/* Save some parameters from the parameter page for future use */
5280
-	if (le16_to_cpu(p->opt_cmd) & ONFI_OPT_CMD_SET_GET_FEATURES) {
5281
-		chip->parameters.supports_set_get_features = true;
5282
-		bitmap_set(chip->parameters.get_feature_list,
5283
-			   ONFI_FEATURE_ADDR_TIMING_MODE, 1);
5284
-		bitmap_set(chip->parameters.set_feature_list,
5285
-			   ONFI_FEATURE_ADDR_TIMING_MODE, 1);
5286
-	}
5287
-
5288
-	onfi = kzalloc(sizeof(*onfi), GFP_KERNEL);
5289
-	if (!onfi) {
5290
-		ret = -ENOMEM;
5291
-		goto free_model;
5292
-	}
5293
-
5294
-	onfi->version = onfi_version;
5295
-	onfi->tPROG = le16_to_cpu(p->t_prog);
5296
-	onfi->tBERS = le16_to_cpu(p->t_bers);
5297
-	onfi->tR = le16_to_cpu(p->t_r);
5298
-	onfi->tCCS = le16_to_cpu(p->t_ccs);
5299
-	onfi->async_timing_mode = le16_to_cpu(p->async_timing_mode);
5300
-	onfi->vendor_revision = le16_to_cpu(p->vendor_revision);
5301
-	memcpy(onfi->vendor, p->vendor, sizeof(p->vendor));
5302
-	chip->parameters.onfi = onfi;
5303
-
5304
-	/* Identification done, free the full ONFI parameter page and exit */
5305
-	kfree(p);
5306
-
5307
-	return 1;
5308
-
5309
-free_model:
5310
-	kfree(chip->parameters.model);
5311
-free_onfi_param_page:
5312
-	kfree(p);
5313
-
5314
-	return ret;
5315
-}
5316
-
5317
-/*
5318
- * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
5319
- */
5320
-static int nand_flash_detect_jedec(struct nand_chip *chip)
5321
-{
5322
-	struct mtd_info *mtd = nand_to_mtd(chip);
5323
-	struct nand_jedec_params *p;
5324
-	struct jedec_ecc_info *ecc;
5325
-	int jedec_version = 0;
5326
-	char id[5];
5327
-	int i, val, ret;
5328
-
5329
-	/* Try JEDEC for unknown chip or LP */
5330
-	ret = nand_readid_op(chip, 0x40, id, sizeof(id));
5331
-	if (ret || strncmp(id, "JEDEC", sizeof(id)))
5332
-		return 0;
5333
-
5334
-	/* JEDEC chip: allocate a buffer to hold its parameter page */
5335
-	p = kzalloc(sizeof(*p), GFP_KERNEL);
5336
-	if (!p)
5337
-		return -ENOMEM;
5338
-
5339
-	ret = nand_read_param_page_op(chip, 0x40, NULL, 0);
5340
-	if (ret) {
5341
-		ret = 0;
5342
-		goto free_jedec_param_page;
5343
-	}
5344
-
5345
-	for (i = 0; i < 3; i++) {
5346
-		ret = nand_read_data_op(chip, p, sizeof(*p), true);
5347
-		if (ret) {
5348
-			ret = 0;
5349
-			goto free_jedec_param_page;
5350
-		}
5351
-
5352
-		if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) ==
5353
-				le16_to_cpu(p->crc))
5354
-			break;
5355
-	}
5356
-
5357
-	if (i == 3) {
5358
-		pr_err("Could not find valid JEDEC parameter page; aborting\n");
5359
-		goto free_jedec_param_page;
5360
-	}
5361
-
5362
-	/* Check version */
5363
-	val = le16_to_cpu(p->revision);
5364
-	if (val & (1 << 2))
5365
-		jedec_version = 10;
5366
-	else if (val & (1 << 1))
5367
-		jedec_version = 1; /* vendor specific version */
5368
-
5369
-	if (!jedec_version) {
5370
-		pr_info("unsupported JEDEC version: %d\n", val);
5371
-		goto free_jedec_param_page;
5372
-	}
5373
-
5374
-	sanitize_string(p->manufacturer, sizeof(p->manufacturer));
5375
-	sanitize_string(p->model, sizeof(p->model));
5376
-	chip->parameters.model = kstrdup(p->model, GFP_KERNEL);
5377
-	if (!chip->parameters.model) {
5378
-		ret = -ENOMEM;
5379
-		goto free_jedec_param_page;
5380
-	}
5381
-
5382
-	mtd->writesize = le32_to_cpu(p->byte_per_page);
5383
-
5384
-	/* Please reference to the comment for nand_flash_detect_onfi. */
5385
-	mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
5386
-	mtd->erasesize *= mtd->writesize;
5387
-
5388
-	mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
5389
-
5390
-	/* Please reference to the comment for nand_flash_detect_onfi. */
5391
-	chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
5392
-	chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
5393
-	chip->bits_per_cell = p->bits_per_cell;
5394
-
5395
-	if (le16_to_cpu(p->features) & JEDEC_FEATURE_16_BIT_BUS)
5396
-		chip->options |= NAND_BUSWIDTH_16;
5397
-
5398
-	/* ECC info */
5399
-	ecc = &p->ecc_info[0];
5400
-
5401
-	if (ecc->codeword_size >= 9) {
5402
-		chip->ecc_strength_ds = ecc->ecc_bits;
5403
-		chip->ecc_step_ds = 1 << ecc->codeword_size;
5404
-	} else {
5405
-		pr_warn("Invalid codeword size\n");
5406
-	}
5407
-
5408
-free_jedec_param_page:
5409
-	kfree(p);
5410
-	return ret;
5411
4433
 }
5412
4434
 
5413
4435
 /*
..
..
@@ -5486,21 +4508,29 @@
5486
4508
  */
5487
4509
 void nand_decode_ext_id(struct nand_chip *chip)
5488
4510
 {
4511
+	struct nand_memory_organization *memorg;
5489
4512
 	struct mtd_info *mtd = nand_to_mtd(chip);
5490
4513
 	int extid;
5491
4514
 	u8 *id_data = chip->id.data;
4515
+
4516
+	memorg = nanddev_get_memorg(&chip->base);
4517
+
5492
4518
 	/* The 3rd id byte holds MLC / multichip data */
5493
-	chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
4519
+	memorg->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
5494
4520
 	/* The 4th id byte is the important one */
5495
4521
 	extid = id_data[3];
5496
4522
 
5497
4523
 	/* Calc pagesize */
5498
-	mtd->writesize = 1024 << (extid & 0x03);
4524
+	memorg->pagesize = 1024 << (extid & 0x03);
4525
+	mtd->writesize = memorg->pagesize;
5499
4526
 	extid >>= 2;
5500
4527
 	/* Calc oobsize */
5501
-	mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
4528
+	memorg->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
4529
+	mtd->oobsize = memorg->oobsize;
5502
4530
 	extid >>= 2;
5503
4531
 	/* Calc blocksize. Blocksize is multiples of 64KiB */
4532
+	memorg->pages_per_eraseblock = ((64 * 1024) << (extid & 0x03)) /
4533
+				       memorg->pagesize;
5504
4534
 	mtd->erasesize = (64 * 1024) << (extid & 0x03);
5505
4535
 	extid >>= 2;
5506
4536
 	/* Get buswidth information */
..
..
@@ -5517,13 +4547,19 @@
5517
4547
 static void nand_decode_id(struct nand_chip *chip, struct nand_flash_dev *type)
5518
4548
 {
5519
4549
 	struct mtd_info *mtd = nand_to_mtd(chip);
4550
+	struct nand_memory_organization *memorg;
5520
4551
 
4552
+	memorg = nanddev_get_memorg(&chip->base);
4553
+
4554
+	memorg->pages_per_eraseblock = type->erasesize / type->pagesize;
5521
4555
 	mtd->erasesize = type->erasesize;
5522
-	mtd->writesize = type->pagesize;
5523
-	mtd->oobsize = mtd->writesize / 32;
4556
+	memorg->pagesize = type->pagesize;
4557
+	mtd->writesize = memorg->pagesize;
4558
+	memorg->oobsize = memorg->pagesize / 32;
4559
+	mtd->oobsize = memorg->oobsize;
5524
4560
 
5525
4561
 	/* All legacy ID NAND are small-page, SLC */
5526
-	chip->bits_per_cell = 1;
4562
+	memorg->bits_per_cell = 1;
5527
4563
 }
5528
4564
 
5529
4565
 /*
..
..
@@ -5537,9 +4573,9 @@
5537
4573
 
5538
4574
 	/* Set the bad block position */
5539
4575
 	if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
5540
-		chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
4576
+		chip->badblockpos = NAND_BBM_POS_LARGE;
5541
4577
 	else
5542
-		chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
4578
+		chip->badblockpos = NAND_BBM_POS_SMALL;
5543
4579
 }
5544
4580
 
5545
4581
 static inline bool is_full_id_nand(struct nand_flash_dev *type)
..
..
@@ -5550,21 +4586,32 @@
5550
4586
 static bool find_full_id_nand(struct nand_chip *chip,
5551
4587
 			      struct nand_flash_dev *type)
5552
4588
 {
4589
+	struct nand_device *base = &chip->base;
4590
+	struct nand_ecc_props requirements;
5553
4591
 	struct mtd_info *mtd = nand_to_mtd(chip);
4592
+	struct nand_memory_organization *memorg;
5554
4593
 	u8 *id_data = chip->id.data;
5555
4594
 
5556
-	if (!strncmp(type->id, id_data, type->id_len)) {
5557
-		mtd->writesize = type->pagesize;
5558
-		mtd->erasesize = type->erasesize;
5559
-		mtd->oobsize = type->oobsize;
4595
+	memorg = nanddev_get_memorg(&chip->base);
5560
4596
 
5561
-		chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
5562
-		chip->chipsize = (uint64_t)type->chipsize << 20;
4597
+	if (!strncmp(type->id, id_data, type->id_len)) {
4598
+		memorg->pagesize = type->pagesize;
4599
+		mtd->writesize = memorg->pagesize;
4600
+		memorg->pages_per_eraseblock = type->erasesize /
4601
+					       type->pagesize;
4602
+		mtd->erasesize = type->erasesize;
4603
+		memorg->oobsize = type->oobsize;
4604
+		mtd->oobsize = memorg->oobsize;
4605
+
4606
+		memorg->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
4607
+		memorg->eraseblocks_per_lun =
4608
+			DIV_ROUND_DOWN_ULL((u64)type->chipsize << 20,
4609
+					   memorg->pagesize *
4610
+					   memorg->pages_per_eraseblock);
5563
4611
 		chip->options |= type->options;
5564
-		chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
5565
-		chip->ecc_step_ds = NAND_ECC_STEP(type);
5566
-		chip->onfi_timing_mode_default =
5567
-					type->onfi_timing_mode_default;
4612
+		requirements.strength = NAND_ECC_STRENGTH(type);
4613
+		requirements.step_size = NAND_ECC_STEP(type);
4614
+		nanddev_set_ecc_requirements(base, &requirements);
5568
4615
 
5569
4616
 		chip->parameters.model = kstrdup(type->name, GFP_KERNEL);
5570
4617
 		if (!chip->parameters.model)
..
..
@@ -5588,8 +4635,12 @@
5588
4635
 	 */
5589
4636
 	if (chip->manufacturer.desc && chip->manufacturer.desc->ops &&
5590
4637
 	    chip->manufacturer.desc->ops->detect) {
4638
+		struct nand_memory_organization *memorg;
4639
+
4640
+		memorg = nanddev_get_memorg(&chip->base);
4641
+
5591
4642
 		/* The 3rd id byte holds MLC / multichip data */
5592
-		chip->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]);
4643
+		memorg->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]);
5593
4644
 		chip->manufacturer.desc->ops->detect(chip);
5594
4645
 	} else {
5595
4646
 		nand_decode_ext_id(chip);
..
..
@@ -5625,16 +4676,32 @@
5625
4676
 		chip->manufacturer.desc->ops->cleanup(chip);
5626
4677
 }
5627
4678
 
4679
+static const char *
4680
+nand_manufacturer_name(const struct nand_manufacturer_desc *manufacturer_desc)
4681
+{
4682
+	return manufacturer_desc ? manufacturer_desc->name : "Unknown";
4683
+}
4684
+
5628
4685
 /*
5629
4686
  * Get the flash and manufacturer id and lookup if the type is supported.
5630
4687
  */
5631
4688
 static int nand_detect(struct nand_chip *chip, struct nand_flash_dev *type)
5632
4689
 {
5633
-	const struct nand_manufacturer *manufacturer;
4690
+	const struct nand_manufacturer_desc *manufacturer_desc;
5634
4691
 	struct mtd_info *mtd = nand_to_mtd(chip);
4692
+	struct nand_memory_organization *memorg;
5635
4693
 	int busw, ret;
5636
4694
 	u8 *id_data = chip->id.data;
5637
4695
 	u8 maf_id, dev_id;
4696
+	u64 targetsize;
4697
+
4698
+	/*
4699
+	 * Let's start by initializing memorg fields that might be left
4700
+	 * unassigned by the ID-based detection logic.
4701
+	 */
4702
+	memorg = nanddev_get_memorg(&chip->base);
4703
+	memorg->planes_per_lun = 1;
4704
+	memorg->luns_per_target = 1;
5638
4705
 
5639
4706
 	/*
5640
4707
 	 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
..
..
@@ -5645,7 +4712,7 @@
5645
4712
 		return ret;
5646
4713
 
5647
4714
 	/* Select the device */
5648
-	chip->select_chip(mtd, 0);
4715
+	nand_select_target(chip, 0);
5649
4716
 
5650
4717
 	/* Send the command for reading device ID */
5651
4718
 	ret = nand_readid_op(chip, 0, id_data, 2);
..
..
@@ -5677,8 +4744,8 @@
5677
4744
 	chip->id.len = nand_id_len(id_data, ARRAY_SIZE(chip->id.data));
5678
4745
 
5679
4746
 	/* Try to identify manufacturer */
5680
-	manufacturer = nand_get_manufacturer(maf_id);
5681
-	chip->manufacturer.desc = manufacturer;
4747
+	manufacturer_desc = nand_get_manufacturer_desc(maf_id);
4748
+	chip->manufacturer.desc = manufacturer_desc;
5682
4749
 
5683
4750
 	if (!type)
5684
4751
 		type = nand_flash_ids;
..
..
@@ -5709,14 +4776,14 @@
5709
4776
 
5710
4777
 	if (!type->name || !type->pagesize) {
5711
4778
 		/* Check if the chip is ONFI compliant */
5712
-		ret = nand_flash_detect_onfi(chip);
4779
+		ret = nand_onfi_detect(chip);
5713
4780
 		if (ret < 0)
5714
4781
 			return ret;
5715
4782
 		else if (ret)
5716
4783
 			goto ident_done;
5717
4784
 
5718
4785
 		/* Check if the chip is JEDEC compliant */
5719
-		ret = nand_flash_detect_jedec(chip);
4786
+		ret = nand_jedec_detect(chip);
5720
4787
 		if (ret < 0)
5721
4788
 			return ret;
5722
4789
 		else if (ret)
..
..
@@ -5730,8 +4797,6 @@
5730
4797
 	if (!chip->parameters.model)
5731
4798
 		return -ENOMEM;
5732
4799
 
5733
-	chip->chipsize = (uint64_t)type->chipsize << 20;
5734
-
5735
4800
 	if (!type->pagesize)
5736
4801
 		nand_manufacturer_detect(chip);
5737
4802
 	else
..
..
@@ -5739,6 +4804,11 @@
5739
4804
 
5740
4805
 	/* Get chip options */
5741
4806
 	chip->options |= type->options;
4807
+
4808
+	memorg->eraseblocks_per_lun =
4809
+			DIV_ROUND_DOWN_ULL((u64)type->chipsize << 20,
4810
+					   memorg->pagesize *
4811
+					   memorg->pages_per_eraseblock);
5742
4812
 
5743
4813
 ident_done:
5744
4814
 	if (!mtd->name)
..
..
@@ -5754,7 +4824,7 @@
5754
4824
 		 */
5755
4825
 		pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
5756
4826
 			maf_id, dev_id);
5757
-		pr_info("%s %s\n", nand_manufacturer_name(manufacturer),
4827
+		pr_info("%s %s\n", nand_manufacturer_name(manufacturer_desc),
5758
4828
 			mtd->name);
5759
4829
 		pr_warn("bus width %d instead of %d bits\n", busw ? 16 : 8,
5760
4830
 			(chip->options & NAND_BUSWIDTH_16) ? 16 : 8);
..
..
@@ -5768,14 +4838,15 @@
5768
4838
 	/* Calculate the address shift from the page size */
5769
4839
 	chip->page_shift = ffs(mtd->writesize) - 1;
5770
4840
 	/* Convert chipsize to number of pages per chip -1 */
5771
-	chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
4841
+	targetsize = nanddev_target_size(&chip->base);
4842
+	chip->pagemask = (targetsize >> chip->page_shift) - 1;
5772
4843
 
5773
4844
 	chip->bbt_erase_shift = chip->phys_erase_shift =
5774
4845
 		ffs(mtd->erasesize) - 1;
5775
-	if (chip->chipsize & 0xffffffff)
5776
-		chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
4846
+	if (targetsize & 0xffffffff)
4847
+		chip->chip_shift = ffs((unsigned)targetsize) - 1;
5777
4848
 	else {
5778
-		chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
4849
+		chip->chip_shift = ffs((unsigned)(targetsize >> 32));
5779
4850
 		chip->chip_shift += 32 - 1;
5780
4851
 	}
5781
4852
 
..
..
@@ -5783,18 +4854,15 @@
5783
4854
 		chip->options |= NAND_ROW_ADDR_3;
5784
4855
 
5785
4856
 	chip->badblockbits = 8;
5786
-	chip->erase = single_erase;
5787
4857
 
5788
-	/* Do not replace user supplied command function! */
5789
-	if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
5790
-		chip->cmdfunc = nand_command_lp;
4858
+	nand_legacy_adjust_cmdfunc(chip);
5791
4859
 
5792
4860
 	pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
5793
4861
 		maf_id, dev_id);
5794
-	pr_info("%s %s\n", nand_manufacturer_name(manufacturer),
4862
+	pr_info("%s %s\n", nand_manufacturer_name(manufacturer_desc),
5795
4863
 		chip->parameters.model);
5796
4864
 	pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
5797
-		(int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
4865
+		(int)(targetsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
5798
4866
 		mtd->erasesize >> 10, mtd->writesize, mtd->oobsize);
5799
4867
 	return 0;
5800
4868
 
..
..
@@ -5804,90 +4872,101 @@
5804
4872
 	return ret;
5805
4873
 }
5806
4874
 
5807
-static const char * const nand_ecc_modes[] = {
5808
-	[NAND_ECC_NONE]		= "none",
5809
-	[NAND_ECC_SOFT]		= "soft",
5810
-	[NAND_ECC_HW]		= "hw",
5811
-	[NAND_ECC_HW_SYNDROME]	= "hw_syndrome",
5812
-	[NAND_ECC_HW_OOB_FIRST]	= "hw_oob_first",
5813
-	[NAND_ECC_ON_DIE]	= "on-die",
5814
-};
5815
-
5816
-static int of_get_nand_ecc_mode(struct device_node *np)
4875
+static enum nand_ecc_engine_type
4876
+of_get_rawnand_ecc_engine_type_legacy(struct device_node *np)
5817
4877
 {
4878
+	enum nand_ecc_legacy_mode {
4879
+		NAND_ECC_INVALID,
4880
+		NAND_ECC_NONE,
4881
+		NAND_ECC_SOFT,
4882
+		NAND_ECC_SOFT_BCH,
4883
+		NAND_ECC_HW,
4884
+		NAND_ECC_HW_SYNDROME,
4885
+		NAND_ECC_ON_DIE,
4886
+	};
4887
+	const char * const nand_ecc_legacy_modes[] = {
4888
+		[NAND_ECC_NONE]		= "none",
4889
+		[NAND_ECC_SOFT]		= "soft",
4890
+		[NAND_ECC_SOFT_BCH]	= "soft_bch",
4891
+		[NAND_ECC_HW]		= "hw",
4892
+		[NAND_ECC_HW_SYNDROME]	= "hw_syndrome",
4893
+		[NAND_ECC_ON_DIE]	= "on-die",
4894
+	};
4895
+	enum nand_ecc_legacy_mode eng_type;
5818
4896
 	const char *pm;
5819
-	int err, i;
4897
+	int err;
5820
4898
 
5821
4899
 	err = of_property_read_string(np, "nand-ecc-mode", &pm);
5822
-	if (err < 0)
5823
-		return err;
4900
+	if (err)
4901
+		return NAND_ECC_ENGINE_TYPE_INVALID;
5824
4902
 
5825
-	for (i = 0; i < ARRAY_SIZE(nand_ecc_modes); i++)
5826
-		if (!strcasecmp(pm, nand_ecc_modes[i]))
5827
-			return i;
5828
-
5829
-	/*
5830
-	 * For backward compatibility we support few obsoleted values that don't
5831
-	 * have their mappings into nand_ecc_modes_t anymore (they were merged
5832
-	 * with other enums).
5833
-	 */
5834
-	if (!strcasecmp(pm, "soft_bch"))
5835
-		return NAND_ECC_SOFT;
5836
-
5837
-	return -ENODEV;
5838
-}
5839
-
5840
-static const char * const nand_ecc_algos[] = {
5841
-	[NAND_ECC_HAMMING]	= "hamming",
5842
-	[NAND_ECC_BCH]		= "bch",
5843
-	[NAND_ECC_RS]		= "rs",
5844
-};
5845
-
5846
-static int of_get_nand_ecc_algo(struct device_node *np)
5847
-{
5848
-	const char *pm;
5849
-	int err, i;
5850
-
5851
-	err = of_property_read_string(np, "nand-ecc-algo", &pm);
5852
-	if (!err) {
5853
-		for (i = NAND_ECC_HAMMING; i < ARRAY_SIZE(nand_ecc_algos); i++)
5854
-			if (!strcasecmp(pm, nand_ecc_algos[i]))
5855
-				return i;
5856
-		return -ENODEV;
4903
+	for (eng_type = NAND_ECC_NONE;
4904
+	     eng_type < ARRAY_SIZE(nand_ecc_legacy_modes); eng_type++) {
4905
+		if (!strcasecmp(pm, nand_ecc_legacy_modes[eng_type])) {
4906
+			switch (eng_type) {
4907
+			case NAND_ECC_NONE:
4908
+				return NAND_ECC_ENGINE_TYPE_NONE;
4909
+			case NAND_ECC_SOFT:
4910
+			case NAND_ECC_SOFT_BCH:
4911
+				return NAND_ECC_ENGINE_TYPE_SOFT;
4912
+			case NAND_ECC_HW:
4913
+			case NAND_ECC_HW_SYNDROME:
4914
+				return NAND_ECC_ENGINE_TYPE_ON_HOST;
4915
+			case NAND_ECC_ON_DIE:
4916
+				return NAND_ECC_ENGINE_TYPE_ON_DIE;
4917
+			default:
4918
+				break;
4919
+			}
4920
+		}
5857
4921
 	}
5858
4922
 
5859
-	/*
5860
-	 * For backward compatibility we also read "nand-ecc-mode" checking
5861
-	 * for some obsoleted values that were specifying ECC algorithm.
5862
-	 */
4923
+	return NAND_ECC_ENGINE_TYPE_INVALID;
4924
+}
4925
+
4926
+static enum nand_ecc_placement
4927
+of_get_rawnand_ecc_placement_legacy(struct device_node *np)
4928
+{
4929
+	const char *pm;
4930
+	int err;
4931
+
5863
4932
 	err = of_property_read_string(np, "nand-ecc-mode", &pm);
5864
-	if (err < 0)
5865
-		return err;
4933
+	if (!err) {
4934
+		if (!strcasecmp(pm, "hw_syndrome"))
4935
+			return NAND_ECC_PLACEMENT_INTERLEAVED;
4936
+	}
5866
4937
 
5867
-	if (!strcasecmp(pm, "soft"))
5868
-		return NAND_ECC_HAMMING;
5869
-	else if (!strcasecmp(pm, "soft_bch"))
5870
-		return NAND_ECC_BCH;
5871
-
5872
-	return -ENODEV;
4938
+	return NAND_ECC_PLACEMENT_UNKNOWN;
5873
4939
 }
5874
4940
 
5875
-static int of_get_nand_ecc_step_size(struct device_node *np)
4941
+static enum nand_ecc_algo of_get_rawnand_ecc_algo_legacy(struct device_node *np)
5876
4942
 {
5877
-	int ret;
5878
-	u32 val;
4943
+	const char *pm;
4944
+	int err;
5879
4945
 
5880
-	ret = of_property_read_u32(np, "nand-ecc-step-size", &val);
5881
-	return ret ? ret : val;
4946
+	err = of_property_read_string(np, "nand-ecc-mode", &pm);
4947
+	if (!err) {
4948
+		if (!strcasecmp(pm, "soft"))
4949
+			return NAND_ECC_ALGO_HAMMING;
4950
+		else if (!strcasecmp(pm, "soft_bch"))
4951
+			return NAND_ECC_ALGO_BCH;
4952
+	}
4953
+
4954
+	return NAND_ECC_ALGO_UNKNOWN;
5882
4955
 }
5883
4956
 
5884
-static int of_get_nand_ecc_strength(struct device_node *np)
4957
+static void of_get_nand_ecc_legacy_user_config(struct nand_chip *chip)
5885
4958
 {
5886
-	int ret;
5887
-	u32 val;
4959
+	struct device_node *dn = nand_get_flash_node(chip);
4960
+	struct nand_ecc_props *user_conf = &chip->base.ecc.user_conf;
5888
4961
 
5889
-	ret = of_property_read_u32(np, "nand-ecc-strength", &val);
5890
-	return ret ? ret : val;
4962
+	if (user_conf->engine_type == NAND_ECC_ENGINE_TYPE_INVALID)
4963
+		user_conf->engine_type = of_get_rawnand_ecc_engine_type_legacy(dn);
4964
+
4965
+	if (user_conf->algo == NAND_ECC_ALGO_UNKNOWN)
4966
+		user_conf->algo = of_get_rawnand_ecc_algo_legacy(dn);
4967
+
4968
+	if (user_conf->placement == NAND_ECC_PLACEMENT_UNKNOWN)
4969
+		user_conf->placement = of_get_rawnand_ecc_placement_legacy(dn);
5891
4970
 }
5892
4971
 
5893
4972
 static int of_get_nand_bus_width(struct device_node *np)
..
..
@@ -5911,10 +4990,10 @@
5911
4990
 	return of_property_read_bool(np, "nand-on-flash-bbt");
5912
4991
 }
5913
4992
 
5914
-static int nand_dt_init(struct nand_chip *chip)
4993
+static int rawnand_dt_init(struct nand_chip *chip)
5915
4994
 {
4995
+	struct nand_device *nand = mtd_to_nanddev(nand_to_mtd(chip));
5916
4996
 	struct device_node *dn = nand_get_flash_node(chip);
5917
-	int ecc_mode, ecc_algo, ecc_strength, ecc_step;
5918
4997
 
5919
4998
 	if (!dn)
5920
4999
 		return 0;
..
..
@@ -5928,25 +5007,29 @@
5928
5007
 	if (of_get_nand_on_flash_bbt(dn))
5929
5008
 		chip->bbt_options |= NAND_BBT_USE_FLASH;
5930
5009
 
5931
-	ecc_mode = of_get_nand_ecc_mode(dn);
5932
-	ecc_algo = of_get_nand_ecc_algo(dn);
5933
-	ecc_strength = of_get_nand_ecc_strength(dn);
5934
-	ecc_step = of_get_nand_ecc_step_size(dn);
5010
+	of_get_nand_ecc_user_config(nand);
5011
+	of_get_nand_ecc_legacy_user_config(chip);
5935
5012
 
5936
-	if (ecc_mode >= 0)
5937
-		chip->ecc.mode = ecc_mode;
5013
+	/*
5014
+	 * If neither the user nor the NAND controller have requested a specific
5015
+	 * ECC engine type, we will default to NAND_ECC_ENGINE_TYPE_ON_HOST.
5016
+	 */
5017
+	nand->ecc.defaults.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
5938
5018
 
5939
-	if (ecc_algo >= 0)
5940
-		chip->ecc.algo = ecc_algo;
5019
+	/*
5020
+	 * Use the user requested engine type, unless there is none, in this
5021
+	 * case default to the NAND controller choice, otherwise fallback to
5022
+	 * the raw NAND default one.
5023
+	 */
5024
+	if (nand->ecc.user_conf.engine_type != NAND_ECC_ENGINE_TYPE_INVALID)
5025
+		chip->ecc.engine_type = nand->ecc.user_conf.engine_type;
5026
+	if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_INVALID)
5027
+		chip->ecc.engine_type = nand->ecc.defaults.engine_type;
5941
5028
 
5942
-	if (ecc_strength >= 0)
5943
-		chip->ecc.strength = ecc_strength;
5944
-
5945
-	if (ecc_step > 0)
5946
-		chip->ecc.size = ecc_step;
5947
-
5948
-	if (of_property_read_bool(dn, "nand-ecc-maximize"))
5949
-		chip->ecc.options |= NAND_ECC_MAXIMIZE;
5029
+	chip->ecc.placement = nand->ecc.user_conf.placement;
5030
+	chip->ecc.algo = nand->ecc.user_conf.algo;
5031
+	chip->ecc.strength = nand->ecc.user_conf.strength;
5032
+	chip->ecc.size = nand->ecc.user_conf.step_size;
5950
5033
 
5951
5034
 	return 0;
5952
5035
 }
..
..
@@ -5965,78 +5048,83 @@
5965
5048
  * prevented dynamic allocations during this phase which was unconvenient and
5966
5049
  * as been banned for the benefit of the ->init_ecc()/cleanup_ecc() hooks.
5967
5050
  */
5968
-static int nand_scan_ident(struct nand_chip *chip, int maxchips,
5051
+static int nand_scan_ident(struct nand_chip *chip, unsigned int maxchips,
5969
5052
 			   struct nand_flash_dev *table)
5970
5053
 {
5971
5054
 	struct mtd_info *mtd = nand_to_mtd(chip);
5972
-	int i, nand_maf_id, nand_dev_id;
5055
+	struct nand_memory_organization *memorg;
5056
+	int nand_maf_id, nand_dev_id;
5057
+	unsigned int i;
5973
5058
 	int ret;
5974
5059
 
5975
-	/* Enforce the right timings for reset/detection */
5976
-	onfi_fill_data_interface(chip, NAND_SDR_IFACE, 0);
5060
+	memorg = nanddev_get_memorg(&chip->base);
5977
5061
 
5978
-	ret = nand_dt_init(chip);
5062
+	/* Assume all dies are deselected when we enter nand_scan_ident(). */
5063
+	chip->cur_cs = -1;
5064
+
5065
+	mutex_init(&chip->lock);
5066
+	init_waitqueue_head(&chip->resume_wq);
5067
+
5068
+	/* Enforce the right timings for reset/detection */
5069
+	chip->current_interface_config = nand_get_reset_interface_config();
5070
+
5071
+	ret = rawnand_dt_init(chip);
5979
5072
 	if (ret)
5980
5073
 		return ret;
5981
5074
 
5982
5075
 	if (!mtd->name && mtd->dev.parent)
5983
5076
 		mtd->name = dev_name(mtd->dev.parent);
5984
5077
 
5985
-	/*
5986
-	 * ->cmdfunc() is legacy and will only be used if ->exec_op() is not
5987
-	 * populated.
5988
-	 */
5989
-	if (!chip->exec_op) {
5990
-		/*
5991
-		 * Default functions assigned for ->cmdfunc() and
5992
-		 * ->select_chip() both expect ->cmd_ctrl() to be populated.
5993
-		 */
5994
-		if ((!chip->cmdfunc || !chip->select_chip) && !chip->cmd_ctrl) {
5995
-			pr_err("->cmd_ctrl() should be provided\n");
5996
-			return -EINVAL;
5997
-		}
5998
-	}
5999
-
6000
5078
 	/* Set the default functions */
6001
5079
 	nand_set_defaults(chip);
5080
+
5081
+	ret = nand_legacy_check_hooks(chip);
5082
+	if (ret)
5083
+		return ret;
5084
+
5085
+	memorg->ntargets = maxchips;
6002
5086
 
6003
5087
 	/* Read the flash type */
6004
5088
 	ret = nand_detect(chip, table);
6005
5089
 	if (ret) {
6006
5090
 		if (!(chip->options & NAND_SCAN_SILENT_NODEV))
6007
5091
 			pr_warn("No NAND device found\n");
6008
-		chip->select_chip(mtd, -1);
5092
+		nand_deselect_target(chip);
6009
5093
 		return ret;
6010
5094
 	}
6011
5095
 
6012
5096
 	nand_maf_id = chip->id.data[0];
6013
5097
 	nand_dev_id = chip->id.data[1];
6014
5098
 
6015
-	chip->select_chip(mtd, -1);
5099
+	nand_deselect_target(chip);
6016
5100
 
6017
5101
 	/* Check for a chip array */
6018
5102
 	for (i = 1; i < maxchips; i++) {
6019
5103
 		u8 id[2];
6020
5104
 
6021
5105
 		/* See comment in nand_get_flash_type for reset */
6022
-		nand_reset(chip, i);
5106
+		ret = nand_reset(chip, i);
5107
+		if (ret)
5108
+			break;
6023
5109
 
6024
-		chip->select_chip(mtd, i);
5110
+		nand_select_target(chip, i);
6025
5111
 		/* Send the command for reading device ID */
6026
-		nand_readid_op(chip, 0, id, sizeof(id));
5112
+		ret = nand_readid_op(chip, 0, id, sizeof(id));
5113
+		if (ret)
5114
+			break;
6027
5115
 		/* Read manufacturer and device IDs */
6028
5116
 		if (nand_maf_id != id[0] || nand_dev_id != id[1]) {
6029
-			chip->select_chip(mtd, -1);
5117
+			nand_deselect_target(chip);
6030
5118
 			break;
6031
5119
 		}
6032
-		chip->select_chip(mtd, -1);
5120
+		nand_deselect_target(chip);
6033
5121
 	}
6034
5122
 	if (i > 1)
6035
5123
 		pr_info("%d chips detected\n", i);
6036
5124
 
6037
5125
 	/* Store the number of chips and calc total size for mtd */
6038
-	chip->numchips = i;
6039
-	mtd->size = i * chip->chipsize;
5126
+	memorg->ntargets = i;
5127
+	mtd->size = i * nanddev_target_size(&chip->base);
6040
5128
 
6041
5129
 	return 0;
6042
5130
 }
..
..
@@ -6047,33 +5135,99 @@
6047
5135
 	kfree(chip->parameters.onfi);
6048
5136
 }
6049
5137
 
6050
-static int nand_set_ecc_soft_ops(struct mtd_info *mtd)
5138
+static int nand_set_ecc_on_host_ops(struct nand_chip *chip)
6051
5139
 {
6052
-	struct nand_chip *chip = mtd_to_nand(mtd);
6053
5140
 	struct nand_ecc_ctrl *ecc = &chip->ecc;
6054
5141
 
6055
-	if (WARN_ON(ecc->mode != NAND_ECC_SOFT))
5142
+	switch (ecc->placement) {
5143
+	case NAND_ECC_PLACEMENT_UNKNOWN:
5144
+	case NAND_ECC_PLACEMENT_OOB:
5145
+		/* Use standard hwecc read page function? */
5146
+		if (!ecc->read_page)
5147
+			ecc->read_page = nand_read_page_hwecc;
5148
+		if (!ecc->write_page)
5149
+			ecc->write_page = nand_write_page_hwecc;
5150
+		if (!ecc->read_page_raw)
5151
+			ecc->read_page_raw = nand_read_page_raw;
5152
+		if (!ecc->write_page_raw)
5153
+			ecc->write_page_raw = nand_write_page_raw;
5154
+		if (!ecc->read_oob)
5155
+			ecc->read_oob = nand_read_oob_std;
5156
+		if (!ecc->write_oob)
5157
+			ecc->write_oob = nand_write_oob_std;
5158
+		if (!ecc->read_subpage)
5159
+			ecc->read_subpage = nand_read_subpage;
5160
+		if (!ecc->write_subpage && ecc->hwctl && ecc->calculate)
5161
+			ecc->write_subpage = nand_write_subpage_hwecc;
5162
+		fallthrough;
5163
+
5164
+	case NAND_ECC_PLACEMENT_INTERLEAVED:
5165
+		if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
5166
+		    (!ecc->read_page ||
5167
+		     ecc->read_page == nand_read_page_hwecc ||
5168
+		     !ecc->write_page ||
5169
+		     ecc->write_page == nand_write_page_hwecc)) {
5170
+			WARN(1, "No ECC functions supplied; hardware ECC not possible\n");
5171
+			return -EINVAL;
5172
+		}
5173
+		/* Use standard syndrome read/write page function? */
5174
+		if (!ecc->read_page)
5175
+			ecc->read_page = nand_read_page_syndrome;
5176
+		if (!ecc->write_page)
5177
+			ecc->write_page = nand_write_page_syndrome;
5178
+		if (!ecc->read_page_raw)
5179
+			ecc->read_page_raw = nand_read_page_raw_syndrome;
5180
+		if (!ecc->write_page_raw)
5181
+			ecc->write_page_raw = nand_write_page_raw_syndrome;
5182
+		if (!ecc->read_oob)
5183
+			ecc->read_oob = nand_read_oob_syndrome;
5184
+		if (!ecc->write_oob)
5185
+			ecc->write_oob = nand_write_oob_syndrome;
5186
+		break;
5187
+
5188
+	default:
5189
+		pr_warn("Invalid NAND_ECC_PLACEMENT %d\n",
5190
+			ecc->placement);
5191
+		return -EINVAL;
5192
+	}
5193
+
5194
+	return 0;
5195
+}
5196
+
5197
+static int nand_set_ecc_soft_ops(struct nand_chip *chip)
5198
+{
5199
+	struct mtd_info *mtd = nand_to_mtd(chip);
5200
+	struct nand_device *nanddev = mtd_to_nanddev(mtd);
5201
+	struct nand_ecc_ctrl *ecc = &chip->ecc;
5202
+
5203
+	if (WARN_ON(ecc->engine_type != NAND_ECC_ENGINE_TYPE_SOFT))
6056
5204
 		return -EINVAL;
6057
5205
 
6058
5206
 	switch (ecc->algo) {
6059
-	case NAND_ECC_HAMMING:
5207
+	case NAND_ECC_ALGO_HAMMING:
6060
5208
 		ecc->calculate = nand_calculate_ecc;
6061
5209
 		ecc->correct = nand_correct_data;
6062
5210
 		ecc->read_page = nand_read_page_swecc;
6063
5211
 		ecc->read_subpage = nand_read_subpage;
6064
5212
 		ecc->write_page = nand_write_page_swecc;
6065
-		ecc->read_page_raw = nand_read_page_raw;
6066
-		ecc->write_page_raw = nand_write_page_raw;
5213
+		if (!ecc->read_page_raw)
5214
+			ecc->read_page_raw = nand_read_page_raw;
5215
+		if (!ecc->write_page_raw)
5216
+			ecc->write_page_raw = nand_write_page_raw;
6067
5217
 		ecc->read_oob = nand_read_oob_std;
6068
5218
 		ecc->write_oob = nand_write_oob_std;
6069
5219
 		if (!ecc->size)
6070
5220
 			ecc->size = 256;
6071
5221
 		ecc->bytes = 3;
6072
5222
 		ecc->strength = 1;
5223
+
5224
+		if (IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC))
5225
+			ecc->options |= NAND_ECC_SOFT_HAMMING_SM_ORDER;
5226
+
6073
5227
 		return 0;
6074
-	case NAND_ECC_BCH:
5228
+	case NAND_ECC_ALGO_BCH:
6075
5229
 		if (!mtd_nand_has_bch()) {
6076
-			WARN(1, "CONFIG_MTD_NAND_ECC_BCH not enabled\n");
5230
+			WARN(1, "CONFIG_MTD_NAND_ECC_SW_BCH not enabled\n");
6077
5231
 			return -EINVAL;
6078
5232
 		}
6079
5233
 		ecc->calculate = nand_bch_calculate_ecc;
..
..
@@ -6081,8 +5235,10 @@
6081
5235
 		ecc->read_page = nand_read_page_swecc;
6082
5236
 		ecc->read_subpage = nand_read_subpage;
6083
5237
 		ecc->write_page = nand_write_page_swecc;
6084
-		ecc->read_page_raw = nand_read_page_raw;
6085
-		ecc->write_page_raw = nand_write_page_raw;
5238
+		if (!ecc->read_page_raw)
5239
+			ecc->read_page_raw = nand_read_page_raw;
5240
+		if (!ecc->write_page_raw)
5241
+			ecc->write_page_raw = nand_write_page_raw;
6086
5242
 		ecc->read_oob = nand_read_oob_std;
6087
5243
 		ecc->write_oob = nand_write_oob_std;
6088
5244
 
..
..
@@ -6107,7 +5263,7 @@
6107
5263
 				return -EINVAL;
6108
5264
 			}
6109
5265
 
6110
-			mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
5266
+			mtd_set_ooblayout(mtd, nand_get_large_page_ooblayout());
6111
5267
 
6112
5268
 		}
6113
5269
 
..
..
@@ -6116,8 +5272,8 @@
6116
5272
 		 * used, otherwise we don't know how many bytes can really be
6117
5273
 		 * used.
6118
5274
 		 */
6119
-		if (mtd->ooblayout == &nand_ooblayout_lp_ops &&
6120
-		    ecc->options & NAND_ECC_MAXIMIZE) {
5275
+		if (mtd->ooblayout == nand_get_large_page_ooblayout() &&
5276
+		    nanddev->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH) {
6121
5277
 			int steps, bytes;
6122
5278
 
6123
5279
 			/* Always prefer 1k blocks over 512bytes ones */
..
..
@@ -6211,10 +5367,12 @@
6211
5367
 nand_match_ecc_req(struct nand_chip *chip,
6212
5368
 		   const struct nand_ecc_caps *caps, int oobavail)
6213
5369
 {
5370
+	const struct nand_ecc_props *requirements =
5371
+		nanddev_get_ecc_requirements(&chip->base);
6214
5372
 	struct mtd_info *mtd = nand_to_mtd(chip);
6215
5373
 	const struct nand_ecc_step_info *stepinfo;
6216
-	int req_step = chip->ecc_step_ds;
6217
-	int req_strength = chip->ecc_strength_ds;
5374
+	int req_step = requirements->step_size;
5375
+	int req_strength = requirements->strength;
6218
5376
 	int req_corr, step_size, strength, nsteps, ecc_bytes, ecc_bytes_total;
6219
5377
 	int best_step, best_strength, best_ecc_bytes;
6220
5378
 	int best_ecc_bytes_total = INT_MAX;
..
..
@@ -6355,11 +5513,12 @@
6355
5513
  * @caps: ECC engine caps info structure
6356
5514
  * @oobavail: OOB size that the ECC engine can use
6357
5515
  *
6358
- * Choose the ECC configuration according to following logic
5516
+ * Choose the ECC configuration according to following logic.
6359
5517
  *
6360
5518
  * 1. If both ECC step size and ECC strength are already set (usually by DT)
6361
5519
  *    then check if it is supported by this controller.
6362
- * 2. If NAND_ECC_MAXIMIZE is set, then select maximum ECC strength.
5520
+ * 2. If the user provided the nand-ecc-maximize property, then select maximum
5521
+ *    ECC strength.
6363
5522
  * 3. Otherwise, try to match the ECC step size and ECC strength closest
6364
5523
  *    to the chip's requirement. If available OOB size can't fit the chip
6365
5524
  *    requirement then fallback to the maximum ECC step size and ECC strength.
..
..
@@ -6370,6 +5529,7 @@
6370
5529
 			 const struct nand_ecc_caps *caps, int oobavail)
6371
5530
 {
6372
5531
 	struct mtd_info *mtd = nand_to_mtd(chip);
5532
+	struct nand_device *nanddev = mtd_to_nanddev(mtd);
6373
5533
 
6374
5534
 	if (WARN_ON(oobavail < 0 || oobavail > mtd->oobsize))
6375
5535
 		return -EINVAL;
..
..
@@ -6377,7 +5537,7 @@
6377
5537
 	if (chip->ecc.size && chip->ecc.strength)
6378
5538
 		return nand_check_ecc_caps(chip, caps, oobavail);
6379
5539
 
6380
-	if (chip->ecc.options & NAND_ECC_MAXIMIZE)
5540
+	if (nanddev->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH)
6381
5541
 		return nand_maximize_ecc(chip, caps, oobavail);
6382
5542
 
6383
5543
 	if (!nand_match_ecc_req(chip, caps, oobavail))
..
..
@@ -6387,39 +5547,49 @@
6387
5547
 }
6388
5548
 EXPORT_SYMBOL_GPL(nand_ecc_choose_conf);
6389
5549
 
6390
-/*
6391
- * Check if the chip configuration meet the datasheet requirements.
6392
-
6393
- * If our configuration corrects A bits per B bytes and the minimum
6394
- * required correction level is X bits per Y bytes, then we must ensure
6395
- * both of the following are true:
6396
- *
6397
- * (1) A / B >= X / Y
6398
- * (2) A >= X
6399
- *
6400
- * Requirement (1) ensures we can correct for the required bitflip density.
6401
- * Requirement (2) ensures we can correct even when all bitflips are clumped
6402
- * in the same sector.
6403
- */
6404
-static bool nand_ecc_strength_good(struct mtd_info *mtd)
5550
+static int rawnand_erase(struct nand_device *nand, const struct nand_pos *pos)
6405
5551
 {
6406
-	struct nand_chip *chip = mtd_to_nand(mtd);
6407
-	struct nand_ecc_ctrl *ecc = &chip->ecc;
6408
-	int corr, ds_corr;
5552
+	struct nand_chip *chip = container_of(nand, struct nand_chip,
5553
+					      base);
5554
+	unsigned int eb = nanddev_pos_to_row(nand, pos);
5555
+	int ret;
6409
5556
 
6410
-	if (ecc->size == 0 || chip->ecc_step_ds == 0)
6411
-		/* Not enough information */
6412
-		return true;
5557
+	eb >>= nand->rowconv.eraseblock_addr_shift;
6413
5558
 
6414
-	/*
6415
-	 * We get the number of corrected bits per page to compare
6416
-	 * the correction density.
6417
-	 */
6418
-	corr = (mtd->writesize * ecc->strength) / ecc->size;
6419
-	ds_corr = (mtd->writesize * chip->ecc_strength_ds) / chip->ecc_step_ds;
5559
+	nand_select_target(chip, pos->target);
5560
+	ret = nand_erase_op(chip, eb);
5561
+	nand_deselect_target(chip);
6420
5562
 
6421
-	return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds;
5563
+	return ret;
6422
5564
 }
5565
+
5566
+static int rawnand_markbad(struct nand_device *nand,
5567
+			   const struct nand_pos *pos)
5568
+{
5569
+	struct nand_chip *chip = container_of(nand, struct nand_chip,
5570
+					      base);
5571
+
5572
+	return nand_markbad_bbm(chip, nanddev_pos_to_offs(nand, pos));
5573
+}
5574
+
5575
+static bool rawnand_isbad(struct nand_device *nand, const struct nand_pos *pos)
5576
+{
5577
+	struct nand_chip *chip = container_of(nand, struct nand_chip,
5578
+					      base);
5579
+	int ret;
5580
+
5581
+	nand_select_target(chip, pos->target);
5582
+	ret = nand_isbad_bbm(chip, nanddev_pos_to_offs(nand, pos));
5583
+	nand_deselect_target(chip);
5584
+
5585
+	return ret;
5586
+}
5587
+
5588
+static const struct nand_ops rawnand_ops = {
5589
+	.erase = rawnand_erase,
5590
+	.markbad = rawnand_markbad,
5591
+	.isbad = rawnand_isbad,
5592
+};
6423
5593
 
6424
5594
 /**
6425
5595
  * nand_scan_tail - Scan for the NAND device
..
..
@@ -6451,9 +5621,9 @@
6451
5621
 	 * to explictly select the relevant die when interacting with the NAND
6452
5622
 	 * chip.
6453
5623
 	 */
6454
-	chip->select_chip(mtd, 0);
5624
+	nand_select_target(chip, 0);
6455
5625
 	ret = nand_manufacturer_init(chip);
6456
-	chip->select_chip(mtd, -1);
5626
+	nand_deselect_target(chip);
6457
5627
 	if (ret)
6458
5628
 		goto err_free_buf;
6459
5629
 
..
..
@@ -6464,15 +5634,17 @@
6464
5634
 	 * If no default placement scheme is given, select an appropriate one.
6465
5635
 	 */
6466
5636
 	if (!mtd->ooblayout &&
6467
-	    !(ecc->mode == NAND_ECC_SOFT && ecc->algo == NAND_ECC_BCH)) {
5637
+	    !(ecc->engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&
5638
+	      ecc->algo == NAND_ECC_ALGO_BCH)) {
6468
5639
 		switch (mtd->oobsize) {
6469
5640
 		case 8:
6470
5641
 		case 16:
6471
-			mtd_set_ooblayout(mtd, &nand_ooblayout_sp_ops);
5642
+			mtd_set_ooblayout(mtd, nand_get_small_page_ooblayout());
6472
5643
 			break;
6473
5644
 		case 64:
6474
5645
 		case 128:
6475
-			mtd_set_ooblayout(mtd, &nand_ooblayout_lp_hamming_ops);
5646
+			mtd_set_ooblayout(mtd,
5647
+					  nand_get_large_page_hamming_ooblayout());
6476
5648
 			break;
6477
5649
 		default:
6478
5650
 			/*
..
..
@@ -6482,9 +5654,9 @@
6482
5654
 			 * page with ECC layout when ->oobsize <= 128 for
6483
5655
 			 * compatibility reasons.
6484
5656
 			 */
6485
-			if (ecc->mode == NAND_ECC_NONE) {
5657
+			if (ecc->engine_type == NAND_ECC_ENGINE_TYPE_NONE) {
6486
5658
 				mtd_set_ooblayout(mtd,
6487
-						&nand_ooblayout_lp_ops);
5659
+						  nand_get_large_page_ooblayout());
6488
5660
 				break;
6489
5661
 			}
6490
5662
 
..
..
@@ -6500,59 +5672,11 @@
6500
5672
 	 * selected and we have 256 byte pagesize fallback to software ECC
6501
5673
 	 */
6502
5674
 
6503
-	switch (ecc->mode) {
6504
-	case NAND_ECC_HW_OOB_FIRST:
6505
-		/* Similar to NAND_ECC_HW, but a separate read_page handle */
6506
-		if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
6507
-			WARN(1, "No ECC functions supplied; hardware ECC not possible\n");
6508
-			ret = -EINVAL;
5675
+	switch (ecc->engine_type) {
5676
+	case NAND_ECC_ENGINE_TYPE_ON_HOST:
5677
+		ret = nand_set_ecc_on_host_ops(chip);
5678
+		if (ret)
6509
5679
 			goto err_nand_manuf_cleanup;
6510
-		}
6511
-		if (!ecc->read_page)
6512
-			ecc->read_page = nand_read_page_hwecc_oob_first;
6513
-
6514
-	case NAND_ECC_HW:
6515
-		/* Use standard hwecc read page function? */
6516
-		if (!ecc->read_page)
6517
-			ecc->read_page = nand_read_page_hwecc;
6518
-		if (!ecc->write_page)
6519
-			ecc->write_page = nand_write_page_hwecc;
6520
-		if (!ecc->read_page_raw)
6521
-			ecc->read_page_raw = nand_read_page_raw;
6522
-		if (!ecc->write_page_raw)
6523
-			ecc->write_page_raw = nand_write_page_raw;
6524
-		if (!ecc->read_oob)
6525
-			ecc->read_oob = nand_read_oob_std;
6526
-		if (!ecc->write_oob)
6527
-			ecc->write_oob = nand_write_oob_std;
6528
-		if (!ecc->read_subpage)
6529
-			ecc->read_subpage = nand_read_subpage;
6530
-		if (!ecc->write_subpage && ecc->hwctl && ecc->calculate)
6531
-			ecc->write_subpage = nand_write_subpage_hwecc;
6532
-
6533
-	case NAND_ECC_HW_SYNDROME:
6534
-		if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
6535
-		    (!ecc->read_page ||
6536
-		     ecc->read_page == nand_read_page_hwecc ||
6537
-		     !ecc->write_page ||
6538
-		     ecc->write_page == nand_write_page_hwecc)) {
6539
-			WARN(1, "No ECC functions supplied; hardware ECC not possible\n");
6540
-			ret = -EINVAL;
6541
-			goto err_nand_manuf_cleanup;
6542
-		}
6543
-		/* Use standard syndrome read/write page function? */
6544
-		if (!ecc->read_page)
6545
-			ecc->read_page = nand_read_page_syndrome;
6546
-		if (!ecc->write_page)
6547
-			ecc->write_page = nand_write_page_syndrome;
6548
-		if (!ecc->read_page_raw)
6549
-			ecc->read_page_raw = nand_read_page_raw_syndrome;
6550
-		if (!ecc->write_page_raw)
6551
-			ecc->write_page_raw = nand_write_page_raw_syndrome;
6552
-		if (!ecc->read_oob)
6553
-			ecc->read_oob = nand_read_oob_syndrome;
6554
-		if (!ecc->write_oob)
6555
-			ecc->write_oob = nand_write_oob_syndrome;
6556
5680
 
6557
5681
 		if (mtd->writesize >= ecc->size) {
6558
5682
 			if (!ecc->strength) {
..
..
@@ -6564,18 +5688,17 @@
6564
5688
 		}
6565
5689
 		pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
6566
5690
 			ecc->size, mtd->writesize);
6567
-		ecc->mode = NAND_ECC_SOFT;
6568
-		ecc->algo = NAND_ECC_HAMMING;
5691
+		ecc->engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
5692
+		ecc->algo = NAND_ECC_ALGO_HAMMING;
5693
+		fallthrough;
6569
5694
 
6570
-	case NAND_ECC_SOFT:
6571
-		ret = nand_set_ecc_soft_ops(mtd);
6572
-		if (ret) {
6573
-			ret = -EINVAL;
5695
+	case NAND_ECC_ENGINE_TYPE_SOFT:
5696
+		ret = nand_set_ecc_soft_ops(chip);
5697
+		if (ret)
6574
5698
 			goto err_nand_manuf_cleanup;
6575
-		}
6576
5699
 		break;
6577
5700
 
6578
-	case NAND_ECC_ON_DIE:
5701
+	case NAND_ECC_ENGINE_TYPE_ON_DIE:
6579
5702
 		if (!ecc->read_page || !ecc->write_page) {
6580
5703
 			WARN(1, "No ECC functions supplied; on-die ECC not possible\n");
6581
5704
 			ret = -EINVAL;
..
..
@@ -6587,8 +5710,8 @@
6587
5710
 			ecc->write_oob = nand_write_oob_std;
6588
5711
 		break;
6589
5712
 
6590
-	case NAND_ECC_NONE:
6591
-		pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n");
5713
+	case NAND_ECC_ENGINE_TYPE_NONE:
5714
+		pr_warn("NAND_ECC_ENGINE_TYPE_NONE selected by board driver. This is not recommended!\n");
6592
5715
 		ecc->read_page = nand_read_page_raw;
6593
5716
 		ecc->write_page = nand_write_page_raw;
6594
5717
 		ecc->read_oob = nand_read_oob_std;
..
..
@@ -6601,7 +5724,7 @@
6601
5724
 		break;
6602
5725
 
6603
5726
 	default:
6604
-		WARN(1, "Invalid NAND_ECC_MODE %d\n", ecc->mode);
5727
+		WARN(1, "Invalid NAND_ECC_MODE %d\n", ecc->engine_type);
6605
5728
 		ret = -EINVAL;
6606
5729
 		goto err_nand_manuf_cleanup;
6607
5730
 	}
..
..
@@ -6635,7 +5758,10 @@
6635
5758
 		ret = -EINVAL;
6636
5759
 		goto err_nand_manuf_cleanup;
6637
5760
 	}
5761
+
6638
5762
 	ecc->total = ecc->steps * ecc->bytes;
5763
+	chip->base.ecc.ctx.total = ecc->total;
5764
+
6639
5765
 	if (ecc->total > mtd->oobsize) {
6640
5766
 		WARN(1, "Total number of ECC bytes exceeded oobsize\n");
6641
5767
 		ret = -EINVAL;
..
..
@@ -6653,9 +5779,11 @@
6653
5779
 	mtd->oobavail = ret;
6654
5780
 
6655
5781
 	/* ECC sanity check: warn if it's too weak */
6656
-	if (!nand_ecc_strength_good(mtd))
6657
-		pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n",
6658
-			mtd->name);
5782
+	if (!nand_ecc_is_strong_enough(&chip->base))
5783
+		pr_warn("WARNING: %s: the ECC used on your system (%db/%dB) is too weak compared to the one required by the NAND chip (%db/%dB)\n",
5784
+			mtd->name, chip->ecc.strength, chip->ecc.size,
5785
+			nanddev_get_ecc_requirements(&chip->base)->strength,
5786
+			nanddev_get_ecc_requirements(&chip->base)->step_size);
6659
5787
 
6660
5788
 	/* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
6661
5789
 	if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
..
..
@@ -6672,15 +5800,12 @@
6672
5800
 	}
6673
5801
 	chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
6674
5802
 
6675
-	/* Initialize state */
6676
-	chip->state = FL_READY;
6677
-
6678
5803
 	/* Invalidate the pagebuffer reference */
6679
-	chip->pagebuf = -1;
5804
+	chip->pagecache.page = -1;
6680
5805
 
6681
5806
 	/* Large page NAND with SOFT_ECC should support subpage reads */
6682
-	switch (ecc->mode) {
6683
-	case NAND_ECC_SOFT:
5807
+	switch (ecc->engine_type) {
5808
+	case NAND_ECC_ENGINE_TYPE_SOFT:
6684
5809
 		if (chip->page_shift > 9)
6685
5810
 			chip->options |= NAND_SUBPAGE_READ;
6686
5811
 		break;
..
..
@@ -6689,10 +5814,15 @@
6689
5814
 		break;
6690
5815
 	}
6691
5816
 
5817
+	ret = nanddev_init(&chip->base, &rawnand_ops, mtd->owner);
5818
+	if (ret)
5819
+		goto err_nand_manuf_cleanup;
5820
+
5821
+	/* Adjust the MTD_CAP_ flags when NAND_ROM is set. */
5822
+	if (chip->options & NAND_ROM)
5823
+		mtd->flags = MTD_CAP_ROM;
5824
+
6692
5825
 	/* Fill in remaining MTD driver data */
6693
-	mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
6694
-	mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
6695
-						MTD_CAP_NANDFLASH;
6696
5826
 	mtd->_erase = nand_erase;
6697
5827
 	mtd->_point = NULL;
6698
5828
 	mtd->_unpoint = NULL;
..
..
@@ -6700,16 +5830,15 @@
6700
5830
 	mtd->_read_oob = nand_read_oob;
6701
5831
 	mtd->_write_oob = nand_write_oob;
6702
5832
 	mtd->_sync = nand_sync;
6703
-	mtd->_lock = NULL;
6704
-	mtd->_unlock = NULL;
5833
+	mtd->_lock = nand_lock;
5834
+	mtd->_unlock = nand_unlock;
6705
5835
 	mtd->_suspend = nand_suspend;
6706
5836
 	mtd->_resume = nand_resume;
6707
5837
 	mtd->_reboot = nand_shutdown;
6708
5838
 	mtd->_block_isreserved = nand_block_isreserved;
6709
5839
 	mtd->_block_isbad = nand_block_isbad;
6710
5840
 	mtd->_block_markbad = nand_block_markbad;
6711
-	mtd->_max_bad_blocks = nand_max_bad_blocks;
6712
-	mtd->writebufsize = mtd->writesize;
5841
+	mtd->_max_bad_blocks = nanddev_mtd_max_bad_blocks;
6713
5842
 
6714
5843
 	/*
6715
5844
 	 * Initialize bitflip_threshold to its default prior scan_bbt() call.
..
..
@@ -6719,16 +5848,16 @@
6719
5848
 	if (!mtd->bitflip_threshold)
6720
5849
 		mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4);
6721
5850
 
6722
-	/* Initialize the ->data_interface field. */
6723
-	ret = nand_init_data_interface(chip);
5851
+	/* Find the fastest data interface for this chip */
5852
+	ret = nand_choose_interface_config(chip);
6724
5853
 	if (ret)
6725
-		goto err_nand_manuf_cleanup;
5854
+		goto err_nanddev_cleanup;
6726
5855
 
6727
5856
 	/* Enter fastest possible mode on all dies. */
6728
-	for (i = 0; i < chip->numchips; i++) {
6729
-		ret = nand_setup_data_interface(chip, i);
5857
+	for (i = 0; i < nanddev_ntargets(&chip->base); i++) {
5858
+		ret = nand_setup_interface(chip, i);
6730
5859
 		if (ret)
6731
-			goto err_nand_manuf_cleanup;
5860
+			goto err_free_interface_config;
6732
5861
 	}
6733
5862
 
6734
5863
 	/* Check, if we should skip the bad block table scan */
..
..
@@ -6738,10 +5867,15 @@
6738
5867
 	/* Build bad block table */
6739
5868
 	ret = nand_create_bbt(chip);
6740
5869
 	if (ret)
6741
-		goto err_nand_manuf_cleanup;
5870
+		goto err_free_interface_config;
6742
5871
 
6743
5872
 	return 0;
6744
5873
 
5874
+err_free_interface_config:
5875
+	kfree(chip->best_interface_config);
5876
+
5877
+err_nanddev_cleanup:
5878
+	nanddev_cleanup(&chip->base);
6745
5879
 
6746
5880
 err_nand_manuf_cleanup:
6747
5881
 	nand_manufacturer_cleanup(chip);
..
..
@@ -6771,25 +5905,24 @@
6771
5905
 /**
6772
5906
  * nand_scan_with_ids - [NAND Interface] Scan for the NAND device
6773
5907
  * @chip: NAND chip object
6774
- * @maxchips: number of chips to scan for. @nand_scan_ident() will not be run if
6775
- *	      this parameter is zero (useful for specific drivers that must
6776
- *	      handle this part of the process themselves, e.g docg4).
5908
+ * @maxchips: number of chips to scan for.
6777
5909
  * @ids: optional flash IDs table
6778
5910
  *
6779
5911
  * This fills out all the uninitialized function pointers with the defaults.
6780
5912
  * The flash ID is read and the mtd/chip structures are filled with the
6781
5913
  * appropriate values.
6782
5914
  */
6783
-int nand_scan_with_ids(struct nand_chip *chip, int maxchips,
5915
+int nand_scan_with_ids(struct nand_chip *chip, unsigned int maxchips,
6784
5916
 		       struct nand_flash_dev *ids)
6785
5917
 {
6786
5918
 	int ret;
6787
5919
 
6788
-	if (maxchips) {
6789
-		ret = nand_scan_ident(chip, maxchips, ids);
6790
-		if (ret)
6791
-			return ret;
6792
-	}
5920
+	if (!maxchips)
5921
+		return -EINVAL;
5922
+
5923
+	ret = nand_scan_ident(chip, maxchips, ids);
5924
+	if (ret)
5925
+		return ret;
6793
5926
 
6794
5927
 	ret = nand_attach(chip);
6795
5928
 	if (ret)
..
..
@@ -6816,9 +5949,11 @@
6816
5949
  */
6817
5950
 void nand_cleanup(struct nand_chip *chip)
6818
5951
 {
6819
-	if (chip->ecc.mode == NAND_ECC_SOFT &&
6820
-	    chip->ecc.algo == NAND_ECC_BCH)
5952
+	if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&
5953
+	    chip->ecc.algo == NAND_ECC_ALGO_BCH)
6821
5954
 		nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
5955
+
5956
+	nanddev_cleanup(&chip->base);
6822
5957
 
6823
5958
 	/* Free bad block table memory */
6824
5959
 	kfree(chip->bbt);
..
..
@@ -6831,6 +5966,9 @@
6831
5966
 			& NAND_BBT_DYNAMICSTRUCT)
6832
5967
 		kfree(chip->badblock_pattern);
6833
5968
 
5969
+	/* Free the data interface */
5970
+	kfree(chip->best_interface_config);
5971
+
6834
5972
 	/* Free manufacturer priv data. */
6835
5973
 	nand_manufacturer_cleanup(chip);
6836
5974
 
..
..
@@ -6842,18 +5980,6 @@
6842
5980
 }
6843
5981
 
6844
5982
 EXPORT_SYMBOL_GPL(nand_cleanup);
6845
-
6846
-/**
6847
- * nand_release - [NAND Interface] Unregister the MTD device and free resources
6848
- *		  held by the NAND device
6849
- * @chip: NAND chip object
6850
- */
6851
-void nand_release(struct nand_chip *chip)
6852
-{
6853
-	mtd_device_unregister(nand_to_mtd(chip));
6854
-	nand_cleanup(chip);
6855
-}
6856
-EXPORT_SYMBOL_GPL(nand_release);
6857
5983
 
6858
5984
 MODULE_LICENSE("GPL");
6859
5985
 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");