change wifi driver to cypress

hc

2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390

 kernel/drivers/media/platform/exynos4-is/fimc-lite-reg.h
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@@ -1,13 +1,12 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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  * Copyright (C) 2012 Samsung Electronics Co., Ltd.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  */
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 #ifndef FIMC_LITE_REG_H_
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 #define FIMC_LITE_REG_H_
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+
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+#include <linux/bitops.h>
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 #include "fimc-lite.h"
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@@ -30,27 +29,27 @@
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 /* User defined formats. x = 0...15 */
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 #define FLITE_REG_CIGCTRL_USER(x)		((0x30 + x - 1) << 24)
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 #define FLITE_REG_CIGCTRL_FMT_MASK		(0x3f << 24)
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-#define FLITE_REG_CIGCTRL_SHADOWMASK_DISABLE	(1 << 21)
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-#define FLITE_REG_CIGCTRL_ODMA_DISABLE		(1 << 20)
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-#define FLITE_REG_CIGCTRL_SWRST_REQ		(1 << 19)
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-#define FLITE_REG_CIGCTRL_SWRST_RDY		(1 << 18)
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-#define FLITE_REG_CIGCTRL_SWRST			(1 << 17)
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-#define FLITE_REG_CIGCTRL_TEST_PATTERN_COLORBAR	(1 << 15)
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-#define FLITE_REG_CIGCTRL_INVPOLPCLK		(1 << 14)
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-#define FLITE_REG_CIGCTRL_INVPOLVSYNC		(1 << 13)
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-#define FLITE_REG_CIGCTRL_INVPOLHREF		(1 << 12)
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+#define FLITE_REG_CIGCTRL_SHADOWMASK_DISABLE	BIT(21)
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+#define FLITE_REG_CIGCTRL_ODMA_DISABLE		BIT(20)
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+#define FLITE_REG_CIGCTRL_SWRST_REQ		BIT(19)
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+#define FLITE_REG_CIGCTRL_SWRST_RDY		BIT(18)
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+#define FLITE_REG_CIGCTRL_SWRST			BIT(17)
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+#define FLITE_REG_CIGCTRL_TEST_PATTERN_COLORBAR	BIT(15)
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+#define FLITE_REG_CIGCTRL_INVPOLPCLK		BIT(14)
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+#define FLITE_REG_CIGCTRL_INVPOLVSYNC		BIT(13)
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+#define FLITE_REG_CIGCTRL_INVPOLHREF		BIT(12)
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 /* Interrupts mask bits (1 disables an interrupt) */
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-#define FLITE_REG_CIGCTRL_IRQ_LASTEN		(1 << 8)
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-#define FLITE_REG_CIGCTRL_IRQ_ENDEN		(1 << 7)
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-#define FLITE_REG_CIGCTRL_IRQ_STARTEN		(1 << 6)
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-#define FLITE_REG_CIGCTRL_IRQ_OVFEN		(1 << 5)
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+#define FLITE_REG_CIGCTRL_IRQ_LASTEN		BIT(8)
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+#define FLITE_REG_CIGCTRL_IRQ_ENDEN		BIT(7)
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+#define FLITE_REG_CIGCTRL_IRQ_STARTEN		BIT(6)
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+#define FLITE_REG_CIGCTRL_IRQ_OVFEN		BIT(5)
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 #define FLITE_REG_CIGCTRL_IRQ_DISABLE_MASK	(0xf << 5)
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-#define FLITE_REG_CIGCTRL_SELCAM_MIPI		(1 << 3)
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+#define FLITE_REG_CIGCTRL_SELCAM_MIPI		BIT(3)
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 /* Image Capture Enable */
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 #define FLITE_REG_CIIMGCPT			0x08
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-#define FLITE_REG_CIIMGCPT_IMGCPTEN		(1 << 31)
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-#define FLITE_REG_CIIMGCPT_CPT_FREN		(1 << 25)
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+#define FLITE_REG_CIIMGCPT_IMGCPTEN		BIT(31)
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+#define FLITE_REG_CIIMGCPT_CPT_FREN		BIT(25)
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 #define FLITE_REG_CIIMGCPT_CPT_MOD_FRCNT	(1 << 18)
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 #define FLITE_REG_CIIMGCPT_CPT_MOD_FREN		(0 << 18)
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@@ -59,10 +58,10 @@
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 /* Camera Window Offset */
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 #define FLITE_REG_CIWDOFST			0x10
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-#define FLITE_REG_CIWDOFST_WINOFSEN		(1 << 31)
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-#define FLITE_REG_CIWDOFST_CLROVIY		(1 << 31)
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-#define FLITE_REG_CIWDOFST_CLROVFICB		(1 << 15)
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-#define FLITE_REG_CIWDOFST_CLROVFICR		(1 << 14)
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+#define FLITE_REG_CIWDOFST_WINOFSEN		BIT(31)
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+#define FLITE_REG_CIWDOFST_CLROVIY		BIT(31)
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+#define FLITE_REG_CIWDOFST_CLROVFICB		BIT(15)
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+#define FLITE_REG_CIWDOFST_CLROVFICR		BIT(14)
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 #define FLITE_REG_CIWDOFST_OFST_MASK		((0x1fff << 16) | 0x1fff)
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 /* Camera Window Offset2 */
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@@ -70,8 +69,8 @@
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 /* Camera Output DMA Format */
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 #define FLITE_REG_CIODMAFMT			0x18
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-#define FLITE_REG_CIODMAFMT_RAW_CON		(1 << 15)
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-#define FLITE_REG_CIODMAFMT_PACK12		(1 << 14)
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+#define FLITE_REG_CIODMAFMT_RAW_CON		BIT(15)
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+#define FLITE_REG_CIODMAFMT_PACK12		BIT(14)
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 #define FLITE_REG_CIODMAFMT_YCBYCR		(0 << 4)
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 #define FLITE_REG_CIODMAFMT_YCRYCB		(1 << 4)
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 #define FLITE_REG_CIODMAFMT_CBYCRY		(2 << 4)
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@@ -91,34 +90,34 @@
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 /* Camera Status */
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 #define FLITE_REG_CISTATUS			0x40
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-#define FLITE_REG_CISTATUS_MIPI_VVALID		(1 << 22)
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-#define FLITE_REG_CISTATUS_MIPI_HVALID		(1 << 21)
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-#define FLITE_REG_CISTATUS_MIPI_DVALID		(1 << 20)
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-#define FLITE_REG_CISTATUS_ITU_VSYNC		(1 << 14)
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-#define FLITE_REG_CISTATUS_ITU_HREFF		(1 << 13)
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-#define FLITE_REG_CISTATUS_OVFIY		(1 << 10)
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-#define FLITE_REG_CISTATUS_OVFICB		(1 << 9)
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-#define FLITE_REG_CISTATUS_OVFICR		(1 << 8)
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-#define FLITE_REG_CISTATUS_IRQ_SRC_OVERFLOW	(1 << 7)
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-#define FLITE_REG_CISTATUS_IRQ_SRC_LASTCAPEND	(1 << 6)
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-#define FLITE_REG_CISTATUS_IRQ_SRC_FRMSTART	(1 << 5)
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-#define FLITE_REG_CISTATUS_IRQ_SRC_FRMEND	(1 << 4)
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-#define FLITE_REG_CISTATUS_IRQ_CAM		(1 << 0)
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+#define FLITE_REG_CISTATUS_MIPI_VVALID		BIT(22)
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+#define FLITE_REG_CISTATUS_MIPI_HVALID		BIT(21)
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+#define FLITE_REG_CISTATUS_MIPI_DVALID		BIT(20)
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+#define FLITE_REG_CISTATUS_ITU_VSYNC		BIT(14)
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+#define FLITE_REG_CISTATUS_ITU_HREFF		BIT(13)
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+#define FLITE_REG_CISTATUS_OVFIY		BIT(10)
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+#define FLITE_REG_CISTATUS_OVFICB		BIT(9)
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+#define FLITE_REG_CISTATUS_OVFICR		BIT(8)
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+#define FLITE_REG_CISTATUS_IRQ_SRC_OVERFLOW	BIT(7)
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+#define FLITE_REG_CISTATUS_IRQ_SRC_LASTCAPEND	BIT(6)
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+#define FLITE_REG_CISTATUS_IRQ_SRC_FRMSTART	BIT(5)
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+#define FLITE_REG_CISTATUS_IRQ_SRC_FRMEND	BIT(4)
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+#define FLITE_REG_CISTATUS_IRQ_CAM		BIT(0)
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 #define FLITE_REG_CISTATUS_IRQ_MASK		(0xf << 4)
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 /* Camera Status2 */
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 #define FLITE_REG_CISTATUS2			0x44
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-#define FLITE_REG_CISTATUS2_LASTCAPEND		(1 << 1)
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-#define FLITE_REG_CISTATUS2_FRMEND		(1 << 0)
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+#define FLITE_REG_CISTATUS2_LASTCAPEND		BIT(1)
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+#define FLITE_REG_CISTATUS2_FRMEND		BIT(0)
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 /* Qos Threshold */
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 #define FLITE_REG_CITHOLD			0xf0
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-#define FLITE_REG_CITHOLD_W_QOS_EN		(1 << 30)
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+#define FLITE_REG_CITHOLD_W_QOS_EN		BIT(30)
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 /* Camera General Purpose */
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 #define FLITE_REG_CIGENERAL			0xfc
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 /* b0: 1 - camera B, 0 - camera A */
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-#define FLITE_REG_CIGENERAL_CAM_B		(1 << 0)
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+#define FLITE_REG_CIGENERAL_CAM_B		BIT(0)
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 #define FLITE_REG_CIFCNTSEQ			0x100
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 #define FLITE_REG_CIOSAN(x)			(0x200 + (4 * (x)))