change wifi driver to cypress

hc

2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390

 kernel/drivers/media/platform/cadence/cdns-csi2tx.c
..
..
@@ -2,7 +2,7 @@
2
2
 /*
3
3
  * Driver for Cadence MIPI-CSI2 TX Controller
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4
  *
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- * Copyright (C) 2017-2018 Cadence Design Systems Inc.
5
+ * Copyright (C) 2017-2019 Cadence Design Systems Inc.
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6
  */
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7
 
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8
 #include <linux/clk.h>
..
..
@@ -52,6 +52,17 @@
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52
 #define CSI2TX_STREAM_IF_CFG_REG(n)	(0x100 + (n) * 4)
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53
 #define CSI2TX_STREAM_IF_CFG_FILL_LEVEL(n)	((n) & 0x1f)
54
54
 
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+/* CSI2TX V2 Registers */
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+#define CSI2TX_V2_DPHY_CFG_REG			0x28
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+#define CSI2TX_V2_DPHY_CFG_RESET		BIT(16)
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+#define CSI2TX_V2_DPHY_CFG_CLOCK_MODE		BIT(10)
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+#define CSI2TX_V2_DPHY_CFG_MODE_MASK		GENMASK(9, 8)
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+#define CSI2TX_V2_DPHY_CFG_MODE_LPDT		(2 << 8)
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+#define CSI2TX_V2_DPHY_CFG_MODE_HS		(1 << 8)
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+#define CSI2TX_V2_DPHY_CFG_MODE_ULPS		(0 << 8)
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+#define CSI2TX_V2_DPHY_CFG_CLK_ENABLE		BIT(4)
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+#define CSI2TX_V2_DPHY_CFG_LANE_ENABLE(n)	BIT(n)
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+
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66
 #define CSI2TX_LANES_MAX	4
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67
 #define CSI2TX_STREAMS_MAX	4
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68
 
..
..
@@ -70,6 +81,13 @@
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 	u32	bpp;
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82
 };
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83
 
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+struct csi2tx_priv;
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+
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+/* CSI2TX Variant Operations */
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+struct csi2tx_vops {
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+	void (*dphy_setup)(struct csi2tx_priv *csi2tx);
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+};
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+
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91
 struct csi2tx_priv {
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 	struct device			*dev;
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 	unsigned int			count;
..
..
@@ -81,6 +99,8 @@
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 	struct mutex			lock;
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100
 
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101
 	void __iomem			*base;
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+
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+	struct csi2tx_vops		*vops;
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104
 
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 	struct clk			*esc_clk;
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106
 	struct clk			*p_clk;
..
..
@@ -209,6 +229,68 @@
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 	.set_fmt	= csi2tx_set_pad_format,
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 };
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231
 
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+/* Set Wake Up value in the D-PHY */
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+static void csi2tx_dphy_set_wakeup(struct csi2tx_priv *csi2tx)
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+{
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+	writel(CSI2TX_DPHY_CLK_WAKEUP_ULPS_CYCLES(32),
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+	       csi2tx->base + CSI2TX_DPHY_CLK_WAKEUP_REG);
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+}
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+
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+/*
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+ * Finishes the D-PHY initialization
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+ * reg dphy cfg value to be used
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+ */
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+static void csi2tx_dphy_init_finish(struct csi2tx_priv *csi2tx, u32 reg)
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+{
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+	unsigned int i;
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+
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+	udelay(10);
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+
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+	/* Enable our (clock and data) lanes */
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+	reg |= CSI2TX_DPHY_CFG_CLK_ENABLE;
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+	for (i = 0; i < csi2tx->num_lanes; i++)
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+		reg |= CSI2TX_DPHY_CFG_LANE_ENABLE(csi2tx->lanes[i] - 1);
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+	writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG);
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+
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+	udelay(10);
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+
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+	/* Switch to HS mode */
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+	reg &= ~CSI2TX_DPHY_CFG_MODE_MASK;
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+	writel(reg | CSI2TX_DPHY_CFG_MODE_HS,
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+	       csi2tx->base + CSI2TX_DPHY_CFG_REG);
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+}
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+
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+/* Configures D-PHY in CSIv1.3 */
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+static void csi2tx_dphy_setup(struct csi2tx_priv *csi2tx)
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+{
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+	u32 reg;
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+	unsigned int i;
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+
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+	csi2tx_dphy_set_wakeup(csi2tx);
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+
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+	/* Put our lanes (clock and data) out of reset */
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+	reg = CSI2TX_DPHY_CFG_CLK_RESET | CSI2TX_DPHY_CFG_MODE_LPDT;
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+	for (i = 0; i < csi2tx->num_lanes; i++)
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+		reg |= CSI2TX_DPHY_CFG_LANE_RESET(csi2tx->lanes[i] - 1);
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+	writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG);
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+
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+	csi2tx_dphy_init_finish(csi2tx, reg);
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+}
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+
280
+/* Configures D-PHY in CSIv2 */
281
+static void csi2tx_v2_dphy_setup(struct csi2tx_priv *csi2tx)
282
+{
283
+	u32 reg;
284
+
285
+	csi2tx_dphy_set_wakeup(csi2tx);
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+
287
+	/* Put our lanes (clock and data) out of reset */
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+	reg = CSI2TX_V2_DPHY_CFG_RESET | CSI2TX_V2_DPHY_CFG_MODE_LPDT;
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+	writel(reg, csi2tx->base + CSI2TX_V2_DPHY_CFG_REG);
290
+
291
+	csi2tx_dphy_init_finish(csi2tx, reg);
292
+}
293
+
212
294
 static void csi2tx_reset(struct csi2tx_priv *csi2tx)
213
295
 {
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 	writel(CSI2TX_CONFIG_SRST_REQ, csi2tx->base + CSI2TX_CONFIG_REG);
..
..
@@ -221,7 +303,6 @@
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303
 	struct media_entity *entity = &csi2tx->subdev.entity;
222
304
 	struct media_link *link;
223
305
 	unsigned int i;
224
-	u32 reg;
225
306
 
226
307
 	csi2tx_reset(csi2tx);
227
308
 
..
..
@@ -229,32 +310,10 @@
229
310
 
230
311
 	udelay(10);
231
312
 
232
-	/* Configure our PPI interface with the D-PHY */
233
-	writel(CSI2TX_DPHY_CLK_WAKEUP_ULPS_CYCLES(32),
234
-	       csi2tx->base + CSI2TX_DPHY_CLK_WAKEUP_REG);
235
-
236
-	/* Put our lanes (clock and data) out of reset */
237
-	reg = CSI2TX_DPHY_CFG_CLK_RESET | CSI2TX_DPHY_CFG_MODE_LPDT;
238
-	for (i = 0; i < csi2tx->num_lanes; i++)
239
-		reg |= CSI2TX_DPHY_CFG_LANE_RESET(csi2tx->lanes[i]);
240
-	writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG);
241
-
242
-	udelay(10);
243
-
244
-	/* Enable our (clock and data) lanes */
245
-	reg |= CSI2TX_DPHY_CFG_CLK_ENABLE;
246
-	for (i = 0; i < csi2tx->num_lanes; i++)
247
-		reg |= CSI2TX_DPHY_CFG_LANE_ENABLE(csi2tx->lanes[i]);
248
-	writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG);
249
-
250
-	udelay(10);
251
-
252
-	/* Switch to HS mode */
253
-	reg &= ~CSI2TX_DPHY_CFG_MODE_MASK;
254
-	writel(reg | CSI2TX_DPHY_CFG_MODE_HS,
255
-	       csi2tx->base + CSI2TX_DPHY_CFG_REG);
256
-
257
-	udelay(10);
313
+	if (csi2tx->vops && csi2tx->vops->dphy_setup) {
314
+		csi2tx->vops->dphy_setup(csi2tx);
315
+		udelay(10);
316
+	}
258
317
 
259
318
 	/*
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319
 	 * Create a static mapping between the CSI virtual channels
..
..
@@ -432,9 +491,9 @@
432
491
 
433
492
 static int csi2tx_check_lanes(struct csi2tx_priv *csi2tx)
434
493
 {
435
-	struct v4l2_fwnode_endpoint v4l2_ep;
494
+	struct v4l2_fwnode_endpoint v4l2_ep = { .bus_type = 0 };
436
495
 	struct device_node *ep;
437
-	int ret;
496
+	int ret, i;
438
497
 
439
498
 	ep = of_graph_get_endpoint_by_regs(csi2tx->dev->of_node, 0, 0);
440
499
 	if (!ep)
..
..
@@ -446,7 +505,7 @@
446
505
 		goto out;
447
506
 	}
448
507
 
449
-	if (v4l2_ep.bus_type != V4L2_MBUS_CSI2) {
508
+	if (v4l2_ep.bus_type != V4L2_MBUS_CSI2_DPHY) {
450
509
 		dev_err(csi2tx->dev, "Unsupported media bus type: 0x%x\n",
451
510
 			v4l2_ep.bus_type);
452
511
 		ret = -EINVAL;
..
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@@ -461,6 +520,15 @@
461
520
 		goto out;
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521
 	}
463
522
 
523
+	for (i = 0; i < csi2tx->num_lanes; i++) {
524
+		if (v4l2_ep.bus.mipi_csi2.data_lanes[i] < 1) {
525
+			dev_err(csi2tx->dev, "Invalid lane[%d] number: %u\n",
526
+				i, v4l2_ep.bus.mipi_csi2.data_lanes[i]);
527
+			ret = -EINVAL;
528
+			goto out;
529
+		}
530
+	}
531
+
464
532
 	memcpy(csi2tx->lanes, v4l2_ep.bus.mipi_csi2.data_lanes,
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533
 	       sizeof(csi2tx->lanes));
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534
 
..
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@@ -469,9 +537,35 @@
469
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 	return ret;
470
538
 }
471
539
 
540
+static const struct csi2tx_vops csi2tx_vops = {
541
+	.dphy_setup = csi2tx_dphy_setup,
542
+};
543
+
544
+static const struct csi2tx_vops csi2tx_v2_vops = {
545
+	.dphy_setup = csi2tx_v2_dphy_setup,
546
+};
547
+
548
+static const struct of_device_id csi2tx_of_table[] = {
549
+	{
550
+		.compatible = "cdns,csi2tx",
551
+		.data = &csi2tx_vops
552
+	},
553
+	{
554
+		.compatible = "cdns,csi2tx-1.3",
555
+		.data = &csi2tx_vops
556
+	},
557
+	{
558
+		.compatible = "cdns,csi2tx-2.1",
559
+		.data = &csi2tx_v2_vops
560
+	},
561
+	{ }
562
+};
563
+MODULE_DEVICE_TABLE(of, csi2tx_of_table);
564
+
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565
 static int csi2tx_probe(struct platform_device *pdev)
473
566
 {
474
567
 	struct csi2tx_priv *csi2tx;
568
+	const struct of_device_id *of_id;
475
569
 	unsigned int i;
476
570
 	int ret;
477
571
 
..
..
@@ -485,6 +579,9 @@
485
579
 	ret = csi2tx_get_resources(csi2tx, pdev);
486
580
 	if (ret)
487
581
 		goto err_free_priv;
582
+
583
+	of_id = of_match_node(csi2tx_of_table, pdev->dev.of_node);
584
+	csi2tx->vops = (struct csi2tx_vops *)of_id->data;
488
585
 
489
586
 	v4l2_subdev_init(&csi2tx->subdev, &csi2tx_subdev_ops);
490
587
 	csi2tx->subdev.owner = THIS_MODULE;
..
..
@@ -542,12 +639,6 @@
542
639
 
543
640
 	return 0;
544
641
 }
545
-
546
-static const struct of_device_id csi2tx_of_table[] = {
547
-	{ .compatible = "cdns,csi2tx" },
548
-	{ },
549
-};
550
-MODULE_DEVICE_TABLE(of, csi2tx_of_table);
551
642
 
552
643
 static struct platform_driver csi2tx_driver = {
553
644
 	.probe	= csi2tx_probe,