~hc/RK356X_SDK_RELEASE.git

..	..	@@ -385,14 +385,20 @@
385	385	/* Ensure all unused data is 0 */
386	386	data_trail &= 0xFFFFFFFF >> (8 * (sizeof(u32) - trail_bytes));
387	387	writel(data_trail, data_reg);
388		- data_reg++;
	388	+ data_reg += sizeof(u32);
389	389	}
	390	+
390	391	/*
391	392	* 'data_reg' indicates next register to write. If we did not already
392	393	* write on tx complete reg(last reg), we must do so for transmit
	394	+ * In addition, we also need to make sure all intermediate data
	395	+ * registers(if any required), are reset to 0 for TISCI backward
	396	+ * compatibility to be maintained.
393	397	*/
394		- if (data_reg <= qinst->queue_buff_end)
395		- writel(0, qinst->queue_buff_end);
	398	+ while (data_reg <= qinst->queue_buff_end) {
	399	+ writel(0, data_reg);
	400	+ data_reg += sizeof(u32);
	401	+ }
396	402
397	403	return 0;
398	404	}