hc
2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390
kernel/drivers/irqchip/irq-ath79-misc.c
....@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23 * Atheros AR71xx/AR724x/AR913x MISC interrupt controller
34 *
....@@ -7,10 +8,6 @@
78 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
89 *
910 * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
10
- *
11
- * This program is free software; you can redistribute it and/or modify it
12
- * under the terms of the GNU General Public License version 2 as published
13
- * by the Free Software Foundation.
1411 */
1512
1613 #include <linux/irqchip.h>
....@@ -22,6 +19,15 @@
2219 #define AR71XX_RESET_REG_MISC_INT_ENABLE 4
2320
2421 #define ATH79_MISC_IRQ_COUNT 32
22
+#define ATH79_MISC_PERF_IRQ 5
23
+
24
+static int ath79_perfcount_irq;
25
+
26
+int get_c0_perfcount_int(void)
27
+{
28
+ return ath79_perfcount_irq;
29
+}
30
+EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
2531
2632 static void ath79_misc_irq_handler(struct irq_desc *desc)
2733 {
....@@ -113,6 +119,8 @@
113119 {
114120 void __iomem *base = domain->host_data;
115121
122
+ ath79_perfcount_irq = irq_create_mapping(domain, ATH79_MISC_PERF_IRQ);
123
+
116124 /* Disable and clear all interrupts */
117125 __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
118126 __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);