change wifi driver to cypress

hc

2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390

 kernel/drivers/gpu/drm/v3d/v3d_irq.c
..
..
@@ -4,26 +4,34 @@
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4
 /**
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5
  * DOC: Interrupt management for the V3D engine
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  *
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- * When we take a binning or rendering flush done interrupt, we need
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- * to signal the fence for that job so that the scheduler can queue up
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- * the next one and unblock any waiters.
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+ * When we take a bin, render, TFU done, or CSD done interrupt, we
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+ * need to signal the fence for that job so that the scheduler can
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+ * queue up the next one and unblock any waiters.
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  *
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11
  * When we take the binner out of memory interrupt, we need to
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  * allocate some new memory and pass it to the binner so that the
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  * current job can make progress.
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  */
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15
 
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+#include <linux/platform_device.h>
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+
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18
 #include "v3d_drv.h"
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19
 #include "v3d_regs.h"
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+#include "v3d_trace.h"
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21
 
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 #define V3D_CORE_IRQS ((u32)(V3D_INT_OUTOMEM |	\
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23
 			     V3D_INT_FLDONE |	\
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24
 			     V3D_INT_FRDONE |	\
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+			     V3D_INT_CSDDONE |	\
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 			     V3D_INT_GMPV))
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27
 
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 #define V3D_HUB_IRQS ((u32)(V3D_HUB_INT_MMU_WRV |	\
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29
 			    V3D_HUB_INT_MMU_PTI |	\
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-			    V3D_HUB_INT_MMU_CAP))
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+			    V3D_HUB_INT_MMU_CAP |	\
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+			    V3D_HUB_INT_TFUC))
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+
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+static irqreturn_t
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+v3d_hub_irq(int irq, void *arg);
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35
 
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 static void
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37
 v3d_overflow_mem_work(struct work_struct *work)
..
..
@@ -32,12 +40,14 @@
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 		container_of(work, struct v3d_dev, overflow_mem_work);
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41
 	struct drm_device *dev = &v3d->drm;
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 	struct v3d_bo *bo = v3d_bo_create(dev, NULL /* XXX: GMP */, 256 * 1024);
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+	struct drm_gem_object *obj;
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44
 	unsigned long irqflags;
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45
 
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 	if (IS_ERR(bo)) {
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 		DRM_ERROR("Couldn't allocate binner overflow mem\n");
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 		return;
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 	}
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+	obj = &bo->base.base;
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51
 
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 	/* We lost a race, and our work task came in after the bin job
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53
 	 * completed and exited.  This can happen because the HW
..
..
@@ -54,15 +64,15 @@
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64
 		goto out;
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 	}
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66
 
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-	drm_gem_object_get(&bo->base);
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-	list_add_tail(&bo->unref_head, &v3d->bin_job->unref_list);
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+	drm_gem_object_get(obj);
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+	list_add_tail(&bo->unref_head, &v3d->bin_job->render->unref_list);
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 	spin_unlock_irqrestore(&v3d->job_lock, irqflags);
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70
 
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 	V3D_CORE_WRITE(0, V3D_PTB_BPOA, bo->node.start << PAGE_SHIFT);
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-	V3D_CORE_WRITE(0, V3D_PTB_BPOS, bo->base.size);
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+	V3D_CORE_WRITE(0, V3D_PTB_BPOS, obj->size);
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73
 
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 out:
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-	drm_gem_object_put_unlocked(&bo->base);
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+	drm_gem_object_put(obj);
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 }
67
77
 
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 static irqreturn_t
..
..
@@ -80,19 +90,37 @@
80
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 	if (intsts & V3D_INT_OUTOMEM) {
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 		/* Note that the OOM status is edge signaled, so the
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 		 * interrupt won't happen again until the we actually
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-		 * add more memory.
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+		 * add more memory.  Also, as of V3D 4.1, FLDONE won't
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+		 * be reported until any OOM state has been cleared.
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95
 		 */
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 		schedule_work(&v3d->overflow_mem_work);
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 		status = IRQ_HANDLED;
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98
 	}
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99
 
89
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 	if (intsts & V3D_INT_FLDONE) {
90
-		dma_fence_signal(v3d->bin_job->bin.done_fence);
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+		struct v3d_fence *fence =
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+			to_v3d_fence(v3d->bin_job->base.irq_fence);
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+
104
+		trace_v3d_bcl_irq(&v3d->drm, fence->seqno);
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+		dma_fence_signal(&fence->base);
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 		status = IRQ_HANDLED;
92
107
 	}
93
108
 
94
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 	if (intsts & V3D_INT_FRDONE) {
95
-		dma_fence_signal(v3d->render_job->render.done_fence);
110
+		struct v3d_fence *fence =
111
+			to_v3d_fence(v3d->render_job->base.irq_fence);
112
+
113
+		trace_v3d_rcl_irq(&v3d->drm, fence->seqno);
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+		dma_fence_signal(&fence->base);
115
+		status = IRQ_HANDLED;
116
+	}
117
+
118
+	if (intsts & V3D_INT_CSDDONE) {
119
+		struct v3d_fence *fence =
120
+			to_v3d_fence(v3d->csd_job->base.irq_fence);
121
+
122
+		trace_v3d_csd_irq(&v3d->drm, fence->seqno);
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+		dma_fence_signal(&fence->base);
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124
 		status = IRQ_HANDLED;
97
125
 	}
98
126
 
..
..
@@ -100,7 +128,13 @@
100
128
 	 * always-allowed mode.
101
129
 	 */
102
130
 	if (intsts & V3D_INT_GMPV)
103
-		dev_err(v3d->dev, "GMP violation\n");
131
+		dev_err(v3d->drm.dev, "GMP violation\n");
132
+
133
+	/* V3D 4.2 wires the hub and core IRQs together, so if we &
134
+	 * didn't see the common one then check hub for MMU IRQs.
135
+	 */
136
+	if (v3d->single_irq_line && status == IRQ_NONE)
137
+		return v3d_hub_irq(irq, arg);
104
138
 
105
139
 	return status;
106
140
 }
..
..
@@ -117,14 +151,46 @@
117
151
 	/* Acknowledge the interrupts we're handling here. */
118
152
 	V3D_WRITE(V3D_HUB_INT_CLR, intsts);
119
153
 
154
+	if (intsts & V3D_HUB_INT_TFUC) {
155
+		struct v3d_fence *fence =
156
+			to_v3d_fence(v3d->tfu_job->base.irq_fence);
157
+
158
+		trace_v3d_tfu_irq(&v3d->drm, fence->seqno);
159
+		dma_fence_signal(&fence->base);
160
+		status = IRQ_HANDLED;
161
+	}
162
+
120
163
 	if (intsts & (V3D_HUB_INT_MMU_WRV |
121
164
 		      V3D_HUB_INT_MMU_PTI |
122
165
 		      V3D_HUB_INT_MMU_CAP)) {
123
166
 		u32 axi_id = V3D_READ(V3D_MMU_VIO_ID);
124
-		u64 vio_addr = (u64)V3D_READ(V3D_MMU_VIO_ADDR) << 8;
167
+		u64 vio_addr = ((u64)V3D_READ(V3D_MMU_VIO_ADDR) <<
168
+				(v3d->va_width - 32));
169
+		static const char *const v3d41_axi_ids[] = {
170
+			"L2T",
171
+			"PTB",
172
+			"PSE",
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+			"TLB",
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+			"CLE",
175
+			"TFU",
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+			"MMU",
177
+			"GMP",
178
+		};
179
+		const char *client = "?";
125
180
 
126
-		dev_err(v3d->dev, "MMU error from client %d at 0x%08llx%s%s%s\n",
127
-			axi_id, (long long)vio_addr,
181
+		V3D_WRITE(V3D_MMU_CTL,
182
+			  V3D_READ(V3D_MMU_CTL) & (V3D_MMU_CTL_CAP_EXCEEDED |
183
+						   V3D_MMU_CTL_PT_INVALID |
184
+						   V3D_MMU_CTL_WRITE_VIOLATION));
185
+
186
+		if (v3d->ver >= 41) {
187
+			axi_id = axi_id >> 5;
188
+			if (axi_id < ARRAY_SIZE(v3d41_axi_ids))
189
+				client = v3d41_axi_ids[axi_id];
190
+		}
191
+
192
+		dev_err(v3d->drm.dev, "MMU error from client %s (%d) at 0x%llx%s%s%s\n",
193
+			client, axi_id, (long long)vio_addr,
128
194
 			((intsts & V3D_HUB_INT_MMU_WRV) ?
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195
 			 ", write violation" : ""),
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196
 			((intsts & V3D_HUB_INT_MMU_PTI) ?
..
..
@@ -140,7 +206,7 @@
140
206
 int
141
207
 v3d_irq_init(struct v3d_dev *v3d)
142
208
 {
143
-	int ret, core;
209
+	int irq1, ret, core;
144
210
 
145
211
 	INIT_WORK(&v3d->overflow_mem_work, v3d_overflow_mem_work);
146
212
 
..
..
@@ -151,24 +217,38 @@
151
217
 		V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS);
152
218
 	V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS);
153
219
 
154
-	ret = devm_request_irq(v3d->dev, platform_get_irq(v3d->pdev, 0),
155
-			       v3d_hub_irq, IRQF_SHARED,
156
-			       "v3d_hub", v3d);
157
-	if (ret)
158
-		goto fail;
220
+	irq1 = platform_get_irq(v3d_to_pdev(v3d), 1);
221
+	if (irq1 == -EPROBE_DEFER)
222
+		return irq1;
223
+	if (irq1 > 0) {
224
+		ret = devm_request_irq(v3d->drm.dev, irq1,
225
+				       v3d_irq, IRQF_SHARED,
226
+				       "v3d_core0", v3d);
227
+		if (ret)
228
+			goto fail;
229
+		ret = devm_request_irq(v3d->drm.dev,
230
+				       platform_get_irq(v3d_to_pdev(v3d), 0),
231
+				       v3d_hub_irq, IRQF_SHARED,
232
+				       "v3d_hub", v3d);
233
+		if (ret)
234
+			goto fail;
235
+	} else {
236
+		v3d->single_irq_line = true;
159
237
 
160
-	ret = devm_request_irq(v3d->dev, platform_get_irq(v3d->pdev, 1),
161
-			       v3d_irq, IRQF_SHARED,
162
-			       "v3d_core0", v3d);
163
-	if (ret)
164
-		goto fail;
238
+		ret = devm_request_irq(v3d->drm.dev,
239
+				       platform_get_irq(v3d_to_pdev(v3d), 0),
240
+				       v3d_irq, IRQF_SHARED,
241
+				       "v3d", v3d);
242
+		if (ret)
243
+			goto fail;
244
+	}
165
245
 
166
246
 	v3d_irq_enable(v3d);
167
247
 	return 0;
168
248
 
169
249
 fail:
170
250
 	if (ret != -EPROBE_DEFER)
171
-		dev_err(v3d->dev, "IRQ setup failed: %d\n", ret);
251
+		dev_err(v3d->drm.dev, "IRQ setup failed: %d\n", ret);
172
252
 	return ret;
173
253
 }
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254