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2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390 
 kernel/drivers/gpu/drm/tegra/sor.h
....@@ -1,9 +1,6 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  * Copyright (C) 2013 NVIDIA Corporation
3
- *
4
- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
74  */
85 
96 #ifndef DRM_TEGRA_SOR_H
....@@ -42,6 +39,7 @@
4239 #define  SOR_STATE_ASY_CRC_MODE_NON_ACTIVE	(0x2 << 6)
4340 #define  SOR_STATE_ASY_CRC_MODE_COMPLETE	(0x1 << 6)
4441 #define  SOR_STATE_ASY_CRC_MODE_ACTIVE		(0x0 << 6)
42
+#define  SOR_STATE_ASY_SUBOWNER_MASK		(0x3 << 4)
4543 #define  SOR_STATE_ASY_OWNER_MASK		0xf
4644 #define  SOR_STATE_ASY_OWNER(x)			(((x) & 0xf) << 0)
4745 
....@@ -286,10 +284,12 @@
286284 #define  SOR_DP_PADCTL_CM_TXD_2		(1 << 6)
287285 #define  SOR_DP_PADCTL_CM_TXD_1		(1 << 5)
288286 #define  SOR_DP_PADCTL_CM_TXD_0		(1 << 4)
287
+#define  SOR_DP_PADCTL_CM_TXD(x)	(1 << (4 + (x)))
289288 #define  SOR_DP_PADCTL_PD_TXD_3		(1 << 3)
290289 #define  SOR_DP_PADCTL_PD_TXD_0		(1 << 2)
291290 #define  SOR_DP_PADCTL_PD_TXD_1		(1 << 1)
292291 #define  SOR_DP_PADCTL_PD_TXD_2		(1 << 0)
292
+#define  SOR_DP_PADCTL_PD_TXD(x)	(1 << (0 + (x)))
293293 
294294 #define SOR_DP_PADCTL1 0x5d
295295 
....@@ -364,11 +364,27 @@
364364 #define  INFOFRAME_HEADER_VERSION(x) (((x) & 0xff) << 8)
365365 #define  INFOFRAME_HEADER_TYPE(x) (((x) & 0xff) << 0)
366366 
367
+#define SOR_HDMI_ACR_CTRL 0xb1
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+
369
+#define SOR_HDMI_ACR_0320_SUBPACK_LOW 0xb2
370
+#define  SOR_HDMI_ACR_SUBPACK_LOW_SB1(x) (((x) & 0xff) << 24)
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+
372
+#define SOR_HDMI_ACR_0320_SUBPACK_HIGH 0xb3
373
+#define  SOR_HDMI_ACR_SUBPACK_HIGH_ENABLE (1 << 31)
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+
375
+#define SOR_HDMI_ACR_0441_SUBPACK_LOW 0xb4
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+#define SOR_HDMI_ACR_0441_SUBPACK_HIGH 0xb5
377
+
367378 #define SOR_HDMI_CTRL 0xc0
368379 #define  SOR_HDMI_CTRL_ENABLE (1 << 30)
369380 #define  SOR_HDMI_CTRL_MAX_AC_PACKET(x) (((x) & 0x1f) << 16)
370381 #define  SOR_HDMI_CTRL_AUDIO_LAYOUT (1 << 10)
371382 #define  SOR_HDMI_CTRL_REKEY(x) (((x) & 0x7f) << 0)
383
+
384
+#define SOR_HDMI_SPARE 0xcb
385
+#define  SOR_HDMI_SPARE_ACR_PRIORITY_HIGH (1 << 31)
386
+#define  SOR_HDMI_SPARE_CTS_RESET(x) (((x) & 0x7) << 16)
387
+#define  SOR_HDMI_SPARE_HW_CTS_ENABLE (1 << 0)
372388 
373389 #define SOR_REFCLK 0xe6
374390 #define  SOR_REFCLK_DIV_INT(x) ((((x) >> 2) & 0xff) << 8)
....@@ -378,10 +394,62 @@
378394 #define  SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED (1 << 1)
379395 #define  SOR_INPUT_CONTROL_HDMI_SRC_SELECT(x) (((x) & 0x1) << 0)
380396 
397
+#define SOR_AUDIO_CNTRL 0xfc
398
+#define  SOR_AUDIO_CNTRL_INJECT_NULLSMPL (1 << 29)
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+#define  SOR_AUDIO_CNTRL_SOURCE_SELECT(x) (((x) & 0x3) << 20)
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+#define   SOURCE_SELECT_MASK 0x3
401
+#define   SOURCE_SELECT_HDA 0x2
402
+#define   SOURCE_SELECT_SPDIF 0x1
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+#define   SOURCE_SELECT_AUTO 0x0
404
+#define  SOR_AUDIO_CNTRL_AFIFO_FLUSH (1 << 12)
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+
406
+#define SOR_AUDIO_SPARE 0xfe
407
+#define  SOR_AUDIO_SPARE_HBR_ENABLE (1 << 27)
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+
409
+#define SOR_AUDIO_NVAL_0320 0xff
410
+#define SOR_AUDIO_NVAL_0441 0x100
411
+#define SOR_AUDIO_NVAL_0882 0x101
412
+#define SOR_AUDIO_NVAL_1764 0x102
413
+#define SOR_AUDIO_NVAL_0480 0x103
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+#define SOR_AUDIO_NVAL_0960 0x104
415
+#define SOR_AUDIO_NVAL_1920 0x105
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+
417
+#define SOR_AUDIO_HDA_CODEC_SCRATCH0 0x10a
418
+#define  SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID (1 << 30)
419
+#define  SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK 0xffff
420
+
421
+#define SOR_AUDIO_HDA_ELD_BUFWR 0x10c
422
+#define  SOR_AUDIO_HDA_ELD_BUFWR_INDEX(x) (((x) & 0xff) << 8)
423
+#define  SOR_AUDIO_HDA_ELD_BUFWR_DATA(x) (((x) & 0xff) << 0)
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+
425
+#define SOR_AUDIO_HDA_PRESENSE 0x10d
426
+#define  SOR_AUDIO_HDA_PRESENSE_ELDV (1 << 1)
427
+#define  SOR_AUDIO_HDA_PRESENSE_PD (1 << 0)
428
+
429
+#define SOR_AUDIO_AVAL_0320 0x10f
430
+#define SOR_AUDIO_AVAL_0441 0x110
431
+#define SOR_AUDIO_AVAL_0882 0x111
432
+#define SOR_AUDIO_AVAL_1764 0x112
433
+#define SOR_AUDIO_AVAL_0480 0x113
434
+#define SOR_AUDIO_AVAL_0960 0x114
435
+#define SOR_AUDIO_AVAL_1920 0x115
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+
437
+#define SOR_INT_STATUS 0x11c
438
+#define  SOR_INT_CODEC_CP_REQUEST (1 << 2)
439
+#define  SOR_INT_CODEC_SCRATCH1 (1 << 1)
440
+#define  SOR_INT_CODEC_SCRATCH0 (1 << 0)
441
+
442
+#define SOR_INT_MASK 0x11d
443
+#define SOR_INT_ENABLE 0x11e
444
+
381445 #define SOR_HDMI_VSI_INFOFRAME_CTRL 0x123
382446 #define SOR_HDMI_VSI_INFOFRAME_STATUS 0x124
383447 #define SOR_HDMI_VSI_INFOFRAME_HEADER 0x125
384448 
449
+#define SOR_HDMI_AUDIO_N 0x13c
450
+#define SOR_HDMI_AUDIO_N_LOOKUP (1 << 28)
451
+#define SOR_HDMI_AUDIO_N_RESET (1 << 20)
452
+
385453 #define SOR_HDMI2_CTRL 0x13e
386454 #define  SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4 (1 << 1)
387455 #define  SOR_HDMI2_CTRL_SCRAMBLE (1 << 0)