| .. | .. |
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| 25 | 25 | * Alex Deucher |
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| 26 | 26 | * Jerome Glisse |
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| 27 | 27 | */ |
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| 28 | | -#include <drm/drmP.h> |
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| 28 | + |
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| 29 | 29 | #include <drm/radeon_drm.h> |
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| 30 | 30 | #include "radeon.h" |
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| 31 | 31 | #include "radeon_trace.h" |
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| .. | .. |
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| 142 | 142 | list[0].preferred_domains = RADEON_GEM_DOMAIN_VRAM; |
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| 143 | 143 | list[0].allowed_domains = RADEON_GEM_DOMAIN_VRAM; |
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| 144 | 144 | list[0].tv.bo = &vm->page_directory->tbo; |
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| 145 | | - list[0].tv.shared = true; |
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| 145 | + list[0].tv.num_shared = 1; |
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| 146 | 146 | list[0].tiling_flags = 0; |
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| 147 | 147 | list_add(&list[0].tv.head, head); |
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| 148 | 148 | |
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| .. | .. |
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| 154 | 154 | list[idx].preferred_domains = RADEON_GEM_DOMAIN_VRAM; |
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| 155 | 155 | list[idx].allowed_domains = RADEON_GEM_DOMAIN_VRAM; |
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| 156 | 156 | list[idx].tv.bo = &list[idx].robj->tbo; |
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| 157 | | - list[idx].tv.shared = true; |
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| 157 | + list[idx].tv.num_shared = 1; |
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| 158 | 158 | list[idx].tiling_flags = 0; |
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| 159 | 159 | list_add(&list[idx++].tv.head, head); |
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| 160 | 160 | } |
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| .. | .. |
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| 188 | 188 | vm_id->last_id_use == rdev->vm_manager.active[vm_id->id]) |
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| 189 | 189 | return NULL; |
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| 190 | 190 | |
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| 191 | | - /* we definately need to flush */ |
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| 191 | + /* we definitely need to flush */ |
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| 192 | 192 | vm_id->pd_gpu_addr = ~0ll; |
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| 193 | 193 | |
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| 194 | 194 | /* skip over VMID 0, since it is the system VM */ |
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| .. | .. |
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| 296 | 296 | struct radeon_bo_va *bo_va; |
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| 297 | 297 | |
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| 298 | 298 | list_for_each_entry(bo_va, &bo->va, bo_list) { |
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| 299 | | - if (bo_va->vm == vm) { |
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| 299 | + if (bo_va->vm == vm) |
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| 300 | 300 | return bo_va; |
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| 301 | | - } |
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| 301 | + |
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| 302 | 302 | } |
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| 303 | 303 | return NULL; |
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| 304 | 304 | } |
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| .. | .. |
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| 323 | 323 | struct radeon_bo_va *bo_va; |
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| 324 | 324 | |
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| 325 | 325 | bo_va = kzalloc(sizeof(struct radeon_bo_va), GFP_KERNEL); |
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| 326 | | - if (bo_va == NULL) { |
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| 326 | + if (bo_va == NULL) |
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| 327 | 327 | return NULL; |
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| 328 | | - } |
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| 328 | + |
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| 329 | 329 | bo_va->vm = vm; |
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| 330 | 330 | bo_va->bo = bo; |
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| 331 | 331 | bo_va->it.start = 0; |
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| .. | .. |
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| 702 | 702 | if (ib.length_dw != 0) { |
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| 703 | 703 | radeon_asic_vm_pad_ib(rdev, &ib); |
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| 704 | 704 | |
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| 705 | | - radeon_sync_resv(rdev, &ib.sync, pd->tbo.resv, true); |
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| 705 | + radeon_sync_resv(rdev, &ib.sync, pd->tbo.base.resv, true); |
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| 706 | 706 | WARN_ON(ib.length_dw > ndw); |
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| 707 | 707 | r = radeon_ib_schedule(rdev, &ib, NULL, false); |
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| 708 | 708 | if (r) { |
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| .. | .. |
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| 830 | 830 | uint64_t pte; |
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| 831 | 831 | int r; |
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| 832 | 832 | |
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| 833 | | - radeon_sync_resv(rdev, &ib->sync, pt->tbo.resv, true); |
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| 834 | | - r = reservation_object_reserve_shared(pt->tbo.resv); |
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| 833 | + radeon_sync_resv(rdev, &ib->sync, pt->tbo.base.resv, true); |
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| 834 | + r = dma_resv_reserve_shared(pt->tbo.base.resv, 1); |
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| 835 | 835 | if (r) |
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| 836 | 836 | return r; |
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| 837 | 837 | |
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| .. | .. |
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| 911 | 911 | */ |
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| 912 | 912 | int radeon_vm_bo_update(struct radeon_device *rdev, |
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| 913 | 913 | struct radeon_bo_va *bo_va, |
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| 914 | | - struct ttm_mem_reg *mem) |
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| 914 | + struct ttm_resource *mem) |
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| 915 | 915 | { |
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| 916 | 916 | struct radeon_vm *vm = bo_va->vm; |
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| 917 | 917 | struct radeon_ib ib; |
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| .. | .. |
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| 942 | 942 | bo_va->flags &= ~RADEON_VM_PAGE_VALID; |
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| 943 | 943 | bo_va->flags &= ~RADEON_VM_PAGE_SYSTEM; |
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| 944 | 944 | bo_va->flags &= ~RADEON_VM_PAGE_SNOOPED; |
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| 945 | | - if (bo_va->bo && radeon_ttm_tt_is_readonly(bo_va->bo->tbo.ttm)) |
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| 945 | + if (bo_va->bo && radeon_ttm_tt_is_readonly(rdev, bo_va->bo->tbo.ttm)) |
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| 946 | 946 | bo_va->flags &= ~RADEON_VM_PAGE_WRITEABLE; |
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| 947 | 947 | |
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| 948 | 948 | if (mem) { |
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| 949 | | - addr = mem->start << PAGE_SHIFT; |
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| 950 | | - if (mem->mem_type != TTM_PL_SYSTEM) { |
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| 949 | + addr = (u64)mem->start << PAGE_SHIFT; |
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| 950 | + if (mem->mem_type != TTM_PL_SYSTEM) |
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| 951 | 951 | bo_va->flags |= RADEON_VM_PAGE_VALID; |
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| 952 | | - } |
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| 952 | + |
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| 953 | 953 | if (mem->mem_type == TTM_PL_TT) { |
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| 954 | 954 | bo_va->flags |= RADEON_VM_PAGE_SYSTEM; |
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| 955 | 955 | if (!(bo_va->bo->flags & (RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC))) |
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| .. | .. |
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| 1233 | 1233 | struct radeon_bo_va *bo_va, *tmp; |
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| 1234 | 1234 | int i, r; |
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| 1235 | 1235 | |
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| 1236 | | - if (!RB_EMPTY_ROOT(&vm->va.rb_root)) { |
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| 1236 | + if (!RB_EMPTY_ROOT(&vm->va.rb_root)) |
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| 1237 | 1237 | dev_err(rdev->dev, "still active bo inside vm\n"); |
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| 1238 | | - } |
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| 1238 | + |
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| 1239 | 1239 | rbtree_postorder_for_each_entry_safe(bo_va, tmp, |
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| 1240 | 1240 | &vm->va.rb_root, it.rb) { |
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| 1241 | 1241 | interval_tree_remove(&bo_va->it, &vm->va); |
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